CN104465346B - The method for forming grid - Google Patents
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- CN104465346B CN104465346B CN201310425760.2A CN201310425760A CN104465346B CN 104465346 B CN104465346 B CN 104465346B CN 201310425760 A CN201310425760 A CN 201310425760A CN 104465346 B CN104465346 B CN 104465346B
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- 238000000034 method Methods 0.000 title claims abstract description 38
- 239000000758 substrate Substances 0.000 claims abstract description 19
- 238000010926 purge Methods 0.000 claims abstract description 12
- 239000007789 gas Substances 0.000 claims description 39
- 235000012431 wafers Nutrition 0.000 claims description 15
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 claims description 12
- 230000015572 biosynthetic process Effects 0.000 claims description 12
- 229910052739 hydrogen Inorganic materials 0.000 claims description 12
- 239000001257 hydrogen Substances 0.000 claims description 12
- 239000000463 material Substances 0.000 claims description 11
- UFHFLCQGNIYNRP-UHFFFAOYSA-N Hydrogen Chemical compound [H][H] UFHFLCQGNIYNRP-UHFFFAOYSA-N 0.000 claims description 9
- 238000000151 deposition Methods 0.000 claims description 9
- 238000004518 low pressure chemical vapour deposition Methods 0.000 claims description 8
- VEXZGXHMUGYJMC-UHFFFAOYSA-N Hydrochloric acid Chemical compound Cl VEXZGXHMUGYJMC-UHFFFAOYSA-N 0.000 claims description 6
- IXCSERBJSXMMFS-UHFFFAOYSA-N hydrogen chloride Substances Cl.Cl IXCSERBJSXMMFS-UHFFFAOYSA-N 0.000 claims description 6
- 229910000041 hydrogen chloride Inorganic materials 0.000 claims description 6
- 229910052757 nitrogen Inorganic materials 0.000 claims description 6
- 230000008021 deposition Effects 0.000 claims description 5
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 5
- SCYULBFZEHDVBN-UHFFFAOYSA-N 1,1-Dichloroethane Chemical class CC(Cl)Cl SCYULBFZEHDVBN-UHFFFAOYSA-N 0.000 claims description 4
- YZCKVEUIGOORGS-OUBTZVSYSA-N Deuterium Chemical compound [2H] YZCKVEUIGOORGS-OUBTZVSYSA-N 0.000 claims description 4
- BLRPTPMANUNPDV-UHFFFAOYSA-N Silane Chemical compound [SiH4] BLRPTPMANUNPDV-UHFFFAOYSA-N 0.000 claims description 4
- 238000005229 chemical vapour deposition Methods 0.000 claims description 4
- 229910052805 deuterium Inorganic materials 0.000 claims description 4
- PZPGRFITIJYNEJ-UHFFFAOYSA-N disilane Chemical compound [SiH3][SiH3] PZPGRFITIJYNEJ-UHFFFAOYSA-N 0.000 claims description 4
- 229920005591 polysilicon Polymers 0.000 claims description 4
- 229910021417 amorphous silicon Inorganic materials 0.000 claims description 3
- 229910000077 silane Inorganic materials 0.000 claims description 3
- 239000007792 gaseous phase Substances 0.000 claims 1
- 239000000126 substance Substances 0.000 claims 1
- 239000012535 impurity Substances 0.000 abstract description 24
- 230000007547 defect Effects 0.000 abstract description 16
- 239000004065 semiconductor Substances 0.000 description 16
- 238000002955 isolation Methods 0.000 description 6
- 238000004519 manufacturing process Methods 0.000 description 5
- 229910021654 trace metal Inorganic materials 0.000 description 5
- 229910021655 trace metal ion Inorganic materials 0.000 description 4
- 150000002431 hydrogen Chemical class 0.000 description 3
- 229910044991 metal oxide Inorganic materials 0.000 description 3
- 150000004706 metal oxides Chemical class 0.000 description 3
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 description 2
- FAPWRFPIFSIZLT-UHFFFAOYSA-M Sodium chloride Chemical compound [Na+].[Cl-] FAPWRFPIFSIZLT-UHFFFAOYSA-M 0.000 description 2
- 238000009825 accumulation Methods 0.000 description 2
- 238000001505 atmospheric-pressure chemical vapour deposition Methods 0.000 description 2
- 229910052799 carbon Inorganic materials 0.000 description 2
- 230000000295 complement effect Effects 0.000 description 2
- 239000013078 crystal Substances 0.000 description 2
- 238000005137 deposition process Methods 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 239000003989 dielectric material Substances 0.000 description 2
- 238000005530 etching Methods 0.000 description 2
- 150000002500 ions Chemical class 0.000 description 2
- 239000002243 precursor Substances 0.000 description 2
- 239000000376 reactant Substances 0.000 description 2
- 125000006850 spacer group Chemical group 0.000 description 2
- 229910007264 Si2H6 Inorganic materials 0.000 description 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- FKNQFGJONOIPTF-UHFFFAOYSA-N Sodium cation Chemical compound [Na+] FKNQFGJONOIPTF-UHFFFAOYSA-N 0.000 description 1
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 1
- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical compound [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 description 1
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 1
- 239000012159 carrier gas Substances 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
- 238000005660 chlorination reaction Methods 0.000 description 1
- 238000004140 cleaning Methods 0.000 description 1
- 229910021419 crystalline silicon Inorganic materials 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000007306 functionalization reaction Methods 0.000 description 1
- 229910000765 intermetallic Inorganic materials 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 230000006911 nucleation Effects 0.000 description 1
- 238000010899 nucleation Methods 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 230000001590 oxidative effect Effects 0.000 description 1
- -1 oxonium ion Chemical class 0.000 description 1
- 239000001301 oxygen Substances 0.000 description 1
- 229910052760 oxygen Inorganic materials 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 239000011780 sodium chloride Substances 0.000 description 1
- 229910001415 sodium ion Inorganic materials 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Electrodes Of Semiconductors (AREA)
Abstract
A kind of method for forming grid, including substrate is provided；Gate dielectric layer is formed in the substrate surface；Reducing gas is carried out to the gate dielectric layer surface to bake；The gate dielectric layer surface is purged；Grid layer is formed on purged gate dielectric layer surface；The graphical grid layer is to form grid.Technical scheme has advantages below：Reducing gas is carried out to the surface of substrate to bake and purge, is eliminated the impurity on the gate dielectric layer surface, is reduced the probability for producing bump defects in subsequent step when the gate dielectric layer surface forms grid layer.
Description
Technical field
The present invention relates to semiconductor fabrication, and in particular to a kind of method for forming grid.
Background technology
With the continuous innovation of ic manufacturing technology, the size of the various elements in integrated circuit constantly reduces, together
When functionalization density constantly increase.The ic manufacturing technology continued to develop under scaled principle improves production
Efficiency, reduce manufacturing cost；Meanwhile the problem of also bringing high power consumption.Pass through semiconductor of the application with low-power consumption feature
Device, for example, complementary metal oxide semiconductor（Complementary Metal Oxide Semiconductor,CMOS）
Device has relatively low power consumption.
Formed on the semiconductor device among the process of grid layer, bump defects are easily produced on grid layer（Bump
Defect）.
The method for forming grid for existing semiconductor devices as depicted in figs. 1 and 2, this method is before this in semiconductor device
Semiconductor material layer 4 is formed on the substrate 1 of part（As shown in Figure 1）, it is easy to produce on the semiconductor material layer 4 that this method is formed
Raw bump defects 3, and then with the bump defects 3 on the grid 5 for causing to eventually form（As shown in Figure 2）.
Because feature sizes of semiconductor devices diminishes, influence of the bump defects to semiconductor devices will become apparent from,
Especially influence whether the finished product yield of semiconductor devices；Now, the requirement for grid layer also uprises accordingly.
At the same time, to semiconductor devices used by the uniformity control of thickness, the thickness of wafer, size between wafer
Control and form the condition such as the temperature control of grid layer and require also to become more and more stricter.
The content of the invention
The present invention solves the problems, such as it is to reduce the probability that bump defects are produced when forming grid layer.
In order to solve the above-mentioned technical problem, the present invention provides a kind of method for forming grid, including：
Substrate is provided；
Gate dielectric layer is formed in the substrate surface；
Reducing gas is carried out to the gate dielectric layer surface to bake；
The gate dielectric layer surface is purged；
Grid layer is formed on purged gate dielectric layer surface；
The graphical grid layer is to form grid.
Optionally, the gate dielectric layer is made using high dielectric constant material.
Optionally, the step of reducing gas bakes includes：The gate dielectric layer surface is baked using hydrogen.
Optionally, the step of reducing gas bakes includes：The gate dielectric layer surface is baked using deuterium.
Optionally, the step of reducing gas bakes includes：Baking temperature is baked in 400~800 degrees Celsius of scope
Scope of the pressure in 0.1~700 support.
Optionally, the reducing gas bakes step and included：Nitrogen is mixed into the reducing gas.
Optionally, described the step of being purged to gate dielectric layer surface, includes：Using hydrogen chloride gas to gate dielectric layer
Surface is purged.
Optionally, described the step of being purged to gate dielectric layer surface, includes：Using dichloroethanes gas to gate medium
Layer surface is purged.
Optionally, described the step of being purged to gate dielectric layer surface, includes：Temperature is purged at 400~800 degrees Celsius
Scope.
Optionally, described the step of being purged to gate dielectric layer surface, includes：Purge model of the pressure in 0.1~700 support
Enclose.
Optionally, the step of formation grid layer includes：The grid layer is formed using silane.
Optionally, the step of formation grid layer includes：The grid layer is formed using disilane.
Optionally, the step of formation grid layer includes：The grid layer is formed by the method for chemical vapor deposition.
Optionally, the chemical vapor deposition is specially low-pressure chemical vapor deposition.
Optionally, in low-pressure chemical vapor deposition, scope of the depositing temperature at 450~750 degrees Celsius, deposition pressure exists
The scope of 0.1~300 support.
Optionally, the grid layer is formed on wafer, and described the step of forming grid layer includes：Respectively in single wafer
It is upper to form the grid layer.
Optionally, the grid layer is formed on wafer, and described the step of forming grid layer includes：Simultaneously in multiple wafers
It is upper to form the grid layer.
Optionally, the step of formation grid layer includes：Grid layer is formed on the wafer by boiler tube.
Optionally, the step of formation grid layer includes：The grid layer is polysilicon layer.
Optionally, the step of formation grid layer includes：The grid layer is amorphous silicon layer.
Compared with prior art, technical scheme has advantages below：
Reducing gas is carried out to gate dielectric layer surface to bake and purge, is eliminated on the gate dielectric layer surface
Impurity, reduce the probability for producing bump defects in subsequent step when the gate dielectric layer surface forms grid layer.
Further, the gate dielectric layer surface is baked using hydrogen or deuterium, the gate medium can be removed
The impurity such as the carbon of layer surface, oxygen.
Further, the gate dielectric layer surface is purged using hydrogen chloride gas or dichloroethanes gas, can be with
Remove the metal impurities on the gate dielectric layer surface.
Brief description of the drawings
Fig. 1 to Fig. 2 is the schematic diagram that prior art makes grid；
Fig. 3 to Fig. 8 is the schematic diagram for the embodiment of the method one formation grid that the present invention forms grid.
Embodiment
The existing method for making grid easily forms bump defects on grid layer, and main caused by the bump defects
One of reason is to remain impurity on the growing surface for forming grid layer.
During the grid layer is formed, on the growing surface of grid layer is formed, the bump defects form more
At the position for remaining impurity, reason is that the impurity of these residuals easily makes the nucleation speed of deposit accelerate and produce
Accumulation, and then produce the bump defects.
Further, the bump defects are by among the patterning step of the grid layer after bringing into so that ultimately form
Grid with described bump defects, had a strong impact on the performance of whole semiconductor devices.
In order to solve the above-mentioned technical problem, the present invention provide it is a kind of formed grid method, methods described generally comprise with
Lower step：
Step S1, there is provided substrate；
Step S2, gate dielectric layer is formed in the substrate surface；
Step S3, reducing gas is carried out to the gate dielectric layer surface and baked；
Step S4, the gate dielectric layer surface is purged；
Step S5, grid layer is formed on purged gate dielectric layer surface；
Step S6, the graphical grid layer is to form grid.
By above-mentioned steps, the impurity for remaining in the gate dielectric layer surface more can be thoroughly removed, to facilitate
Grid layer growth is stated, and then reduces the probability that the bump defects are produced when grid layer is formed in subsequent step.
It is understandable to enable the above objects, features and advantages of the present invention to become apparent, below in conjunction with the accompanying drawings to the present invention
Specific embodiment be described in detail.
Referring to Fig. 3, step S1 is performed, there is provided substrate 100.
In the present embodiment, the substrate 100 uses silicon substrate, and still, the substrate 100 can also partly be led using other
Body material, any restrictions are not done to this present invention.
In the present embodiment, in addition to it is following step by step：
In the substrate 100 by shallow-trench isolation technology (Shallow Trench Isolation, STI) processing, formed
Shallow trench isolation areas, the area of isolation is interior to be filled with spacer medium material 101, to form shallow groove isolation structure.
It should be noted that described be only used for providing condition, this hair to form semiconductor devices in the present embodiment step by step
It is bright not to be limited step by step to described, it can also be and directly carry out follow-up step without shallow-trench isolation.
With continued reference to Fig. 3, step S2 is performed, gate dielectric material is formed in the substrate surface；
After graphical to the gate dielectric material, part grid Jie for being covered in the top of spacer medium material 101 is removed
Material, and then obtain as shown in Figure 4, only covering the gate dielectric layer 110 on the surface of substrate 100.
In the present embodiment, the gate dielectric layer 110 is using the oxide material titanium nitride with high-k
（TiN）.But the gate dielectric layer 110 can also use the oxide material of other high-ks, the present invention is not done to this
Limitation.In addition, whether the present invention uses the material of high-k not also to be limited the gate dielectric layer 110.
As shown in figure 4, step S3, is baked, the reduction to the surface progress reducing gas 130 of the gate dielectric layer 110
The impurity of gas 130 and the remained on surface of gate dielectric layer 110 reacts, and is grid layer in subsequent step to remove these impurity
Growth provides a more clean surface.
The impurity is typically from the process equipment before forming substrate（Such as etching machine, cleaning machine）, or
Come from surrounding environment, the impurity mainly includes：
The impurity such as carbon, oxonium ion；
The surface of gate dielectric layer 110 is due to natural oxidizing layer caused by oxidation（native oxide）；
Trace metal（trace metal）The impurity such as ion and metal oxide.
In the present embodiment, the reducing gas 130 is hydrogen, and the good of the gate dielectric layer 110 is baked using hydrogen 130
It is in the hydrogen has stronger reproducibility and good carrier gas characteristic（Carrier Gas）, using hydrogen as also
Raw-gas, can be than more completely removing the above-mentioned impurity in the surface of gate dielectric layer 110.
But the reducing gas 130 is not limited in hydrogen, can also be such as deuterium（D2）The gas stronger etc. reproducibility
Body.
It should be noted that temperature is too low or too little pressure will cause reducing degree insufficient, and temperature it is too high or
Pressure is excessive, may influence whether substrate 100 and gate dielectric layer 110 characteristic of itself.Therefore, alternatively, temperature when baking
Degree is maintained at 400~800 degrees Celsius of scope, bakes the scope that pressure is maintained at 0.1~700 support,
Further, in the present embodiment, nitrogen can also be mixed into the hydrogen, the nitrogen can be used as protection
Gas, avoid the gate dielectric layer 110 from aoxidizing, or prevent from producing other impurities on the surface of gate dielectric layer 110.
In the present embodiment, the mixed proportion of the hydrogen and nitrogen is 1:2, the mixed gas using this ratio has
Relatively good reproducibility.But the present invention is not limited to mixed proportion, can also be other ratios, as hydrogen than nitrogen is
1:2 to 1:Any ratio between 19.
Reference picture 5, step S4 is performed, the surface of the gate dielectric layer 110 is purged using purge gas 140, with
Further remove the impurity for being attached to the surface of gate dielectric layer 110；These impurity are mainly some trace metal ion impurity,
These trace metal ion impurity react with the purge gas 140, are changed into metallic compound and by the purge gas 140
Take away, forming grid layer for subsequent step provides a more pure growing surface.
In the present embodiment, gate dielectric layer surface is purged using hydrogen chloride gas (HCL), with more quick thorough
The removal trace metal ion.The trace metal ion impurity and hydrogen chloride gas precursor reactant（For example, sodium ion and chlorination
Hydrogen precursor reactant generates sodium chloride）, and taken away by the hydrogen chloride gas.
But the present invention purge gas species is not limited, can also be it is other can be with the trace metal
The gas of ionic reaction such as dichloroethanes gas（DCE,Si2H2Cl2）.
In the present embodiment, 400~800 degrees Celsius of scope is maintained the temperature in purge, while keeps pressure
In the scope in 0.1~700 support, in order to more fully remove the trace metal for remaining in the surface of gate dielectric layer 110
Ion（trace metal）.
Especially, it should be noted that described carry out step S3 and the institute that reducing gas bakes to the gate dielectric layer surface
The order for stating the step S4 purged to the gate dielectric layer surface can be exchanged mutually, that is to say, that can first carry out step
Rapid S3, then perform step S4；Can also first carry out step S4, then perform step S3.
Because the purpose of the two steps is to remove the impurity on the surface of gate dielectric layer 110, two steps are exchanged
S3 and S4 order does not interfere with the formation of subsequent gate layer, does not interfere with yet and carries out impurity removal to the surface of gate dielectric layer 110
Effect.
As shown in fig. 6, performing step S5, formed on gate dielectric layer 110 surface purged through the purge gas 140
Grid layer.
In the present embodiment, the step of forming grid layer can be carried out in single-wafer.But in other embodiments
This can also not limited grid layer, the present invention as described in cvd furnace etc. is formed on multiple wafers simultaneously by batch instrument
System.
In the present embodiment, using silane（SiH4）Or disilane（Si2H6）Form the grid layer.
The grid layer of formation is polysilicon（Poly-Si）Grid layer forms the grid layer, and still, the present invention is to formation
Grid layer is not limited, and can also be non-crystalline silicon（a-Si）Other semi-conducting material grid layers such as grid layer.
In the present embodiment, the grid layer 120 is formed on single wafer respectively.But the present invention is not limited this
System, can also be and utilize batch instrument such as boiler tube（furnace）The grid layer 120 is formed on multiple wafers simultaneously.
With reference to reference to shown in figure 7, in the present embodiment, using low-pressure chemical vapor deposition（Low Pressure
Chemical Vapor Deposition,LPCVD）Method form the grid layer 120, energy is advantageous in that using LPCVD
Enough grid layers 120 with good stepcoverage performance and electrology characteristic formed under relatively low air pressure.
But the present invention is not limited for forming the deposition process of the grid layer, the grid layer 120 can also be
By Films Prepared by APCVD（Atmospheric,Pressure Chemical Vapor Deposition,APCVD）Deng it
Its deposition process is formed.
In the present embodiment, depositing temperature is maintained at 450~750 degrees Celsius of scope, and deposition pressure is maintained at 0.1~
The scope of 300 supports, carry out depositing the grid layer 120 for advantageously forming and being evenly distributed in the temperature and pressure range.
The pre- place for baking and purging due to having carried out reducing gas in above the step of to the surface of gate dielectric layer 110
Reason so that the remained on surface impurity of the gate dielectric layer 110 obtains more thoroughly removing, and then to form grid in deposition
During layer 120, the crystal grain 111 of polysilicon can be uniformly distributed on the surface of gate dielectric layer 110, and avoid and crystal grain 111 occurs
Between accumulation, and then form grid layer 120, make the probability with the bump defects on the grid layer 120 that finally obtains will
Significantly reduce.
It is shown in Figure 8, perform step S6, the graphical grid layer 120 is to form grid 121.
In the present embodiment, the grid layer 120 is etched using the method for anisotropic etching, to form the grid
121, the grid 121 formed in this way has more neat edge.
But the present invention does not do any restrictions to this, can also form the grid 121 using other graphic methods.
It is further to note that above step can be carried out in same chamber, can also enter respectively in different chamber
OK, the present invention is without limitation.
Although present disclosure is as above, the present invention is not limited to this.Any those skilled in the art, this is not being departed from
In the spirit and scope of invention, it can make various changes or modifications, therefore protection scope of the present invention should be with claim institute
The scope of restriction is defined.
Claims (19)
- A kind of 1. method for forming grid, it is characterised in that including：Substrate is provided；Gate dielectric layer is formed in the substrate surface；Reducing gas is carried out to the gate dielectric layer surface to bake；The gate dielectric layer surface is purged；Grid layer, scope of the purging temperature at 400~800 degrees Celsius are formed on purged gate dielectric layer surface；The graphical grid layer is to form grid.
- 2. the method as described in claim 1, it is characterised in that the gate dielectric layer is made using high dielectric constant material.
- 3. the method as described in claim 1, it is characterised in that the step of reducing gas bakes includes：Using hydrogen pair The gate dielectric layer surface is baked.
- 4. the method as described in claim 1, it is characterised in that the step of reducing gas bakes includes：Using deuterium pair The gate dielectric layer surface is baked.
- 5. the method as described in claim 3 or 4, it is characterised in that the step of reducing gas bakes includes：Baking temperature In 400~800 degrees Celsius of scope, scope of the pressure in 0.1~700 support is baked.
- 6. the method as described in claim 1, it is characterised in that the reducing gas, which bakes step, to be included：In the also Primordial Qi Nitrogen is mixed into body.
- 7. the method as described in claim 1, it is characterised in that described the step of being purged to gate dielectric layer surface includes： Gate dielectric layer surface is purged using hydrogen chloride gas.
- 8. the method as described in claim 1, it is characterised in that described the step of being purged to gate dielectric layer surface includes： Gate dielectric layer surface is purged using dichloroethanes gas.
- 9. method as claimed in claim 7 or 8, it is characterised in that described the step of being purged to gate dielectric layer surface wraps Include：Purge scope of the pressure in 0.1~700 support.
- 10. the method as described in claim 1, it is characterised in that described the step of forming grid layer includes：Formed using silane The grid layer.
- 11. the method as described in claim 1, it is characterised in that described the step of forming grid layer includes：Using disilane shape Into the grid layer.
- 12. the method as described in claim 1, it is characterised in that described the step of forming grid layer includes：Pass through chemical gaseous phase The method of deposition forms the grid layer.
- 13. method as claimed in claim 12, it is characterised in that the chemical vapor deposition is low-pressure chemical vapor deposition.
- 14. method as claimed in claim 13, it is characterised in that in low-pressure chemical vapor deposition, depositing temperature 450~ 750 degrees Celsius of scope, scope of the deposition pressure in 0.1~300 support.
- 15. the method as described in claim 1, it is characterised in that the grid layer is formed on wafer, the formation grid layer The step of include：The grid layer is formed on single wafer respectively.
- 16. the method as described in claim 1, it is characterised in that the grid layer is formed on wafer, the formation grid layer The step of include：The grid layer is formed on multiple wafers simultaneously.
- 17. method as claimed in claim 16, it is characterised in that described the step of forming grid layer includes：Existed by boiler tube Grid layer is formed on the wafer.
- 18. the method as described in claim 1, it is characterised in that described the step of forming grid layer includes：The grid layer is Polysilicon layer.
- 19. the method as described in claim 1, it is characterised in that described the step of forming grid layer includes：The grid layer is Amorphous silicon layer.
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| US7732263B2 (en) * | 2004-02-25 | 2010-06-08 | Semiconductor Energy Laboratory Co., Ltd | Semiconductor device |
| JP5395382B2 (en) * | 2007-08-07 | 2014-01-22 | 株式会社半導体エネルギー研究所 | Method for manufacturing a transistor |
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|---|---|---|---|---|
| CN1161569A (en) * | 1995-09-29 | 1997-10-08 | 日本电气株式会社 | Method for mfg. semiconductor device having oxide film of high quality on semiconductor substrate |
| CN102334194A (en) * | 2009-03-10 | 2012-01-25 | 杭州赛昂电力有限公司 | Heterojunction solar cell based on epitaxial crystalline-silicon thin film on metallurgical silicon substrate design |
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| CN104465346A (en) | 2015-03-25 |
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