CN104425338A - Method for improving the narrow width effect of shallow trench isolation structure - Google Patents

Method for improving the narrow width effect of shallow trench isolation structure Download PDF

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Publication number
CN104425338A
CN104425338A CN201310365515.7A CN201310365515A CN104425338A CN 104425338 A CN104425338 A CN 104425338A CN 201310365515 A CN201310365515 A CN 201310365515A CN 104425338 A CN104425338 A CN 104425338A
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CN
China
Prior art keywords
shallow trench
isolation structure
narrow width
material layer
width effect
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CN201310365515.7A
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Chinese (zh)
Inventor
赵猛
洪中山
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Semiconductor Manufacturing International Shanghai Corp
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Semiconductor Manufacturing International Shanghai Corp
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Priority to CN201310365515.7A priority Critical patent/CN104425338A/en
Publication of CN104425338A publication Critical patent/CN104425338A/en
Pending legal-status Critical Current

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/30604—Chemical etching
    • H01L21/30608—Anisotropic liquid etching
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/3065—Plasma etching; Reactive-ion etching

Abstract

The invention provides a method for improving the narrow width effect of a shallow trench isolation structure. The method comprises the steps of providing a semiconductor substrate including a first material layer and a second material layer, sequentially forming an oxide layer and a nitride layer, carrying out etching for the first time to form a first shallow trench isolation groove in the nitride layer, the oxide layer, the first material layer and the second material layer, etching the second material layer for the second time in the first shallow trench isolation groove to form a second shallow trench isolation groove, filling the second shallow trench isolation groove with isolation material, and removing the nitride layer to form a shallow trench isolation structure. By etching the second material layer for the second time, on the premise of ensuring that the effective area of a source/drain region remains unchanged, the bottom width of the shallow trench isolation structure is increased, the isolation effect of the shallow trench isolation structure is improved, the threshold voltage of semiconductor devices is improved to a certain extent, and thus the performance of semiconductor devices is enhanced.

Description

Improve the method for isolation structure of shallow trench narrow width effect
Technical field
The present invention relates to IC manufacturing field, particularly a kind of method improving isolation structure of shallow trench narrow width effect.
Background technology
Isolation between each element of semiconductor device is normally realized by localized oxidation of silicon (LOCOS) and shallow trench isolation (Shallow Trench Isolation, STI).
In both, LOCOS method simple to operate, and wide isolated film and narrow isolated film can be formed simultaneously.But in LOCOS method, limit oxidation can form unfirmly closing type etched figures (bird break), thus makes area of isolation broaden, and causes the effective area of source/drain region to reduce.And, in LOCOS method, depend on that the stress of difference between thermal coefficient of expansion focuses on the edge of sull in the forming process of territory sull, cause forming crystal defect on a silicon substrate and causing a large amount of leakage of current.
Therefore, shallow trench isolation technology is absolutely necessary.Shallow trench isolation has the features such as excellent isolation performance, smooth surface configuration, good anti-locking performance, the erosion of almost nil field, less leakage current and junction capacitance, has now become the main flow isolation technology of process for fabrication of semiconductor device.
The main technological steps of traditional formation isolation structure of shallow trench comprises:
Step 01: provide Semiconductor substrate 100, described Semiconductor substrate 100 forms oxide layer 101 and nitration case 102 successively, as shown in Figure 1a.
Step 02: etch described nitration case 102, oxide layer 101 and part semiconductor substrate 100 successively and form shallow trench isolation groove 103, as shown in Figure 1 b.
Adopt the shallow trench isolation groove 103 that dry etching and high-aspect-ratio technique (HARP) are formed, pattern can be V-arrangement wide at the top and narrow at the bottom or inverted trapezoidal.
Step 03: the method adopting chemical vapour deposition (CVD) or thermal oxidation, forms lining oxide layer 104 at described shallow trench isolation groove 103 inwall, forms shallow trench isolation groove 105, as illustrated in figure 1 c.
Step 04: adopt high-aspect-ratio technique or high density plasma CVD (HDPCVD) technique, insulating oxide 106 is filled in described shallow trench isolation groove 105, insulating oxide 106 described in planarization, and remove nitration case 102, form isolation structure of shallow trench, as shown in Figure 1 d.
Usually, in cmos device technique, the threshold voltage of device increases along with narrowing of channel width, i.e. narrow width effect (narrow width effect); But in shallow trench isolation technique, the threshold voltage of device reduces along with narrowing of channel width, be called anti-narrow width effect (reverse narrow width effect).Along with cmos device size constantly reduces, particularly enter into 65nm and with lower node, anti-narrow width effect has become the key factor of restriction small size device performance.
Summary of the invention
The invention provides a kind of method improving isolation structure of shallow trench narrow width effect, to solve reducing along with dimensions of semiconductor devices in prior art, the threshold voltage of semiconductor device reduces along with narrowing of channel width, thus affects the problem of performance of semiconductor device.
The method of raising isolation structure of shallow trench narrow width effect provided by the invention, comprising:
There is provided semi-conductive substrate, described Semiconductor substrate includes the first material layer and the second material layer;
Form oxide layer and nitration case successively on the semiconductor substrate;
Carry out first time etching, described nitration case, oxide layer, Semiconductor substrate first material layer and the second material layer are formed the first shallow trench isolation groove;
In described first shallow trench isolation groove, second time etching is carried out to described Semiconductor substrate second material layer, forms the second shallow trench isolation groove;
In described second shallow trench isolation groove, fill isolated material, and carry out planarization;
Remove described nitration case, form isolation structure of shallow trench.
Further, described Semiconductor substrate first material layer is different from the material of the second material layer.
Further, the material of described Semiconductor substrate first material layer is silicon, SiGe or carborundum.
Further, the material of described Semiconductor substrate second material layer is silicon, SiGe or carborundum.
Further, in described SiGe, the mol ratio of germanium is 0.2 ~ 0.45.
Further, in described carborundum, the mol ratio of carbon is 0.05 ~ 0.2.
Further, the thickness of described Semiconductor substrate first material layer is 20nm ~ 100nm.
Further, the thickness of described oxide layer is 100 ~ 400 .
Further, first time etches as wet etching.
Further, the second time etching of described silicon or SiGe is wet etching.
Further, hydrofluoric acid is adopted to carry out wet etching to silicon.
Further, acetic acid is adopted to carry out wet etching to SiGe.
Further, the second time etching of described carborundum is dry etching.
Further, using plasma carries out dry etching to carborundum
Further, the material of described oxide layer is silica, and the material of described nitration case is silicon nitride, and the material of described isolated material is silica.
Compared with prior art, the present invention has the following advantages:
1, the first material layer and the second material layer is included in Semiconductor substrate of the present invention, by carrying out second time etching to the second material layer, when ensureing that source/drain region effective area is constant, expand the width bottom isolation structure of shallow trench, add the isolation effect of isolation structure of shallow trench, improve the threshold voltage of semiconductor device to a certain extent, thus improve the performance of semiconductor device;
Meanwhile, when isolation structure of shallow trench overall dimension is consistent, the effective area of source/drain region can be improved, thus improve the performance of semiconductor device within the specific limits;
2, technical process method of the present invention is simple, can melt mutually with traditional shallow trench isolation related process, only need increase and once etch, just can realize good shallow trench isolation, and the technology that identical equipment can be applied to lower node is produced, and reduces the renewal frequency of equipment.
Accompanying drawing explanation
Fig. 1 a ~ 1d is the structural representation forming isolation structure of shallow trench main technological steps in prior art.
The flow chart of the raising isolation structure of shallow trench narrow width effect method that Fig. 2 provides for one embodiment of the invention.
Each step structural representation of the raising isolation structure of shallow trench narrow width effect method that Fig. 3 a ~ 3f provides for one embodiment of the invention.
Embodiment
Be described in further details below in conjunction with the method for the drawings and specific embodiments to the raising isolation structure of shallow trench narrow width effect that the present invention proposes.According to the following describes and claims, advantages and features of the invention will be clearer, it should be noted that, accompanying drawing all adopts the form that simplifies very much and all uses non-ratio accurately, only for object that is convenient, the aid illustration embodiment of the present invention lucidly.
Core concept of the present invention is: include the first material layer and the second material layer in Semiconductor substrate, by carrying out second time etching to the second material layer of bottom, when ensureing that source/drain region effective area is constant, expand the width bottom isolation structure of shallow trench, add the isolation effect of isolation structure of shallow trench, improve the threshold voltage of semiconductor device to a certain extent, thus improve the performance of semiconductor device.
The method flow diagram of the raising isolation structure of shallow trench narrow width effect that Fig. 2 provides for one embodiment of the invention, as shown in Figure 2, a kind of method improving isolation structure of shallow trench narrow width effect that the present invention proposes, comprises the following steps:
Step S01: semi-conductive substrate is provided, described Semiconductor substrate includes the first material layer and the second material layer;
Step S02: form oxide layer and nitration case successively on the semiconductor substrate;
Step S03: carry out first time etching, described nitration case, oxide layer, Semiconductor substrate first material layer and the second material layer are formed the first shallow trench isolation groove;
Step S04: in described first shallow trench isolation groove, carries out second time etching to described Semiconductor substrate second material layer, forms the second shallow trench isolation groove;
Step S05: fill isolated material in described second shallow trench isolation groove, and carry out planarization;
Step S06: remove described nitration case, forms isolation structure of shallow trench.
Each step structural representation of the raising isolation structure of shallow trench narrow width effect method that Fig. 3 a ~ 3f provides for one embodiment of the invention, please refer to shown in Fig. 2, and composition graphs 3a ~ Fig. 3 f, describe the method for the raising isolation structure of shallow trench narrow width effect that the present invention proposes in detail:
Step S01: provide semi-conductive substrate 200, described Semiconductor substrate includes the first material layer 202 and the second material layer 201, as shown in Figure 3 a.
In the present embodiment, the material of described first material 202 is silicon (Si), SiGe (SiGe) or carborundum (SiC), the material of described second material layer 201 is silicon, SiGe or carborundum, and the first selected material layer 202 is different from the material of the second material layer 201.In described SiGe, the mol ratio of germanium is 0.2 ~ 0.45, such as 0.2,0.25,0.3,0.35,0.4,0.45, and wherein, preferably mol ratio is 0.3; In described carborundum, the mol ratio of carbon is 0.05 ~ 0.2, such as 0.05,0.1,0.15,0.2, and wherein preferably mol ratio is 0.1.
The thickness of the first material 202 in described Semiconductor substrate 200 is 20nm ~ 100nm, such as 20nm, 40nm, 60nm, 80nm, 100nm, and preferably thickness is 60nm; The bottom of the isolation structure of shallow trench manufactured in subsequent technique is arranged in described second material layer 201; Described Semiconductor substrate 200 can only include the first material layer 201 and the second material layer 202, also the 3rd material layer can be comprised, be positioned at the bottom of described second material layer, can be silicon substrate, germanium silicon substrate or silicon-on-insulator (SOI), or well known to a person skilled in the art other Semiconductor substrate.
Step S02: form oxide layer 203 and nitration case 204 successively in described Semiconductor substrate 200, as shown in Figure 3 b.
Can form oxide layer 203 by thermal oxidation method on semiconductor substrate 200, other method also can be adopted to be formed, described oxide layer 203 can be silica.The thickness of described oxide layer 203 is 100 ~ 400 , such as 100 , 200 , 300 , 400 , preferably thickness is 300 .
Afterwards, low-pressure chemical vapor deposition or plasma ion assisted deposition method can be adopted in oxide layer 203 to form nitration case 204, for protecting oxide layer 203 in subsequent etching process, described nitration case 204 can be silicon nitride.
Step S03: carry out first time etching, to form the first shallow trench isolation groove 205 on described nitration case 204, oxide layer 203, Semiconductor substrate first material layer 202 and the second material layer 201, as shown in Figure 3 c.
In this step, first spin coating photoresist layer (not shown), then after exposure imaging is carried out to described photoresist layer, define the first shallow trench isolation groove.Then with patterned photoresist layer for mask, adopt wet etching etch described nitration case 204, oxide layer 203, Semiconductor substrate first material layer 202 and the second material layer 201 successively, to form the first shallow trench isolation groove 205.
Step S04: in described first shallow trench isolation groove 205, carries out second time etching to described Semiconductor substrate second material layer 201, forms the second shallow trench isolation groove 206, as shown in Figure 3 d.
In the present embodiment, second time etching, according to the difference of described second layer material 201 material, takes different lithographic methods.The material of described second layer material 201 be silicon or SiGe time, adopt wet etching, such as, adopt hydrofluoric acid to carry out wet etching to silicon, adopt acetic acid to carry out wet etching to SiGe, also can adopt and well known to a person skilled in the art other lithographic method.When the material of described second layer material 201 is carborundum, adopt dry etching, such as using plasma carries out dry etching to carborundum, can certainly adopt other known lithographic method.
Second time etching expands the bottom width of the first shallow trench isolation groove, finally expand the bottom width of isolation structure of shallow trench, but there is no the etching size of change first material layer, namely in the size not changing isolation structure of shallow trench top layer, when ensureing that source/drain region effective area is constant, add the isolation effect of isolation structure of shallow trench, improve the threshold voltage of semiconductor device to a certain extent, thus improve the performance of semiconductor device.Meanwhile, when isolation structure of shallow trench overall dimension is consistent, the effective area of source/drain region can be improved, thus improve the performance of semiconductor device within the specific limits.
Step S05: fill isolated material 207 in described second shallow trench isolation groove 206, and carry out planarization, as shown in Figure 3 e.
The isolated material be used in shallow trench isolation that deposition is conventional in the second shallow trench isolation groove 206, to obtain the spacer material layer 207 filling up the second shallow trench isolation groove 206, such as, isolated material can selective oxidation silicon, or well known to a person skilled in the art other isolated material.Then, the method for cmp is adopted to carry out planarization to described spacer material layer, to described nitration case 204 top.In other embodiments, other method also can be adopted to carry out planarization.
Step S06: remove described nitration case 204, forms isolation structure of shallow trench, as illustrated in figure 3f.
Adopt wet etching to remove described nitration case 204, in the present embodiment, adopt phosphoric acid solution to remove described nitration case 204, in described phosphoric acid solution, the mass percent of phosphoric acid is 80% ~ 90%, and the rate of etch of described phosphoric acid is 45 ~ 55 / min, in above-mentioned scope, the concentration of described phosphoric acid solution will make rate of etch too fast and wayward because concentration is excessive, avoid concentration too small simultaneously, rate of etch can be made comparatively slow and reduce make efficiency.In other embodiments, different etching liquids or different lithographic method etch nitride layers 204 can be adopted.
In sum, the first material layer and the second material layer is included in Semiconductor substrate of the present invention, by carrying out second time etching to the second material layer, when ensureing that source/drain region effective area is constant, expand the width bottom isolation structure of shallow trench, add the isolation effect of isolation structure of shallow trench, improve the threshold voltage of semiconductor device to a certain extent, thus improve the performance of semiconductor device; Meanwhile, when isolation structure of shallow trench overall dimension is consistent, the effective area of source/drain region can be improved, thus improve the performance of semiconductor device within the specific limits; Technical process method of the present invention is simple, can melt mutually with traditional shallow trench isolation related process, only need increase and once etch, just can realize good shallow trench isolation, and the technology that identical equipment can be applied to lower node is produced, and reduces the renewal frequency of equipment.
Foregoing description is only the description to present pre-ferred embodiments, any restriction not to the scope of the invention, and any change that the those of ordinary skill in field of the present invention does according to above-mentioned disclosure, modification, all belong to the protection range of claims.

Claims (15)

1. improve a method for isolation structure of shallow trench narrow width effect, it is characterized in that, comprising:
There is provided semi-conductive substrate, described Semiconductor substrate includes the first material layer and the second material layer;
Form oxide layer and nitration case successively on the semiconductor substrate;
Carry out first time etching, described nitration case, oxide layer, Semiconductor substrate first material layer and the second material layer are formed the first shallow trench isolation groove;
In described first shallow trench isolation groove, second time etching is carried out to described Semiconductor substrate second material layer, forms the second shallow trench isolation groove;
In described second shallow trench isolation groove, fill isolated material, and carry out planarization;
Remove described nitration case, form isolation structure of shallow trench.
2. the method improving isolation structure of shallow trench narrow width effect as claimed in claim 1, it is characterized in that, described Semiconductor substrate first material layer is different from the material of the second material layer.
3. the method improving isolation structure of shallow trench narrow width effect as claimed in claim 2, it is characterized in that, the material of described Semiconductor substrate first material layer is silicon, SiGe or carborundum.
4. the method improving isolation structure of shallow trench narrow width effect as claimed in claim 3, it is characterized in that, the material of described Semiconductor substrate second material layer is silicon, SiGe or carborundum.
5. the method improving isolation structure of shallow trench narrow width effect as claimed in claim 4, it is characterized in that, in described SiGe, the mol ratio of germanium is 0.2 ~ 0.45.
6. the method improving isolation structure of shallow trench narrow width effect as claimed in claim 4, it is characterized in that, in described carborundum, the mol ratio of carbon is 0.05 ~ 0.2.
7. the method improving isolation structure of shallow trench narrow width effect as claimed in claim 1, it is characterized in that, the thickness of described Semiconductor substrate first material layer is 20nm ~ 100nm.
8. the method improving isolation structure of shallow trench narrow width effect as claimed in claim 1, it is characterized in that, the thickness of described oxide layer is 100 ~ 400 .
9. the method improving isolation structure of shallow trench narrow width effect as claimed in claim 1, is characterized in that, described first time etches as wet etching.
10. the method improving isolation structure of shallow trench narrow width effect as claimed in claim 4, is characterized in that, the second time etching of described silicon or SiGe is wet etching.
11. methods improving isolation structure of shallow trench narrow width effect as claimed in claim 10, is characterized in that, adopt hydrofluoric acid to carry out wet etching to silicon.
12. methods improving isolation structure of shallow trench narrow width effect as claimed in claim 10, is characterized in that, adopt acetic acid to carry out wet etching to SiGe.
13. methods improving isolation structure of shallow trench narrow width effect as claimed in claim 4, is characterized in that, the second time etching of described carborundum is dry etching.
14. methods improving isolation structure of shallow trench narrow width effect as claimed in claim 13, it is characterized in that, using plasma carries out dry etching to carborundum.
15. as the method for the raising isolation structure of shallow trench narrow width effect in claim 1 to 14 as described in any one, and it is characterized in that, the material of described oxide layer is silica, and the material of described nitration case is silicon nitride, and the material of described isolated material is silica.
CN201310365515.7A 2013-08-20 2013-08-20 Method for improving the narrow width effect of shallow trench isolation structure Pending CN104425338A (en)

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Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2001043186A1 (en) * 1999-12-13 2001-06-14 Infineon Technologies North America Corp. Body contacted silicon-on-insulator (soi) structure and method of fabrication
US6787423B1 (en) * 2002-12-09 2004-09-07 Advanced Micro Devices, Inc. Strained-silicon semiconductor device
US20040262695A1 (en) * 2003-06-26 2004-12-30 International Business Machines Corporation Selective silicon-on-insulator isolation structure and method

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2001043186A1 (en) * 1999-12-13 2001-06-14 Infineon Technologies North America Corp. Body contacted silicon-on-insulator (soi) structure and method of fabrication
US6787423B1 (en) * 2002-12-09 2004-09-07 Advanced Micro Devices, Inc. Strained-silicon semiconductor device
US20040262695A1 (en) * 2003-06-26 2004-12-30 International Business Machines Corporation Selective silicon-on-insulator isolation structure and method

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Application publication date: 20150318