CN104424124B - Memory device, electronic equipment and the method for controlling memory device - Google Patents
Memory device, electronic equipment and the method for controlling memory device Download PDFInfo
- Publication number
- CN104424124B CN104424124B CN201310410041.3A CN201310410041A CN104424124B CN 104424124 B CN104424124 B CN 104424124B CN 201310410041 A CN201310410041 A CN 201310410041A CN 104424124 B CN104424124 B CN 104424124B
- Authority
- CN
- China
- Prior art keywords
- data
- read
- memory
- unit
- write
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Landscapes
- Memory System Of A Hierarchy Structure (AREA)
- Read Only Memory (AREA)
Abstract
Provide a kind of memory device, electronic equipment and the method for controlling the memory device.The memory device includes：Block storage unit, including multiple memory blocks, each memory block includes multiple pages, which performs the read-write of data as unit of the page；Mapping control unit, receive for perform data read-write order, and mapping relations are established between memory address for the data to be read and write and its storage address in block storage unit, and based on the read-write of mapping relations control data；Buffer unit caches the data to be read and write according to the control of mapping control unit, so as to perform the reading and writing data of described piece of storage unit as unit of the page；Memory interface, for the mapping control unit and buffer unit to be connected to the processing unit.In technical solution according to embodiments of the present invention, the cost of memory device can be reduced, truly reflects memory size to user and does not increase processing load.
Description
Technical field
The present invention relates to information technology field, more particularly, to a kind of memory device, the electronics including the memory device
Equipment and the method for controlling the memory device.
Background technology
Memory is the important component of electronic equipment.By taking electronic equipment is computer as an example, memory is for temporarily storage
Central processing unit（CPU）In operational data and the data that are exchanged with external memories such as hard disks.It is run in computer
When, CPU will carry out operation the data of operation is needed to be transferred in memory, and CPU again sends out result after the completion of operation.
Therefore, influence of the performance of memory to computer is very big.
In existing technology, using based on random access memory（RAM）The various storage unit conducts developed
Memory, but DRAM price costliness that should be based on random access memory so that the cost of electronic equipment is higher.It is in addition, existing
Also there are a kind of virtual memory techniques to improve internal memory performance in technology, and the virtual memory techniques are in the external storage of electronic equipment
Paging file is established in device（paging file）, and exchange to come with the page of external memory in memory by using CPU controls
Partial data in memory is stored in the paging file, to extend the capacity of memory.However, the virtual memory skill
Art increases the processing load of CPU, and since the capacity of the paging file in external memory is not calculated as memory
Capacity, therefore the visible memory size of user is less than the actual measured results of memory.
Therefore, it is desirable to there are a kind of low cost, the memory of the visible large capacity of user, and it is desirable that it does not increase the place of CPU
Reason load.
Invention content
It is described an embodiment of the present invention provides a kind of memory device, the electronic equipment including the memory device and for controlling
The method of memory device can reduce the cost of memory device, truly reflect memory size to user and not increase place
Reason load.
On the one hand, a kind of memory device is provided, for including the electronic equipment of processing unit, which is connected to
The memory device, the memory device may include：Block storage unit, including multiple memory blocks, each memory block includes multiple pages,
The block storage unit performs the read-write of data as unit of the page；Mapping control unit receives the read-write for performing data
Order, and mapping is established between memory address for the data to be read and write and its storage address in memory device and is closed
System, and based on the read-write of mapping relations control data；Buffer unit will be read and write according to the control of mapping control unit to cache
Data, so as to perform the reading and writing data of described piece of storage unit as unit of the page；Memory interface, for the mapping to be controlled
Unit and buffer unit processed are connected to the processing unit, to transmit the order and data of the processing unit.
In the memory device, the mapping control unit may include：Static RAM, for preserving
Mapping relations are stated, so as to improve the control efficiency of the mapping control unit.
In the memory device, the buffer unit can be cache memory.
In the memory device, the mapping control unit can be when receiving the order for reading data, first
Whether in the cache the data to be read are determined, if in cache memory, from caches
The data to be read described in being obtained in device, to be sent out via memory interface.
In the memory device, the buffer unit can be the part using dynamic random access memory come shape
Into cache memory, the remainder of the dynamic random access memory is by the additional storage as the memory device
Unit, to cooperate to carry out reading and writing data with described piece of storage unit.
In the memory device, the mapping control unit can be when receiving the order for reading data, first
The data to be read are determined whether in the additional memory unit, if the data to be read are in the additional memory unit
In, then the data to be read are obtained from the additional memory unit；If the data to be read are not in the additional memory unit
In, it is determined that the data to be read whether in the cache, if in cache memory, from speed buffering
The data to be read described in being obtained in memory, to be sent out via memory interface.
In the memory device, described piece of storage unit can be based on made of optimization flash memory, the optimization flash memory
Read or write speed is more than single layer cell flash memory, and its erasable number is more than single layer cell flash memory.
On the other hand, a kind of electronic equipment is provided, including processing unit and any one memory device as described above.
On the other hand, a kind of method for controlling memory device is provided, the memory device may include that block storage is single
Member, memory interface, the buffer unit being used cooperatively with the block storage unit, described piece of storage unit include multiple memory blocks, respectively
A memory block includes multiple pages, which performs the read-write of data as unit of the page, which is used for
The memory device is connected to processing unit, the method may include：In the memory address for the data to be read and write with wanting
The data of read-write establish mapping relations between the storage address in internal storage location；It is connect via the memory interface from processing unit
For receipts for performing the order of the read-write of data, which includes the memory address for the data to be read and write；Based on the mapping
Relationship determines the storage address of the data to be read and write；The data to be read and write are performed via the memory interface in the storage
The read-write in address is deposited, wherein, when identified storage address is described piece of access unit address, by means of the caching
Unit performs read-write of the data to be read and write in the storage address.
Described in controlling the method for memory device, the memory device to may also include：Static random access memory
Device, for store the memory address and it is described storage address between mapping relations, so as to improve using the mapping relations into
The efficiency of row operation.
Described in controlling the method for memory device, the buffer unit can be cache memory.
Described in controlling the method for memory device, the reading for reading data to be received from the processing unit
During order, it is described the data to be read and write are determined based on the mapping relations storage address the step of may include：It first determines to read
In the cache whether the data taken；If the data to be read are not in the cache, really
Surely the data to be read are in described piece of storage unit, and storage of the data to be read in described piece of storage unit described in acquisition
Deposit address.It is described the data to be read and write are performed via the memory interface in the storage address read-write the step of
It may include：If it is determined that the data to be read are in the cache, then institute is obtained from cache memory
The data to be read are stated, and are sent out via memory interface.
Described in controlling the method for memory device, the buffer unit can utilize dynamic random access memory
A part for device is come the cache memory formed, and the remainder of the dynamic random access memory is by as the memory
The additional memory unit of device, to cooperate to carry out reading and writing data with described piece of storage unit.
Described in controlling the method for memory device, the reading for reading data to be received from the processing unit
During order, it is described the data to be read and write are determined based on the mapping relations storage address the step of may include：It is reflected based on described
Whether the relationship of penetrating determines the data to be read in the additional memory unit；If the data to be read are not deposited in described add
In storage unit, it is determined that in the cache whether the data to be read；If the data to be read are not in the height
In fast buffer storage, it is determined that the data to be read are in described piece of storage unit.It is described to be held via the memory interface
The data to be read and write described in row it is described storage address in read-write the step of may include：If it is determined that the data to be read are in institute
It states in additional memory unit, then the data to be read described in acquisition from the additional memory unit, and being passed via memory interface
It sees off；If it is determined that the data to be read are in the cache, then institute is obtained from cache memory
The data to be read are stated, and are sent out via memory interface.
Described in controlling the method for memory device, described piece of storage unit can be made of based on optimization flash memory
, the read or write speed of the optimization flash memory is more than single layer cell flash memory, and its erasable number is more than single layer cell flash memory.
Memory device in the embodiment of the present invention, the electronic equipment including the memory device and for the memory to be controlled to fill
In the method put, the cost of memory device can be reduced to form internal storage location by using block storage unit, by via
Memory interface docks with outside and truly can reflect memory size to user, and closed by performing mapping in memory device
The maintenance of system is without increasing processing load.
Description of the drawings
It in order to illustrate the technical solution of the embodiments of the present invention more clearly, below will be in embodiment or description of the prior art
Required attached drawing is briefly described, it should be apparent that, the accompanying drawings in the following description is only some realities of the present invention
Example is applied, it for those of ordinary skill in the art, without creative efforts, can also be according to these attached drawings
Obtain other attached drawings.
Fig. 1 is the block diagram for schematically illustrating memory device according to embodiments of the present invention；
Fig. 2 is the block diagram for schematically illustrating memory device according to another embodiment of the present invention；
Fig. 3 is the block diagram for schematically illustrating electronic equipment according to embodiments of the present invention；
Fig. 4 is to schematically illustrate the flow chart for being used to control the method for memory device according to embodiments of the present invention；
Fig. 5 is schematically illustrated according to embodiments of the present invention for controlling in the method for memory device when receiving
The flow chart of performed operation during read command.
Specific embodiment
Below in conjunction with the attached drawing in the embodiment of the present invention, the technical solution in the embodiment of the present invention is carried out clear, complete
Site preparation describes, it is clear that described embodiment is part of the embodiment of the present invention, instead of all the embodiments.
Fig. 1 is the block diagram for schematically illustrating memory device 100 according to embodiments of the present invention.The memory device 100 can
Applied to various electronic equipments, including but not limited to intelligent telephone set, computer, personal digital assistant, Website server, document
Database or data storage server etc., the concrete type of electronic equipment are not construed as limiting the invention.Typically, the electricity
Sub- equipment may include the processing unit of such as central processing unit etc, so as to memory device 100 send out it is various order and with it is interior
Cryopreservation device 100 carries out data transmission.
The memory device 100 may include：Block storage unit 110, including multiple memory blocks, each memory block includes multiple
The page, the block storage unit perform the read-write of data as unit of the page；Mapping control unit 120 receives to perform number
According to read-write order, and built between memory address for the data to be read and write and its storage address in memory device
Vertical mapping relations, and based on the read-write of mapping relations control data；Buffer unit 130, according to the control of mapping control unit
The data to be read and write are cached, so as to perform the reading and writing data of described piece of storage unit as unit of the page；Memory interface 140,
For the mapping control unit and buffer unit to be connected to the processing unit, with transmit the order of the processing unit and
Data.
Described piece of storage unit 110 is typically solid state disk, and illustrated by taking solid state disk as an example below.But
It is the example of solid state disk only described piece of storage unit 110, it is impossible to any to have as the limitation to the embodiment of the present invention
The storage medium of the attribute of described herein piece of storage unit can serve as block storage unit 110.Solid state disk includes multiple
Memory block, each memory block include multiple pages, and each page generally includes multiple bytes.Using the page as list in solid state disk
Position performs the read-write of data.Solid state disk is often used as the hard disk of electronic equipment, and price is well below memory.Therefore,
Main memory unit by the use of block storage unit as the memory device 100 of such as solid state disk can greatly reduce memory device
Price.
Solid state disk is typically made of control unit and storage medium, which is, for example, flash memory（Flash）Or
Dynamic random access memory.With the development of technology, the performance of solid state disk also constantly upgrades.Such as one kind is developed now
Optimize flash memory, the read or write speed of the optimization flash memory is more than single layer cell flash memory, and its erasable number is more than single layer cell flash memory.
Therefore, more preferably performance is had when for memory device 100 based on described piece of storage unit 110 made of optimization flash memory.
The mapping control unit 120 for example from processing unit receive for perform data read-write order, the order
In be, for example, the data to be read and write specify the memory address in memory device, the memory address specified by the processing unit leads to
It is often the address set according to more generally applicable mechanism, is typically logical address.However, data are in memory device
Storage address is the address for the position that data are specifically stored in memory device, is, for example, physical address.The memory address
It is typically different, and therefore need to establish mapping relations between with the storage address, so as to the reading according to processing unit
It instructs and data is read from memory device and data are written to memory device according to the write command of processing unit.
Because the capacity of memory device 100 is gradually increasing, the processing complexity of processing unit is also being gradually increasing, so
The mapping relations that the mapping control unit 120 is established and managed are also relative complex.Moreover, it is such as deposited at random existing
In the memory device of access to memory, the read-write of data is carried out as unit of byte, i.e. the read write command of processing unit is with byte
For unit；However, in an embodiment of the present invention, carry out to perform block storage unit 110 read-write of data as unit of the page, this
Also the maintenance difficulties that mapping control unit 120 is directed to the mapping relations are further increased.It is single in order to improve mapping control
The control efficiency of member 120, the mapping control unit may include static RAM, be closed for preserving the mapping
System.Static RAM has the read or write speed of very block, and its content arbitrarily can read or be written on demand, and reads
The speed write is unrelated with the position of storage unit.Therefore, which can utilize the static random access memory
Device assists to manage the mapping relations between memory address and storage address, so as to improve control efficiency.
After the read/write address of the data to be read and write has been known according to the instruction of processing unit, based on the mapping relations
Storage address of the data in memory device of read-write is known to, so as to performing reading and writing data in the storage address.It closes
In the concrete operations for performing read-write, further described with reference to buffer unit 130.
Buffer unit 130 is used to cache the data to be read and write according to the control of mapping control unit, so as to using the page as
Unit performs the reading and writing data of described piece of storage unit.As previously mentioned, in existing memory device, carried out as unit of byte
The read write command of the read-write of data, i.e. processing unit is as unit of byte；However, in an embodiment of the present invention, with the page
To perform block storage unit 110 read-write of data for unit, and each page generally includes multiple bytes.That is, block
The reading and writing data granularity of storage unit 110 is more than the operation granularity of existing processing unit.Therefore, the buffer unit 130 is utilized
Described piece of storage unit 110 to be assisted to realize the read-write of data.The buffer unit 130 is typically cache memory,
E.g. dynamic random access memory（DRAM）, may be programmed read-only storage (PROM) etc..
When receiving the digital independent as unit of byte from processing unit, mapping control unit 120 carries out control as follows,
By in the digital independent to be read to the buffer unit 130 being stored in block storage unit as unit of the page, from page
Identified byte is read away to determine the required byte of processing unit in the data of unit caching in face.From
When reason unit receives the data write-in as unit of byte, mapping control unit 120 carries out control as follows, it is first determined with to write
The corresponding storage address using the page as unit of data entered, each page of the storage address can usually store portion
Divide the data of byte；Content in identified storage address is read by unit of the page in the buffer unit 130；It will
The byte to be written is written in buffer unit 130；The data in buffer unit 130 are written to block storage as unit of the page
In unit 110, which is included originally in the data of page storage and the data being written later.In addition, if with to be written
Data it is corresponding storage address each page in there is no data, the data that mapping control unit 120 can also will be written
It directly writes in block storage unit 110.It can be seen that although the read write command that memory device is received is as unit of byte
It is written and read, but read-write can also be realized in the block storage unit 110 as unit of the page using the buffer unit 130.
According to the description above for buffer unit 130 it is found that the minimum capacity of the buffer unit 130 is block storage unit
A page in 110.In use, if the capacity of buffer unit 130 is big, the reading of multiple pages can once be performed
It writes, so as to improve the operating efficiency of memory.In the case of the capacity of buffer unit 130 is larger, partial data is being written into
While to block storage unit 110, it may also be retained in the buffer unit 130.Correspondingly, it is described when reading data
Mapping control unit 120 can first determine the data to be read whether in buffer unit 130, if in buffer unit 130,
The data to be read are to send out described in being obtained from buffer unit 130；If the data to be read are not in buffer unit
130, then obtained from block storage unit 110 using buffer unit 130 as described above described in the data to be read to send out
It goes.It in this way, can be fully using the existing data storage capacities of buffer unit 130, to improve the read-write of memory device 100 effect
Rate.
The memory interface 140 is used to the mapping control unit 120 and buffer unit 130 being connected to the processing list
Member, to transmit the order and data of the processing unit.As previously mentioned, although the read write command that memory device is received is with word
It saves and is written and read for unit, but read-write can be realized in the block storage unit as unit of the page using the buffer unit.
That is, existing processing unit does not need to any change, it correspondingly can be real by the use of existing various memory interfaces as the present invention
Apply the memory interface 140 in example.For a user, which can be truly presented to it by the memory interface
100 capacity.It, should in the case where all told of the buffer unit 130 is used for the data of cache blocks storage unit 110
The capacity presented to user is the capacity of block storage unit 110；It is used for cache blocks in the portion capacity of the buffer unit 130
In the case of the data of storage unit 110, which is that the capacity of block storage unit 110 adds buffer unit
The residual capacity other than the portion capacity for being used for caching in 130.
In the technical solution of the memory device of the embodiment of the present invention, internal storage location is formed by using block storage unit
And the cost of memory device can be reduced, truly it can reflect that memory holds to user by being docked via memory interface with outside
Amount, and by handling load without increasing in the internal maintenance for performing mapping relations.
In order to more fully disclose the embodiment of the present invention, the other structures block diagram of memory device is described with reference to Fig. 2.
Fig. 2 is the block diagram for schematically illustrating memory device 200 according to another embodiment of the present invention.
In fig. 2, identical reference numeral has been used to represent the component units identical with Fig. 1.Block storage in Fig. 2 is single
Member 110, mapping control unit 120, buffer unit 130, memory interface 140 are identical with the corresponding part in Fig. 1, omit it here
Description.The difference lies in increase additional memory unit 150 with the memory device 100 of Fig. 1 for the memory device 200 of Fig. 2.It should
Additional memory unit 150 can be formed, such as can be deposited for synchronous dynamic random-access using existing various memory parts
Reservoir（SDRAM）, double data rate random access memory（DDR SDRAM）Deng the type of the additional memory unit 150 is not
Form the limitation to the embodiment of the present invention.Under the control of mapping control unit 120, which can be as existing
The same read-write processing for carrying out data at high speed of some memories.
It is the read-write operation in order to advanced optimize data to increase the additional memory unit 150.In existing electronic equipment
Operating process in, the capacity of required memory device is the process of a dynamic change, for example, for the daily of electronic equipment
Operation, may it is only necessary to 1 gigabyte (GB）Memory size；But when using electronic equipment come when playing game, Ke Nengxu
Want the memory size that 3GB is even more.It is as previously mentioned, usually single via caching when being written and read using block storage unit 110
Member 130 is handled, this reduces the read or write speed of data to a certain extent, although the reduction is limited.Here, inside
Cryopreservation device 200 includes the additional memory unit 150 to meet the routine request of processing unit.That is, required
Memory size hour, the read-write for carrying out data using the additional memory unit 150 in memory device 200；In required
When depositing capacity and becoming larger, using both the additional memory unit 150 in memory device 200 and block storage unit 110 come into line number
According to read-write, so as to also ensure the operating characteristics of memory device while the capacity for increasing memory device.
The additional memory unit 150 can be individual memory devices, can also be with 130 shared drive of buffer unit
Device.For example, the buffer unit 130 can be the speed buffering formed using a part for dynamic random access memory
Memory, and using the remainder of the dynamic random access memory as the additional memory unit 150 of memory device, with
It cooperates to carry out reading and writing data with described piece of storage unit 110.In addition, in the read-write for carrying out data, it is preferential to be deposited using additional
Storage unit 150, and when the additional memory unit 150 does not have free space, make the buffer unit 130 and block storage unit
110 carry out the read-write of data.As an example, when receiving the order for reading data, the mapping control unit exists
120 determine the data to be read whether in the additional memory unit 150 first, if the data to be read are described additional
In storage unit 150, then the data to be read are obtained from the additional memory unit 150, to be sent out via memory interface；
If the data to be read are not in the additional memory unit 150, it is determined that whether the data to be read deposit in speed buffering
In reservoir 130, if in cache memory 130, the data to be read described in acquisition from cache memory, with
It is sent out via memory interface.If the data to be read not in cache memory 130, can determine that this will read
Data in block storage unit 110, and from described piece of storage unit 110 obtain described in the data to be read, with via memory
Interface is sent out.
In memory device shown in Fig. 2, by being mixedly configured and using different types of storage unit, including described
Additional memory unit 150 and block storage unit 110, can ensure memory performance while reduce memory device cost,
Truly reflect memory size to user and do not increase processing load.
It is may be used in various types of electronic equipments above in conjunction with Fig. 1 and Fig. 2 each memory devices described.Accordingly
Ground, the electronic equipment including any of the above-described a memory device are also in the open scope of the embodiment of the present invention.Fig. 3 is signal
Property illustrates the block diagram of electronic equipment according to embodiments of the present invention.As shown in figure 3, the electronic equipment is including processing unit and such as
Upper any one described memory device.Using the memory device in the electronic equipment, can equally reduce memory device cost,
Truly loaded to the processing that user reflects memory size and does not increase processing unit.
Fig. 4 is to schematically illustrate the flow chart for being used to control the method 400 of memory device according to embodiments of the present invention.
The memory device may include block storage unit, memory interface, the buffer unit being used cooperatively with the block storage unit.Described piece
Storage unit may include multiple memory blocks, and each memory block includes multiple pages, which is held as unit of the page
The read-write of row data, the memory interface are used to the memory device being connected to processing unit.The memory device is used in electricity
Program, data needed for operation etc. are temporarily preserved in the operational process of sub- equipment.The concrete type of electronic equipment is not formed to this
The limitation of invention.
Described piece of storage unit is typically solid state disk, can also be the attribute with described herein piece of storage unit
Any other storage medium.Here it is described by taking solid state disk as an example.The price of solid state disk is well below memory.Cause
This, the main memory unit by the use of block storage unit as the memory device of such as solid state disk can greatly reduce memory device
Price.Solid state disk is typically made of control unit and storage medium, which is, for example, flash memory or dynamic random
Access memory.With the development of technology, the performance of solid state disk also constantly upgrades.Such as a kind of optimization is developed now and is dodged
It deposits, the read or write speed of the optimization flash memory is more than single layer cell flash memory, and its erasable number is more than single layer cell flash memory.Therefore,
More preferably performance is had when for memory device based on described piece of storage unit made of optimization flash memory.
Buffer unit is for caching the data to be read and write, so as to perform the data of described piece of storage unit as unit of the page
Read-write.In existing memory device, the read-write of data is carried out as unit of byte；However, in an embodiment of the present invention, with
The page to perform block storage unit the read-write of data for unit, and each page generally includes multiple bytes.That is, block
The reading and writing data granularity of storage unit is more than the operation granularity of existing processing unit.Therefore, it is assisted using the buffer unit
Described piece of storage unit realizes the read-write of data.The buffer unit is typically cache memory, e.g. dynamic with
Machine accesses memory（DRAM）, may be programmed read-only storage (PROM) etc..In addition, one using dynamic random access memory
Divide to form the buffer unit, and using the remainder of the dynamic random access memory as the additional of the memory device
Storage unit, to cooperate to carry out reading and writing data with described piece of storage unit.
The memory interface is the external connection interface of memory device, between the component outside memory device and its
Order and data.As previously mentioned, although the read write command that memory device is received is written and read as unit of byte, it is sharp
Read-write can be realized in the block storage unit as unit of the page with the buffer unit, existing processing unit does not need to be any
Change, it correspondingly can be by the use of existing various memory interfaces as the memory interface.By the memory interface can to
The capacity of the memory device is truly presented in family.The operation of memory device is described with reference to the flow chart of Fig. 4 and Fig. 5.
As shown in figure 4, described be used to that the method 400 of memory device to be controlled to may include：In for the data to be read and write
It deposits address and establishes mapping relations (S410) between storage address in internal storage location of the data to be read and write；Via the memory
From processing unit reception for performing the order of the read-write of data, which is included for the memory of the data to be read and write interface
Location (S420)；The storage address (S430) of the data to be read and write is determined based on the mapping relations；Come via the memory interface
Read-write of the data to be read and write described in execution in the storage address, wherein, when identified storage address is deposited for described piece
During the address of storage unit, read-write of the data to be read and write in the storage address is performed by means of the buffer unit
(S440)。
In S410, in the memory address for the data to be read and write and storage of the data to be read and write in internal storage location
Mapping relations are established between address.This is used for processing list of the memory address of the data to be read and write for example by communicating with memory interface
Specified by member, for example, be included in from processing unit receive for perform data the order of read-write in, which leads to
It is often the address set according to more generally applicable mechanism, is typically logical address.However, data are in memory device
Storage address is the address for the position that data are specifically stored in memory device, is, for example, that the data to be read and write store list in block
Physical address in member or buffer unit.The storage address is different from the memory address, and therefore needs to build between
Vertical mapping relations, so as to according to the reading instruction of data read from memory device data and according to the write command of processing unit to
Data are written in memory device.
Because the capacity of memory device is gradually increasing, the processing complexity of processing unit is also being gradually increasing, so institute
It establishes and the mapping relations of management is also relative complex.Moreover, in the memory device of existing such as random access memory
In, the read-write of data is carried out as unit of byte, i.e. the read write command of processing unit is as unit of byte；However, in this hair
In bright embodiment, carry out to perform block storage unit the read-write of data as unit of the page, this also further increases described reflect
Penetrate the maintenance difficulties of relationship.For the operating efficiency of raising, the memory device may include static RAM, be used for
Preserve the mapping relations.Static RAM has the read or write speed of very block, and its content can on demand arbitrarily
It reads or is written, and the speed read and write is unrelated with the position of storage unit.Therefore, the memory device can utilize it is described it is static with
Machine accesses memory to assist to manage the mapping relations between memory address and storage address, so as to improve operating efficiency.This
In static RAM it is only schematical, described in the storage that dynamic random access memory etc. can also be taken
Mapping relations.
In S420, via the memory interface from processing unit receive for perform data read-write order, the life
Enable the memory address included for the data to be read and write.As previously mentioned, existing various memory interfaces can be utilized as needed
As the memory interface, i.e., the existing processing unit with the memory interface does not need to be changed, so as to good
Compatibility.Via memory interface from processing unit receive described in for the data to be read and write memory address be typically according to
More generally applicable mechanism is typically logical address come the address set.It is interior that the memory address is that processing unit is understood
Deposit address.
In S430, the storage address of the data to be read and write is determined based on the mapping relations.According to processing unit
After the read/write address of the data to be read and write has been known in instruction, the data of read-write are known in memory based on the mapping relations
Storage address in device, so as to perform reading and writing data in the storage address.The storage address can be the number to be read and write
According in block storage unit address, can also be address of the data to be read and write in buffer unit.
In S440, reading of the data to be read and write in the storage address is performed via the memory interface
It writes, wherein, when identified storage address is described piece of access unit address, by means of the buffer unit to perform
State read-write of the data to be read and write in the storage address.S430 and S440 are described in conjunction with each other below, to be more clear
Ground illustrates the present invention.
As previously mentioned, buffer unit is assisted for temporarily storing the data to be read and write in block storage unit with block storage unit
Make to realize the read-write as unit of the page in block storage unit.Specifically, it is received as unit of byte from processing unit
Digital independent when, the storage addresses of the data to be read is determined in S430 as block access unit address, then in S440
It is middle that the data to be read being stored in block storage unit are stored in as unit of the page in the buffer unit, from the page
To determine the required byte of processing unit, and identified byte is read away in the data of unit caching.From processing
When unit receives the data write-in as unit of byte, determined in S430 according to mapping relations corresponding with the data to be written
It is, for example, block access unit address to store address；Then in S440 by it is identified storage address in content using the page for singly
Member is read in the buffer unit, and the byte that will be written is written to the corresponding position in buffer unit, then using the page as
Data in buffer unit are written in block storage unit by unit, the data include originally the page storage data and later
The data of write-in.In addition, in S440, if do not counted in each page of storage address corresponding with the data to be written
According to the data that can also will be written are directly write in block storage unit.It is deposited as it can be seen that the minimum capacity of the buffer unit is block
One page of storage unit.
In use, if the capacity of buffer unit is big, the read-write of multiple pages can be once performed, so as to improve
The operating efficiency of memory.In the case of the capacity of buffer unit is larger, partial data is being written to the same of block storage unit
When, it may also be retained in the buffer unit.Correspondingly, it when reading data, can first determine to read in the S430
Data whether in buffer unit, if in the buffer unit of such as cache memory, deposit receipt of postponing in S440
The data to be read are to send out described in being obtained in member；In S430, if the data to be read not in buffer unit, can
To determine the data to be read in described piece of storage unit, and determine storage of the data to be read in described piece of storage unit
Address is deposited, so as to which the data to be read described in being obtained from block storage unit in S440 are to send out.It in this way, can be abundant
Ground is using the existing data storage capacities of buffer unit, to improve the read-write efficiency of memory device.
Furthermore, it is possible to increase additional memory unit in memory.The additional memory unit can utilize existing various interior
Component is deposited to be formed, such as can be SDRAM, DDR SDRAM etc., the type of the additional memory unit is not formed to of the invention real
Apply the limitation of example.The additional memory unit can carry out the read-write processing of data at high speed as existing memory.Increasing should
Additional memory unit is the read-write operation in order to advanced optimize data.As previously mentioned, using block storage unit can with it is low into
The memory of this offer large capacity, but while being written and read using block storage unit usually to be handled via buffer unit, this
The read or write speed of data is reduced to a certain extent, although the reduction is limited.In the operation of existing electronic equipment
Cheng Zhong, the capacity of required memory device are the processes of a dynamic change.Therefore, in required memory size hour, utilization
The additional memory unit in memory device carries out the read-write of data；When required memory size becomes larger, filled using memory
Both the additional memory unit and block storage unit in putting carry out the read-write of data, so as in the appearance for increasing memory device
The operating characteristics of memory device is also ensured while amount.
The additional memory unit can be individual memory devices, can also be with the buffer unit shared drive device.
For example, the buffer unit can be the cache memory formed using a part for dynamic random access memory,
And using the remainder of the dynamic random access memory as the additional memory unit of memory device, to be deposited with described piece
Storage unit cooperates to carry out reading and writing data.It is illustrated with reference to Fig. 5.Fig. 5 is schematically illustrated according to the present invention
Embodiment for controlling the flow chart of operation performed when receiving read command in the method for memory device.
As an example, when receiving the order for reading data, determine that the data to be read are first in S431
It is no in the additional memory unit, if the data to be read are in the additional memory unit（In S431 is）, then exist
The data to be read are obtained in S441 from the additional memory unit, to be sent out via memory interface；If it to be read
Data are not in the additional memory unit（It is no in S431）, then determine whether the data to be read are slow in high speed in S432
It rushes in memory, if in cache memory（In S432 is）, then obtained from cache memory in S442
The data to be read, to be sent out via memory interface；If the data to be read are not in the cache
（It is no in S432）, then the data to be read are can determine in block storage unit, and are obtained the data to be read and stored in block
Storage address in unit（S443）, the data to be read described in reading from acquired storage address, with single using caching
Member is sent out via memory interface（S444）.Here, S431, S432 are each sub-steps in step S430, S441,
S442, S443, S444 are each sub-steps in step S440.In flow chart shown in Fig. 5, by being mixedly configured and making
With different types of storage unit, including the additional memory unit and block storage unit, it can ensure the performance of memory
The cost of memory device is reduced simultaneously.
In the case where all told of the buffer unit is used for the data of cache blocks storage unit, this is in user
Existing capacity is the capacity of block storage unit；It is used for the data of cache blocks storage unit in the portion capacity of the buffer unit
In the case of, this is cached to the capacity that the capacity that user is presented is block storage unit plus in buffer unit in addition to described
Portion capacity except residual capacity.Certainly, in the case where memory device further includes additional memory unit, memory size
Also to add the capacity of the additional memory unit.
In the embodiment of the present invention for controlling the technical solution of method of memory device in, by using block storage unit
The cost of memory device can be reduced forming internal storage location, by docked via memory interface with outside and can truly to
User reflects memory size, and by handling load without increasing in the internal maintenance for performing mapping relations.
It is apparent to those skilled in the art that the embodiment of the method for foregoing description is applied to memory dress
The structure put can refer to corresponding explanation and diagram in before-mentioned products embodiment；The equipment of foregoing description and unit it is specific
The course of work, can be with the corresponding process in reference method embodiment.
In several embodiments provided herein, it should be understood that disclosed device and method can pass through it
Its mode is realized.For example, the apparatus embodiments described above are merely exemplary, for example, the division of the unit, only
Only a kind of division of logic function can have other dividing mode in actual implementation, such as multiple units or component can be tied
It closes or is desirably integrated into another system or some features can be ignored or does not perform.In addition, in each implementation of the present invention
Each functional unit in example can be integrated in a processing unit or each unit is individually physically present, can also
Two or more units integrate in a unit.
The above description is merely a specific embodiment, but protection scope of the present invention is not limited thereto, any
Those familiar with the art in the technical scope disclosed by the present invention, can readily occur in change or replacement, should all contain
Lid is within protection scope of the present invention.Therefore, protection scope of the present invention described should be subject to the protection scope in claims.
Claims (15)
1. a kind of memory device, for including the electronic equipment of processing unit, which is connected to the memory device, this is interior
Cryopreservation device includes：
Block storage unit, including multiple memory blocks, each memory block includes multiple pages, and the block storage unit is as unit of the page
To perform the read-write of data；
Mapping control unit, receive for perform data read-write order, and for the memory address of the data to be read and write
Mapping relations are established between its storage address in memory device, and based on the read-write of mapping relations control data；
Buffer unit caches the data to be read and write, so as to perform institute as unit of the page according to the control of mapping control unit
State the reading and writing data of block storage unit；
Memory interface, for the mapping control unit and buffer unit to be connected to the processing unit, to transmit the place
Manage the order and data of unit；
Wherein, include described piece of storage unit and the buffer unit to the memory size that user is presented via the memory interface
The residual capacity in addition to the capacity for caching.
2. memory device according to claim 1, wherein, the mapping control unit includes：Static RAM is used
In preserving the mapping relations, so as to improve the control efficiency of the mapping control unit.
3. memory device according to claim 1, wherein, the buffer unit is cache memory.
4. memory device according to claim 3, wherein, the mapping control unit is receiving the order for reading data
When, first whether in the cache the data to be read are determined, if in cache memory, from speed buffering
The data to be read described in being obtained in memory, to be sent out via memory interface.
5. memory device according to claim 1, wherein, the buffer unit is one using dynamic random access memory
The cache memory for dividing to be formed, the remainder of the dynamic random access memory is by as the attached of the memory device
Loading/memorizing unit, to cooperate to carry out reading and writing data with described piece of storage unit.
6. memory device according to claim 5, wherein, the mapping control unit is receiving the order for reading data
When, the data to be read first are determined whether in the additional memory unit, if the data to be read are in the additional storage
In unit, then the data to be read are obtained from the additional memory unit；If the data to be read are not in the additional storage
In unit, it is determined that the data to be read whether in the cache, if in cache memory, from a high speed
The data to be read described in being obtained in buffer storage, to be sent out via memory interface.
7. memory device according to claim 1, wherein, described piece of storage unit is based on made of optimization flash memory, the optimization
The read or write speed of flash memory is more than single layer cell flash memory, and its erasable number is more than single layer cell flash memory.
8. a kind of electronic equipment, including：
Processing unit；With
Memory device as described in any one of claim 1 to 7.
9. a kind of method for controlling memory device, the memory device includes block storage unit, memory interface, is deposited with the block
The buffer unit that storage unit is used cooperatively, described piece of storage unit include multiple memory blocks, and each memory block includes multiple pages,
The block storage unit performs the read-write of data as unit of the page, which is used for memory device connection everywhere
Unit is managed, the method includes：
For being established between storage address in internal storage location of the memory address of the data to be read and write and the data to be read and write
Mapping relations；
Via the memory interface from processing unit reception for performing the order of the read-write of data, which includes reading
The memory address for the data write；
The storage address of the data to be read and write is determined based on the mapping relations；
Read-write of the data to be read and write in the storage address is performed via the memory interface,
Wherein, it when identified storage address is described piece of access unit address, is performed by means of the buffer unit
Read-write of the data to be read and write in the storage address；
Wherein, include described piece of storage unit and the buffer unit to the memory size that user is presented via the memory interface
The residual capacity in addition to the capacity for caching.
10. method according to claim 9, wherein, the memory device further includes：
Static RAM, for storing the mapping relations between the memory address and the storage address, so as to
Improve the efficiency operated using the mapping relations.
11. method according to claim 9, wherein, the buffer unit is cache memory.
12. method according to claim 11, wherein, the read command for reading data is being received from the processing unit
When, it is described the data to be read and write are determined based on the mapping relations storage address the step of include：
First whether in the cache to determine the data to be read；
If the data to be read are not in the cache, it is determined that the data to be read are single in described piece of storage
In member, and storage address of the data to be read in described piece of storage unit described in acquisition,
Wherein, the step of the data to be read and write are performed via the memory interface read-write in the storage address
Suddenly include：If it is determined that the data to be read are in the cache, then institute is obtained from cache memory
The data to be read are stated, and are sent out via memory interface.
13. method according to claim 9, wherein, the buffer unit is the part using dynamic random access memory
Come the cache memory formed, the remainder of the dynamic random access memory is by as the additional of the memory device
Storage unit, to cooperate to carry out reading and writing data with described piece of storage unit.
14. method according to claim 13, wherein, the read command for reading data is being received from the processing unit
When, it is described the data to be read and write are determined based on the mapping relations storage address the step of include：
Determine the data to be read whether in the additional memory unit based on the mapping relations；
If the data to be read are not in the additional memory unit, it is determined that whether the data to be read deposit in speed buffering
In reservoir；
If the data to be read are not in the cache, it is determined that the data to be read are single in described piece of storage
In member, and storage address of the data to be read in described piece of storage unit described in acquisition,
Wherein, the step of the data to be read and write are performed via the memory interface read-write in the storage address
Suddenly include：If it is determined that the data to be read in the additional memory unit, then obtain institute from the additional memory unit
The data to be read are stated, and are sent out via memory interface；If it is determined that the data to be read are in the caches
In device, then the data to be read described in acquisition from cache memory, and being sent out via memory interface.
15. method according to claim 9, wherein, described piece of storage unit is based on made of optimization flash memory, the optimization flash memory
Read or write speed be more than single layer cell flash memory, and its erasable number be more than single layer cell flash memory.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201310410041.3A CN104424124B (en) | 2013-09-10 | 2013-09-10 | Memory device, electronic equipment and the method for controlling memory device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201310410041.3A CN104424124B (en) | 2013-09-10 | 2013-09-10 | Memory device, electronic equipment and the method for controlling memory device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN104424124A CN104424124A (en) | 2015-03-18 |
| CN104424124B true CN104424124B (en) | 2018-07-06 |
Family
ID=52973158
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201310410041.3A Active CN104424124B (en) | 2013-09-10 | 2013-09-10 | Memory device, electronic equipment and the method for controlling memory device |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN104424124B (en) |
Families Citing this family (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104932991B (en) * | 2015-06-15 | 2018-08-28 | 上海新储集成电路有限公司 | A method of substituting mixing memory using afterbody hybrid cache |
| WO2020019173A1 (en) * | 2018-07-24 | 2020-01-30 | 华为技术有限公司 | Memory control circuit for object storage |
| CN111949203B (en) * | 2019-05-17 | 2024-03-01 | 兆易创新科技集团股份有限公司 | Memory, control method and control device thereof |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101552032A (en) * | 2008-12-12 | 2009-10-07 | 深圳市晶凯电子技术有限公司 | Method and device for constructing a high-speed solid state memory disc by using higher-capacity DRAM to join in flash memory medium management |
| CN103019955A (en) * | 2011-09-28 | 2013-04-03 | 中国科学院上海微系统与信息技术研究所 | Memory management method based on application of PCRAM (phase change random access memory) main memory |
| CN103092534A (en) * | 2013-02-04 | 2013-05-08 | 中国科学院微电子研究所 | Scheduling method and device for internal memory structure |
| CN103229155A (en) * | 2010-09-24 | 2013-07-31 | 德克萨斯存储系统股份有限公司 | High-speed memory system |
-
2013
- 2013-09-10 CN CN201310410041.3A patent/CN104424124B/en active Active
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101552032A (en) * | 2008-12-12 | 2009-10-07 | 深圳市晶凯电子技术有限公司 | Method and device for constructing a high-speed solid state memory disc by using higher-capacity DRAM to join in flash memory medium management |
| CN103229155A (en) * | 2010-09-24 | 2013-07-31 | 德克萨斯存储系统股份有限公司 | High-speed memory system |
| CN103019955A (en) * | 2011-09-28 | 2013-04-03 | 中国科学院上海微系统与信息技术研究所 | Memory management method based on application of PCRAM (phase change random access memory) main memory |
| CN103092534A (en) * | 2013-02-04 | 2013-05-08 | 中国科学院微电子研究所 | Scheduling method and device for internal memory structure |
Also Published As
| Publication number | Publication date |
|---|---|
| CN104424124A (en) | 2015-03-18 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| KR102584018B1 (en) | Apparatus, system and method for caching compressed data background | |
| CN107656700B (en) | FLASH-DRAM hybrid memory module | |
| US9053019B2 (en) | Non-volatile memory device, a data processing device using the same, and a swapping method used by the data processing and non-volatile memory devices | |
| CN109074307A (en) | With the memory device for directly reading access | |
| CN110970078B (en) | Method for fast boot reading | |
| US8060669B2 (en) | Memory controller with automatic command processing unit and memory system including the same | |
| US9348747B2 (en) | Solid state memory command queue in hybrid device | |
| JP2013530448A (en) | Cache storage adapter architecture | |
| CN105339910B (en) | Virtual NAND capacity extensions in hybrid drive | |
| CN113168374A (en) | Write command retention in partition namespaces | |
| US8583873B2 (en) | Multiport data cache apparatus and method of controlling the same | |
| US10318165B2 (en) | Data operating method, device, and system | |
| CN106155926B (en) | The data interactive method of memory and memory | |
| CN103985393B (en) | A kind of multiple optical disk data parallel management method and device | |
| CN105677511B (en) | A kind of method for writing data and device reducing synchronization overhead | |
| CN107203411A (en) | A kind of virutal machine memory extended method and system based on long-range SSD | |
| CN110597742A (en) | Improved storage model for computer system with persistent system memory | |
| CN109144899A (en) | Method for managing table recovery | |
| CN109164976A (en) | Optimize storage device performance using write buffer | |
| CN104424124B (en) | Memory device, electronic equipment and the method for controlling memory device | |
| CN109901909A (en) | Method and virtualization system for virtualization system | |
| CN108062201A (en) | For the self-virtualizing flash memory of solid state drive | |
| US9785552B2 (en) | Computer system including virtual memory or cache | |
| CN103019624B (en) | Phase change memory device | |
| CN105653478B (en) | Serial flash controller, serial flash control method and serial flash control system |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |