CN104408014A - System and method for interconnecting processing units of calculation systems - Google Patents
System and method for interconnecting processing units of calculation systems Download PDFInfo
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- CN104408014A CN104408014A CN201410814349.9A CN201410814349A CN104408014A CN 104408014 A CN104408014 A CN 104408014A CN 201410814349 A CN201410814349 A CN 201410814349A CN 104408014 A CN104408014 A CN 104408014A
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/382—Information transfer, e.g. on bus using universal interface adapter
- G06F13/385—Information transfer, e.g. on bus using universal interface adapter for adaptation of a particular data processing system to different peripheral devices
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/40—Bus structure
- G06F13/4063—Device-to-bus coupling
- G06F13/4068—Electrical coupling
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F15/00—Digital computers in general; Data processing equipment in general
- G06F15/16—Combinations of two or more digital computers each having at least an arithmetic unit, a program unit and a register, e.g. for a simultaneous processing of several programs
- G06F15/163—Interprocessor communication
- G06F15/17—Interprocessor communication using an input/output type connection, e.g. channel, I/O port
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F2213/00—Indexing scheme relating to interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F2213/38—Universal adapter
- G06F2213/3852—Converter between protocols
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Abstract
The invention provides a system and method for interconnecting processing units of calculation systems. The system comprises at least two calculation systems. Each calculation system comprises two processing units; the two processing units are in in-board interconnection through a quick path interconnection (QPI) bus. As any two processing units of different calculation systems are in inter-board interconnection through the QPI bus, connection of any two processing units of at least two calculation systems is achieved. By adopting the system and the method, processing units of different calculation systems are directly connected in a tight coupling mode.
Description
Technical field
The present invention relates to field of computer technology, the system and method for particularly processing unit interconnection between a kind of computing system.
Background technology
At present, computing system inside comprises one or more processing unit, thus completes miscellaneous service process.Processing unit often all adopts centralized architecture design, and single or multiple processing unit is in a system integrated.This design enhances the island effect in system, if single processor unit runs into fault, can affect the stability of whole computing system.
In order to solve the problem, expand the processing power of single computing system, can by the processing unit interconnection in different computing system, the mode of current interconnection is: by ethernet device, PCIE interfacing equipment or other interfacing equipments, linked together by the processing unit in different computing system.
Visible, in the prior art, the processing unit in different computing system must realize interconnection indirectly by extra interfacing equipment, is a kind of connected mode of loose coupling, thus add the time delay communicated between processing unit, nor be beneficial to the transmission of high speed signal between processing unit.
Summary of the invention
The invention provides the system and method for processing unit interconnection between a kind of computing system, directly can connect with the processing unit of close coupled system by different computing system.
A system for processing unit interconnection between computing system, comprise at least two computing systems, each computing system comprises two processing units, and these two processing units carry out interconnection in plate by express passway interconnected (QPI) bus;
Any two processing units in different computing system are undertaken interconnecting between plate by QPI bus, the connection of any two processing units at least two computing systems described in realization.
Comprise 2 described computing systems,
Each processing unit in a computing system carries out interconnecting between plate by two processing units in QPI bus and another computing system respectively.
Comprise 4 described computing systems, wherein,
The first processing unit in first computing system is connected with the first processing unit in the 3rd computing system by QPI bus, and is connected with the second processing unit in the second computing system by QPI bus;
The second processing unit in first computing system is connected with the first processing unit in the second computing system by QPI bus, and is connected with the first processing unit in the 4th computing system by QPI bus;
The first processing unit in second computing system is connected with the second processing unit in the 3rd computing system by QPI bus;
The second processing unit in second computing system is connected with the second processing unit in the 4th computing system by QPI bus;
The first processing unit in 3rd computing system is connected with the second processing unit in the 4th computing system by QPI bus;
The second processing unit in 3rd computing system is connected with the first processing unit in the 4th computing system by QPI bus.
Two processing units in each computing system are undertaken interconnecting in plate by the QPI bus of 9.2GT/s.
This system comprises further: interconnect extended module,
Described interconnect extended module is connected with the memory module of each processing unit in described at least two computing systems, to form memory module pond.
The method of processing unit interconnection between a kind of computing system, be applied in any one system above-mentioned, described system comprises at least two computing systems, and each computing system comprises two processing units, and these two processing units are undertaken interconnecting in plate by QPI bus;
The method comprises: undertaken interconnecting between plate by QPI bus by any two processing units in different computing system, the connection of any two processing units at least two computing systems described in realization.
When comprising 2 described computing systems, describedly any two processing units in different computing system to be carried out between plate interconnection by QPI bus comprise:
Each processing unit in a computing system is carried out interconnecting between plate by two processing units in QPI bus and another computing system respectively.
When comprising 4 described computing systems, describedly any two processing units in different computing system to be carried out between plate interconnection by QPI bus comprise:
The first processing unit in first computing system is connected with the first processing unit in the 3rd computing system by QPI bus, and is connected with the second processing unit in the second computing system by QPI bus;
The second processing unit in first computing system is connected with the first processing unit in the second computing system by QPI bus, and is connected with the first processing unit in the 4th computing system by QPI bus;
The first processing unit in second computing system is connected with the second processing unit in the 3rd computing system by QPI bus;
The second processing unit in second computing system is connected with the second processing unit in the 4th computing system by QPI bus;
The first processing unit in 3rd computing system is connected with the second processing unit in the 4th computing system by QPI bus;
The second processing unit in 3rd computing system is connected with the first processing unit in the 4th computing system by QPI bus.
The method comprises further: arrange interconnect extended module,
Described interconnect extended module is connected with the memory module of each processing unit in described at least two computing systems, to form memory module pond.
The method comprises further: according to business load and type of service, carries out universal formulation and configuration to the computational resource of each processing unit in described at least two computing systems.
The embodiment of the present invention proposes the system and method for processing unit interconnection between a kind of computing system, QPI bus can be utilized to be connected directly between together with close coupled system by the processing unit of different computing system, without the need to by other extra interfacing equipments, the process such as data retransmission required when therefore not needing to be connected by interfacing equipment, thus reduce the time delay communicated between processing unit, and be conducive to the transmission of high speed signal between processing unit.
Accompanying drawing explanation
Fig. 1 is two computing system four-processor expansion interconnect architecture schematic diagram in one embodiment of the invention.
Fig. 2 is four computing system eight processor expansion interconnect architecture schematic diagram in one embodiment of the invention.
Fig. 3 is the structural representation building storage pool in one embodiment of the invention in single computing system.
Fig. 4 is the structural representation building storage pool in one embodiment of the invention in two computing system.
Fig. 5 is the structural representation building storage pool in one embodiment of the invention in four computing systems.
Fig. 6 is a kind of structural representation of single computing system inside in one embodiment of the invention.
Embodiment
One embodiment of the invention proposes the system of processing unit interconnection between a kind of computing system, comprise at least two computing systems, each computing system comprises two processing units, these two processing units carry out interconnection in plate by express passway interconnected (QuickPath Interconnect, QPI) bus;
Any two processing units in different computing system are undertaken interconnecting between plate by QPI bus, the connection of any two processing units at least two computing systems described in realization.
Visible, this embodiment of the present invention can utilize QPI bus to be connected directly between together with close coupled system by the processing unit of different computing system, without the need to by other extra interfacing equipments, the process such as data retransmission required when therefore not needing to be connected by interfacing equipment, thus reduce the time delay communicated between processing unit, and be conducive to the transmission of high speed signal between processing unit.
Further, this embodiment of the present invention is the computer architecture architecture design of a kind of close coupled type based on the scalable interconnected formula of QPI high-speed bus, by this extendible high-speed interconnect framework, the linear expansion between multiple processing unit in single computing system can be supported in, this architectural framework can fully according to business load and type of service simultaneously, the computational resource of computing machine is divided and configured, thus reaches the optimization collocation of system resource.
Further, the embodiment of the present invention, can Single Point of Faliure effectively in isolated system based on the multi-computing system expansion architecture design of QPI high-speed bus, the stability of raising whole system.
In some embodiments of the invention, the number of computing system can be 2, and now, between computing system, the interconnection structure of processing unit can see Fig. 1.In Fig. 1, comprise computing system N and computing system N+1 totally 2 computing systems, each computing system comprises processing unit 1 and processing unit 2, wherein,
In plate, interconnection mode is: in computing system N and computing system N+1, and processing unit 1 and processing unit 2 are all undertaken interconnecting in plate by QPI bus;
Between plate, interconnection mode is: for computing system N, and processing unit 1 carries out interconnecting between plate by the processing unit 1 in QPI bus and computing system N+1 and processing unit 2 respectively; And in computing system N, processing unit 2 carries out interconnecting between plate by the processing unit 1 in QPI bus and computing system N+1 and processing unit 2 respectively.
See Fig. 1, the exchange that processing unit after connecting according to above topology arbitrarily in computing system can realize data between any one processing unit directly and in self and other computing system with communicate, like this can the efficiency of data communication between processing unit in effectively raising system, can be interconnected system extension by QPI is 1 whole system of synthesis with 4 processing units simultaneously, promotes the calculated performance of original system.
In other embodiments of the present invention, the number of computing system can be 4, wherein be made up of 2 processing units in each computing system, each processing unit has 2 interconnect port P1 and P2 simultaneously, 4 computing systems can be synthesized by QPI interconnect bus the whole system of synthesis that 1 is supported 8 processing units, now, between computing system, the interconnection structure of processing unit can see Fig. 2.In Fig. 2, comprise computing system N, computing system N+1, computing system N+2 and computing system N+3, totally 4 computing system, each computing system comprises 2 processing units, wherein,
In plate, interconnection mode is (not shown in Fig. 2): in computing system N, and processing unit 0 is interconnected by QPI bus and processing unit 1; In computing system N+1, processing unit 2 is interconnected by QPI bus and processing unit 3; In computing system N+2, processing unit 4 is interconnected by QPI bus and processing unit 5; In computing system N+3, processing unit 6 is interconnected by QPI bus and processing unit 7;
See Fig. 2, between plate, interconnection mode is:
Processing unit 1 in computing system N is connected with the processing unit 1 in computing system N+2 by QPI bus, and the processing unit 1 in computing system N is connected with the processing unit 2 in computing system N+1 by QPI bus;
Processing unit 2 in computing system N is connected with the processing unit 1 in computing system N+1 by QPI bus, and the processing unit 2 in computing system N is connected with the processing unit 1 in computing system N+3 by QPI bus;
Processing unit 1 in computing system N+1 is connected with the processing unit 2 in computing system N+2 by QPI bus;
Processing unit 2 in computing system N+1 is connected with the processing unit 2 in computing system N+3 by QPI bus;
Processing unit 1 in computing system N+2 is connected with the processing unit 2 in computing system N+3 by QPI bus;
Processing unit 2 in computing system N+2 is connected with the processing unit 1 in computing system N+3 by QPI bus.
See Fig. 2, by above-mentioned QPI interconnection topology, can realize being 1 whole system of synthesis with 8 processing units by system extension, the calculated performance of original processing unit is promoted 4 times, simultaneously can Single Point of Faliure effectively in isolated system, the stability of raising whole system.
In the structure shown in above-mentioned Fig. 1 and Fig. 2, two processing units in each computing system can be undertaken interconnecting in plate by the QPI bus of 9.2GT/s.
In order to realize the memory module interconnection in different computing system further, to form memory module pond, thus can be used for each processing unit of interconnection to access, in some embodiments of present system, may further include: interconnect extended module, this interconnect extended module is connected with the memory module of each processing unit at least two computing systems, to form memory module pond.Fig. 3 to Fig. 5 respectively illustrates in single computing system, two computing system and four computing systems, by the schematic diagram in interconnect extended module generation memory module pond.
See Fig. 3 to Fig. 5, support that namely multi-computing system calculates the computer body system structure of source dynamic assignment at the new close coupled type based on fusion architecture, using 1 single system double processing unit as a basic calculation source, by the QPI interconnection topology introduced above, 2 basic calculation sources can dynamic expansion be 1 system supporting 4 processing units by interconnect extended module, and system-computed performance can promote 2 times; Same based on this framework, 4 basic calculation sources can dynamic expansion be 1 system supporting 8 processing units by interconnect extended module, and system-computed performance can promote 4 times.
It should be noted that, based on any one interconnection system of the invention described above embodiment, fully according to business load and type of service, universal formulation and configuration can also be carried out to the computational resource of each processing unit in multiple computing system, thus reach the optimization collocation of system resource.
Fig. 6 is a kind of structural representation of single computing system inside in one embodiment of the invention.See Fig. 6, in an embodiment of the invention, each computing system is made up of information process unit, centralized management unit, information acquisition unit, application extension module, disk expanding element, disk memory array, interconnect extended unit, network transmitting unit etc., processing unit is as the core cell on computing module, adopt the CPU design of traditional X-ray 86 framework, OPI bus by two 9.2GT/s between 2 processing units interconnects, and realizes the data communication between processing unit.Each processing unit supports 4 independently memory expansion unit, each expanding element can provide the data storage capacity of 128GB, there is provided the data transfer bandwidth of 16.7GB/s, therefore each processing unit can put forward the high-speed transfer of data transfer bandwidth as data of 66.7GB/s simultaneously.Have 4 I/O in single calculating source and expand control module, each I/O expanding element is directly connected with information process unit individually by the path of 1 group of PCIex8, can collocation system customization Mezz transition card, realize PCIe-FC, PCIe-Infiniband, PCIe-Ethernet application conversion.Centralized management unit is connected with information process unit by DMI bus, receives the instruction sent by information process unit.Centralized management unit is by the link interconnection network unit of PCIe2.0x4, network element supports the data link of 4 10Gb/s, for the network exchange unit in connected system, the calculation task transmitted by network exchange module can be delivered in processing unit and process, data complete for processing unit processes can be fed back by network element more simultaneously.Disk expanding element is connected with the link of information process unit by PCIe3.0x8, can support the disk storage scheme of the LSI that industry is general or adaptec corp, can realize RAID5, the senior application taking into account performance and security and store such as 6.Disk memory array is connected with storage enhancement unit and information process unit simultaneously, and when collocation storage expansion unit, disk memory array is connected with storage expansion unit by SAS passage, can support the memory device of traditional SAS/SATA/SSD type.When do not arrange in pairs or groups storage expansion unit time, disk memory array is connected with information process unit by two PCIe3.0x4 link, can support the PCIE SSD in future, significantly the disk storage performance of raising calculating origin system.Interconnect extended unit supports 1 QPI bus, can be connected with the other interconnect extended unit calculated in origin system, QPI interconnection topology in composition diagram 1 or Fig. 2, realize many calculating source dynamic expansion of close coupled type, single QPI bus can support the transmission bandwidth of 9.6GT/s.
Above to the embodiment of the present invention propose computing system between processing unit interconnection system be illustrated.
One embodiment of the invention also proposed the method for processing unit interconnection between a kind of computing system, and be applied in the interconnection system of any one structure above-mentioned, this system comprises at least two computing systems, and each computing system comprises two processing units,
The method comprises: these two processing units are undertaken interconnecting in plate by QPI bus; Any two processing units in different computing system are undertaken interconnecting between plate by QPI bus, the connection of any two processing units at least two computing systems described in realization.
In some embodiments of the invention, when comprising 2 described computing systems, described the process that any two processing units in different computing system are undertaken interconnecting between plate by QPI bus to be comprised:
Each processing unit in a computing system is carried out interconnecting between plate by two processing units in QPI bus and another computing system respectively.
In some embodiments of the invention, when comprising 4 described computing systems, describedly any two processing units in different computing system to be carried out between plate interconnection by QPI bus comprise:
The first processing unit in first computing system is connected with the first processing unit in the 3rd computing system by QPI bus, and is connected with the second processing unit in the second computing system by QPI bus; The second processing unit in first computing system is connected with the first processing unit in the second computing system by QPI bus, and is connected with the first processing unit in the 4th computing system by QPI bus; The first processing unit in second computing system is connected with the second processing unit in the 3rd computing system by QPI bus; The second processing unit in second computing system is connected with the second processing unit in the 4th computing system by QPI bus; The first processing unit in 3rd computing system is connected with the second processing unit in the 4th computing system by QPI bus; The second processing unit in 3rd computing system is connected with the first processing unit in the 4th computing system by QPI bus.
In some embodiments of the invention, said method comprises further: arrange interconnect extended module,
Described interconnect extended module is connected with the memory module of each processing unit in described at least two computing systems, to form memory module pond.
In some embodiments of the invention, the method comprises further: according to business load and type of service, carries out universal formulation and configuration to the computational resource of each processing unit in described at least two computing systems.
It should be noted that, in this article, the relational terms of such as first and second and so on is only used for an entity or operation to separate with another entity or operational zone, and not necessarily requires or imply the relation that there is any this reality between these entities or operation or sequentially.And, term " comprises ", " comprising " or its any other variant are intended to contain comprising of nonexcludability, thus make to comprise the process of a series of key element, method, article or equipment and not only comprise those key elements, but also comprise other key elements clearly do not listed, or also comprise by the intrinsic key element of this process, method, article or equipment.When not more restrictions, the key element " being comprised " limited by statement, and be not precluded within process, method, article or the equipment comprising described key element and also there is other same factor.
The foregoing is only preferred embodiment of the present invention, not in order to limit the present invention, within the spirit and principles in the present invention all, any amendment made, equivalent replacement, improvement etc., all should be included within the scope of protection of the invention.
Claims (10)
1. a system for processing unit interconnection between computing system, it is characterized in that, comprise at least two computing systems, each computing system comprises two processing units, and these two processing units are undertaken interconnecting in plate by the interconnected QPI bus of express passway;
Any two processing units in different computing system are undertaken interconnecting between plate by QPI bus, the connection of any two processing units at least two computing systems described in realization.
2. system according to claim 1, is characterized in that, comprises 2 described computing systems,
Each processing unit in a computing system carries out interconnecting between plate by two processing units in QPI bus and another computing system respectively.
3. system according to claim 1, is characterized in that, comprises 4 described computing systems, wherein,
The first processing unit in first computing system is connected with the first processing unit in the 3rd computing system by QPI bus, and is connected with the second processing unit in the second computing system by QPI bus;
The second processing unit in first computing system is connected with the first processing unit in the second computing system by QPI bus, and is connected with the first processing unit in the 4th computing system by QPI bus;
The first processing unit in second computing system is connected with the second processing unit in the 3rd computing system by QPI bus;
The second processing unit in second computing system is connected with the second processing unit in the 4th computing system by QPI bus;
The first processing unit in 3rd computing system is connected with the second processing unit in the 4th computing system by QPI bus;
The second processing unit in 3rd computing system is connected with the first processing unit in the 4th computing system by QPI bus.
4. system according to claim 1, is characterized in that,
Two processing units in each computing system are undertaken interconnecting in plate by the QPI bus of 9.2GT/s.
5., according to described system arbitrary in Claims 1-4, it is characterized in that, this system comprises further: interconnect extended module,
Described interconnect extended module is connected with the memory module of each processing unit in described at least two computing systems, to form memory module pond.
6. the method for processing unit interconnection between a computing system, it is characterized in that, be applied to as in the system as described in arbitrary in claim 1 to 5, described system comprises at least two computing systems, each computing system comprises two processing units, and these two processing units are undertaken interconnecting in plate by QPI bus;
The method comprises: undertaken interconnecting between plate by QPI bus by any two processing units in different computing system, the connection of any two processing units at least two computing systems described in realization.
7. method according to claim 6, is characterized in that, when comprising 2 described computing systems, describedly any two processing units in different computing system to be carried out between plate interconnection by QPI bus comprises:
Each processing unit in a computing system is carried out interconnecting between plate by two processing units in QPI bus and another computing system respectively.
8. method according to claim 6, is characterized in that, when comprising 4 described computing systems, describedly any two processing units in different computing system to be carried out between plate interconnection by QPI bus comprises:
The first processing unit in first computing system is connected with the first processing unit in the 3rd computing system by QPI bus, and is connected with the second processing unit in the second computing system by QPI bus;
The second processing unit in first computing system is connected with the first processing unit in the second computing system by QPI bus, and is connected with the first processing unit in the 4th computing system by QPI bus;
The first processing unit in second computing system is connected with the second processing unit in the 3rd computing system by QPI bus;
The second processing unit in second computing system is connected with the second processing unit in the 4th computing system by QPI bus;
The first processing unit in 3rd computing system is connected with the second processing unit in the 4th computing system by QPI bus;
The second processing unit in 3rd computing system is connected with the first processing unit in the 4th computing system by QPI bus.
9., according to described method arbitrary in claim 6 to 8, it is characterized in that, the method comprises further: arrange interconnect extended module,
Described interconnect extended module is connected with the memory module of each processing unit in described at least two computing systems, to form memory module pond.
10., according to described method arbitrary in claim 6 to 8, it is characterized in that, the method comprises further: according to business load and type of service, carries out universal formulation and configuration to the computational resource of each processing unit in described at least two computing systems.
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| CN105005361A (en) * | 2015-07-01 | 2015-10-28 | 浪潮电子信息产业股份有限公司 | High-performance-computation-oriented novel processing unit and computer system architecture |
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| CN105893322B (en) * | 2016-04-01 | 2018-08-14 | 浪潮电子信息产业股份有限公司 | A kind of CPU interacted systems and implementation method |
| CN106095720A (en) * | 2016-06-21 | 2016-11-09 | 浪潮(北京)电子信息产业有限公司 | A kind of multichannel computer system |
| CN106250277A (en) * | 2016-07-15 | 2016-12-21 | 浪潮(北京)电子信息产业有限公司 | A kind of multipath server system and the method being used for improving its stability |
| CN107766282A (en) * | 2017-10-27 | 2018-03-06 | 郑州云海信息技术有限公司 | A kind of design method of eight road server backplane and double buckle interacted systems |
| CN108509371A (en) * | 2018-04-09 | 2018-09-07 | 郑州云海信息技术有限公司 | A kind of high-end fault-tolerant computer node interacted system and implementation method |
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