CN104407182B - Semiconductor test jig - Google Patents
Semiconductor test jig Download PDFInfo
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- CN104407182B CN104407182B CN201410605255.0A CN201410605255A CN104407182B CN 104407182 B CN104407182 B CN 104407182B CN 201410605255 A CN201410605255 A CN 201410605255A CN 104407182 B CN104407182 B CN 104407182B
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Abstract
A kind of semiconductor test jig, including：Substrate, the substrate include several test zones；An at least row on each test zone of substrate tests syringe needle, each test syringe needle includes the first testing needle, and first testing needle includes the first noumenon, the first test lead positioned at the first noumenon one end and the first connecting pin positioned at the first noumenon other end；Cover the insulating layer on the first noumenon surface of first testing needle；Positioned at surface of insulating layer around the second testing needle of first testing needle, second testing needle and the first test coaxial needle, second testing needle includes the second ontology, the second test lead positioned at second ontology one end and the second connection end positioned at the second ontology other end, and the second test end surfaces are flushed with the first test end surfaces.Semiconductor test jig of the present invention can simultaneously test multiple encapsulating structures to be tested, improve the efficiency of test.
Description
Technical field
The present invention relates to semiconductor test technical field, more particularly to a kind of semiconductor test jig.
Background technology
Test processing procedure is the electrical functionality for the product that test encapsulation is completed after IC package, to ensure IC functions of dispatching from the factory
On integrality, and the product to having tested according to its electrical functionality work classify, as the Appreciation gist of IC different brackets products, most
Make appearance test operation afterwards and to product.
Electrical functionality test is being tested for the various electrical parameters of product to determine product energy normal operation.
Test of two-point contact such as Kelvin's test etc. on traditional same tested terminal mostly uses Double ejection pin or double golden hands
The mode for referring to parallel side-by-side distribution, is primarily present following deficiency：
1, the accuracy of manufacture is relatively low：With the continuous diminution of semiconductor product size, it is tested the size of terminal and different quilts
The spacing surveyed between terminal is also constantly reducing, in order to comply with this trend, Conventional parallel and the Double ejection pin of column distribution or double golden hands
Refer to test mode its close spacing the problem of on bottleneck become increasingly conspicuous, required precision is higher and higher, some even cannot achieve
.
2, structural strength is weaker：In order to which two-point contact test, thimble or gold are realized in limited space on tested terminal
Finger is accordingly increasingly thinner, and Mechanical Structure Strength is also more and more weaker.
3, service life is shorter：The test contact head of traditional thimble or golden finger is easier to frayed, is especially carried in precision
Go out requirements at the higher level, mechanical strength it is relatively low when, degree of wear bigger thereby reduces the service life of measurement jig.
4, measuring accuracy is relatively low：To comply with the light and short growth requirement of semiconductor, increasingly thinner thimble or golden finger
Generated resistance value constantly increases, while when carrying out high-current test, will produce larger pressure drop and influencing test number
Judgement；On the other hand, the Double ejection pin of parallel side-by-side distribution or the also easy of double golden fingers produce because of offset deviation between the two
The deviation of raw test number；In addition, tradition and the Double ejection pin of column distribution in order to reduce the distance between two needles and use two back to
The way of contact on inclined-plane, contact head be easy because in its overall structure the torsion of telescopic spring due to rotate out of tested terminal so that influence
Measuring accuracy.
Invention content
Problems solved by the invention is how to improve the precision and stability of existing electrical performance testing.
To solve the above problems, the present invention provides a kind of semiconductor test jig, including：Substrate, if the substrate includes
Dry test zone；An at least row on each test zone of substrate tests syringe needle, and each syringe needle of testing includes the first survey
Test point, first testing needle include the first noumenon, positioned at first test lead of the first noumenon one end and positioned at the first noumenon
First connecting pin of the other end；Cover the insulating layer on the first noumenon surface of first testing needle；Positioned at surface of insulating layer ring
Around the second testing needle of first testing needle, the second testing needle and the first test coaxial needle, the second testing needle include second
Body, the second test lead positioned at second ontology one end and the second connection end positioned at the second ontology other end, described second surveys
Examination end surfaces are flushed with the first test end surfaces.
Optionally, several tested in encapsulating structure to be tested of several test syringe needles pair on each test zone
Terminal is tested.
Optionally, the row of the number of rows of syringe needle >=1 in each test zone, is tested, often in quantity >=2 of the test zone
Quantity >=2 of syringe needle are tested in one row.
Optionally, a diameter of 500 nanometers~500 microns of first testing needle, the width of insulating layer is 80 nanometers~
400 microns, the width of the second testing needle is 60 nanometers~300 microns.
Optionally, the material of the insulating layer is silica, silicon nitride, silicon oxynitride, fire sand, fire sand or tree
Fat.
Optionally, several signal circuits are formed in the substrate, the signal circuit is suitable for carrying out electricity
When performance test test signal, and the electric signal output for syringe needle acquisition being tested when testing, Mei Gexin are transmitted to test syringe needle
Number transmission circuit and the test syringe needle in corresponding test zone are electrically connected, and each signal circuit includes several first inputs
The first connecting pin electricity of end, the first output end, the second input terminal and second output terminal, each first output end and the first testing needle
Connection, each second output terminal are electrically connected with the second connection end of the second testing needle, the first input end and the second input terminal
It is electrically connected respectively with external test circuit.
Optionally, further include：Dielectric layer in substrate, the dielectric layer fill the space between adjacent test syringe needle
And some or all of coverage test syringe needle sidewall surfaces.
Optionally, the dielectric layer cover it is described test syringe needle whole sidewall surfaces when, the surface of the dielectric layer with
The top surface of test syringe needle flushes, and further includes：Positioned at dielectric layer and the rebound on syringe needle is tested, is had in the rebound
Several metal derbies with test needle tip electrical surface contact.
Optionally, the material of the dielectric layer is silica, silicon nitride, silicon oxynitride, fire sand, fire sand or tree
Fat.
Compared with prior art, technical scheme of the present invention has the following advantages：
First testing needle and the second testing needle are integrated in a survey by the test syringe needle in semiconductor test jig of the present invention
On test point head, the second testing needle uses insulator separation around first testing needle between the second testing needle and the first testing needle,
To while ensureing that the size of testing needle is smaller, promote the mechanical strength of testing needle；On the other hand, the first testing needle and
Two testing needles are coaxially to be distributed so that the precision of spacing is higher between the first testing needle and the second testing needle, improves test
Precision；In another aspect, needing multiple testing needles (such as Double ejection pin or golden finger) that electrical property could be carried out compared with the prior art
It can test, of the invention test syringe needle can carry out the test of electric property；In another aspect, including several in the substrate
Test zone, at least row on each test zone test syringe needle, each test zone can encapsulation to be tested to one tie
Several tested terminals in structure are tested, thus the semiconductor test jig of the present invention can tie several encapsulation to be tested
Structure is carried out at the same time test, improves the efficiency of test.
Further, be formed with signal circuit in the substrate, convenient for test signal in test process transmission and obtain
, and improve semiconductor test jig integrated level.
Description of the drawings
Fig. 1~Fig. 4 is the structural schematic diagram of one embodiment of the invention semiconductor test jig；
Fig. 5~Figure 11 is the structural schematic diagram of one embodiment of the invention semiconductor test jig forming process；
Figure 12~Figure 15 is the structural schematic diagram of another embodiment of the present invention semiconductor test jig forming process.
Specific implementation mode
As described in the background art, the performance of existing thimble or golden finger is still to be improved.
For this purpose, the present invention provides a kind of semiconductor test jig, including substrate, the substrate include several test sections
Domain；An at least row on each test zone of substrate tests syringe needle, and each syringe needle of testing includes the first testing needle, described
First testing needle includes the first noumenon, the first test lead positioned at the first noumenon one end and positioned at the first noumenon other end
One connecting pin；Cover the insulating layer on the first noumenon surface of first testing needle；Positioned at surface of insulating layer around described first
Second testing needle of testing needle, the second testing needle and the first test coaxial needle, the second testing needle include the second ontology, are located at second
Second test lead of ontology one end and second connection end positioned at the second ontology other end, the second test end surfaces and the
One test end surfaces flush.Test syringe needle in semiconductor test jig of the present invention integrates the first testing needle and the second testing needle
It is tested on syringe needle at one, the second testing needle is around first testing needle, with exhausted between the second testing needle and the first testing needle
Edge layer is isolated, to while ensureing that the size of testing needle is smaller, promote the mechanical strength of testing needle；On the other hand, first
Testing needle and the second testing needle are coaxially to be distributed so that the precision of spacing is higher between the first testing needle and the second testing needle, carries
The high precision of test；In another aspect, needing multiple testing needles (such as Double ejection pin or golden finger) ability compared with the prior art
Electrical performance testing is carried out, of the invention test syringe needle can carry out the test of electric property；In another aspect, the substrate
Upper includes several test zones, and at least row on each test zone tests syringe needle, and each test zone can wait for one
Several tested terminals in test encapsulating structure are tested, thus the semiconductor test jig of the present invention can be waited for several
Test encapsulating structure is carried out at the same time test, improves the efficiency of test.
To make the above purposes, features and advantages of the invention more obvious and understandable, below in conjunction with the accompanying drawings to the present invention
Specific embodiment be described in detail.When describing the embodiments of the present invention, for purposes of illustration only, schematic diagram can disobey general proportion
Make partial enlargement, and the schematic diagram is example, should not limit the scope of the invention herein.In addition, in reality
In making should include length, width and depth three-dimensional space.
Fig. 1~Fig. 4 is the structural schematic diagram of one embodiment of the invention semiconductor test jig；Fig. 5~Figure 11 is the present invention
The structural schematic diagram of one embodiment semiconductor test jig forming process；Figure 12~Figure 15 is another embodiment of the present invention semiconductor
The structural schematic diagram of measurement jig forming process.
Please refer to Fig.1 and Fig. 2, Fig. 2 be Fig. 1 along the cross-sectional view in the directions cutting line AB, one embodiment of the invention
A kind of semiconductor test jig is provided, including：
Substrate 200, the substrate 200 include several test zones (21a, 21b, 21c, 21d)；
An at least row on each test zone (21a, 21b, 21c, 21d) of substrate 200 tests syringe needle 20, each
It includes the first testing needle 201 to test syringe needle 20；Cover the insulating layer 202 of the sidewall surfaces of first testing needle 201；Positioned at exhausted
202 surface loop of edge layer is around the second testing needle 203 of first testing needle 201, the second testing needle 203 and the first testing needle 201
Coaxially.
In the present embodiment, the test syringe needle 20 is coaxial test syringe needle, referring to FIG. 3, Fig. 3 is one in Fig. 1 or Fig. 2
The enlarged structure schematic diagram of syringe needle is tested, the test syringe needle 20 includes：
First testing needle 201, first testing needle 201 include the first noumenon, are surveyed positioned at the first of the first noumenon one end
Try end 21 and the first connecting pin 22 positioned at the first noumenon other end；
Cover the insulating layer 202 on the first noumenon surface of first testing needle 201；
Positioned at 202 surface loop of insulating layer around the second testing needle 203 of first testing needle 201, the second testing needle 203 with
First testing needle 201 is coaxial, the second testing needle 203 include the second ontology, positioned at second ontology one end the second test lead 23 with
And the second connection end 24 positioned at the second ontology other end, 23 surface of the second test lead and 31 surface of the first test lead are neat
It is flat.When carrying out electrical performance testing, first test lead, 21 and second test lead 23 and tested terminal point contact.
With continued reference to FIG. 1, in the substrate 200 include several test zones, quantity >=2 of the test zone,
At least there is a row to test syringe needle on each test zone, i.e., the row of the number of rows of test syringe needle on each test zone >=1, and it is each
Quantity >=2 of test syringe needle 20 in row.
In the present embodiment, the quantity of test zone is 4 in the substrate 200, including the first test zone 21a, second
The number of rows of test zone 21b, third test zone 21c, the 4th test zone 21d, the test syringe needle on each test zone are 2
It arranges, the quantity of test syringe needle is 4 in each row.It should be noted that in the other embodiment of the present invention, the substrate 200
On the quantity of test zone, the quantity of test syringe needle can in the number of rows of test syringe needle and each row on each test zone
Think other suitable values.
Several tested ends in encapsulating structure to be tested of several test syringe needles pair on each test zone
Son is tested, i.e., each test zone can test an encapsulating structure to be tested, have with substrate in the present embodiment
For having 4 test zones, the semiconductor test jig in the present embodiment can simultaneously survey 4 test structures to be packaged
Examination, improves testing efficiency.
In the present embodiment, structure, quantity and arrangement mode of test syringe needle on each test zone etc. are same, thus
The semiconductor test jig of the present invention can be simultaneously to having mutually isostructural multiple encapsulating structures to be tested to carry out electric property
Test, faster testing efficiency may be implemented.
In other embodiments of the invention, the quantity of the test syringe needle in different test zones and arrangement mode can not
It is identical, to realize the test to different encapsulating structures to be tested, such as in one embodiment, the testing needle in adjacent test zone
Head number of rows can differ the test syringe needle in either adjacent test zone in each row quantity can differ or
The arrangement mode of syringe needle is tested in adjacent test zone to be differed.
In the present embodiment, the quantity of the test syringe needle of adjacent row is identical with arrangement mode in each test zone, i.e., each
The test syringe needle quantity of row is 4, and the line of centres that syringe needle is tested in a row is in a straight line.
In other embodiments of the invention, in each test zone, the quantity of the test syringe needle of adjacent row and arrangement side
Formula can differ.
It is cylinder, corresponding first testing needle incorporated by reference to the shape with reference to figure 1 and Fig. 3, first testing needle 201
201 section shape is circle, and the section shape of the insulating layer 202 is circular ring shape, the section shape of second testing needle 203
Shape is circular ring shape.It should be noted that the section shape of first testing needle can be other shapes, such as described first
The section shape of testing needle can be regular polygon, such as equilateral triangle, square.
The test syringe needle of the present invention is formed by semiconductor integration making technology, thus the first testing needle 201 formed
Diameter can be smaller, and in one embodiment, a diameter of 100 nanometers~500 microns of first testing needle 201, can be 200
Nanometer~50 microns.
The width of the corresponding insulating layer 202 and the width of the second testing needle 203 can also very little, in an embodiment
In, the width of the insulating layer 202 is 80 nanometers~400 microns, can be 100 nanometers~10 microns, second testing needle
203 width is 60 nanometers~300 microns, can be 90 nanometers~25 microns.
It should be noted that in other embodiments of the invention, according to the needs of test, first testing needle 201
Diameter, the thickness of insulating layer 202 and the thickness of third testing needle 203 can be other suitable numerical value.
The material of first testing needle, 201 and second testing needle 203 be copper, gold, tungsten or alloy material or other
Suitable metal material or metal compound material.
The insulating layer 202 is for the electric isolation between the first testing needle 201 and the second testing needle 203, the present embodiment
In, the top surface (the first test lead 21) of the top surface of the insulating layer 202 and the first testing needle 201 and the second testing needle
203 top surface (the second test lead 23) flushes, i.e., so that the first test lead 21 and the second testing needle of the first testing needle 201
There is no gap between 203 the second test lead 23, in test, prevents the first test lead 21 or the of the first testing needle 201
Second test lead 23 of two testing needles 203 thus between there are gaps to deform under external stress, and make the
The second test lead 23 electrical contact of the first test lead 21 and the second testing needle 203 of one testing needle 201, to influence the essence of test
Degree.
The insulating layer 202 can be single-layer or multi-layer (>=2 layers) stacked structure.
The material of the insulating layer 202 can be insulating dielectric materials, such as silica, silicon nitride, silicon oxynitride, nitrogen carbon
One or more of SiClx, fire sand, the material of the insulating layer can also be resin material, for example, epoxy resin, poly-
Imide resin, polyvinyl resin, benzocyclobutane olefine resin or polybenzoxazoles resin.
From the direction for being directed toward the second test lead 23 far from the second test lead 23, the part body of second testing needle 203
Width be gradually reduced.Specifically referring to FIG. 1, the width of the part body of second testing needle 203, is tested closer to second
Hold 23 its width it is smaller, will mostly with testing needle 20 for test when so that it is adjacent test syringe needle 20 test lead between away from
From increase.
In one embodiment, also there is dielectric layer, the dielectric layer are filled in the substrate 200 between adjacent test syringe needle
Space and coverage test syringe needle partial sidewall surface, the dielectric layer is used to test electric isolation and raising between syringe needle
Test the mechanical strength of syringe needle 20.
The material of the dielectric layer be silica, silicon nitride, silicon oxynitride, fire sand, fire sand or resin or
Other suitable materials.
The thickness of the dielectric layer can be the 1/4~2/3 of 20 height of testing needle.
In another embodiment, also there is dielectric layer in the substrate 200, the dielectric layer fill adjacent test syringe needle it
Between space and coverage test syringe needle sidewall surfaces, the dielectric layer top surface and test syringe needle 20 top surface it is neat
It is flat, further include the rebound being located on dielectric layer, the rebound is as the transition between test syringe needle 20 and tested terminal
Structure to facilitate the test of electric property, and prevents test syringe needle 20 to be in direct contact with tested terminal, is made to calibrating terminal
At damage or it is easy so that test syringe needle 20 deforms.
The rebound includes separation layer and several metal derbies in separation layer, and the separation layer 400 is located at medium
On layer, separation layer is used for the electric isolation between metal derby and fixed corresponding metal derby, the bottom surface of the metal derby
Terminate with the top surface of test syringe needle 20, the top surface of the metal derby is contacted with tested terminal surfaces.
It is applied by the test syringe needle 20 of the present invention when carrying out electrical performance testing, it in one embodiment, can be by this
The test syringe needle of invention is applied to resistance test or high-current test, will test one end and the tested termination contact of syringe needle 20,
Make the first test lead 21 of the first testing needle 201 and 23 surface of the second test lead of the second testing needle 203 and tested terminal
Surface contacts, and applies test voltage between the first testing needle 201 and the second testing needle 202, measures and passes through the first testing needle
201, the electric current on the second testing needle 203 and tested terminal, and pass through test voltage divided by electric current obtains test electricity
Resistance.
In one embodiment, when carrying out the test of resistance using the test syringe needle 20 of the present invention, due to the first testing needle 201
It is coaxial with the second testing needle 203, thus tests electric current and uniformly spread around by the first testing needle 201, flows to the
Two testing needles 203, i.e., so that tested terminal between the first testing needle 201 and the second testing needle 203 annular region (with it is exhausted
The part that edge layer 202 contacts) on the electric current that flows through of different directions be average, improve the precision of test.
In other embodiments of the invention, the test syringe needle of the present invention can be applied to the electric property of other forms
Test, for example the test of multiple test syringe needle progress electric properties can be applied, for example test electric current can be from a testing needle
The first testing needle or the second testing needle of head flow to the first testing needle or the second testing needle of another test syringe needle, or test
The second testing needle and the second testing needle that circuit can test syringe needle from one flow to the first testing needle of another test syringe needle
With the second testing needle.
It is formed with signal circuit in the substrate 200, the signal circuit includes first input end, first defeated
Outlet, the second input terminal and second output terminal, first output end are electrically connected with the first connecting pin of the first testing needle 201,
The second output terminal is electrically connected with the second connection end of the second testing needle 203, the first input end and the second input terminal point
It is not electrically connected with external test circuit.For the test circuit for providing test signal, the signal circuit is used for will
The test signal that test circuit generates is transmitted to the first testing needle 201 and the second testing needle 203, and will be obtained in test process
Electric signal transmission to test circuit, test circuit handles the electric signal of reception, obtains test parameter.
Material PCB resins of the substrate 200 etc., the first input end and the first output end are intrabasement by being located at
First metal wire is electrically connected, and second input terminal and second output terminal are electrically connected by being located at intrabasement second metal wire.
In one embodiment, the substrate 200 includes front and the back side opposite with front, and the back side of the substrate includes
Interface area, several first output ends and second output terminal are located at the front of substrate 200, with the first testing needle and the second testing needle
Position correspond to, several first input ends and the second input terminal can concentrate on the interface area at 200 back side of substrate so that several
First input end and the second input terminal can be connected by one or more interfaces with external test circuit, and semiconductor is simplified
Interface circuit between measurement jig and the test circuit of outside.In a specific embodiment, the substrate 200 can pass through
Multi-layer PCB resin substrate presses to be formed, and each layer of PCB resin substrate includes several interconnection structures, and each interconnection structure includes
It is connected with through-hole interconnection structure through the through-hole interconnection structure of the PCB resin substrates and on PCB resin substrates surface
Metal layer, when multi-layer PCB resin substrate presses, multiple interconnection structures are electrically connected to form the first metal wire or the second metal wire, because
And several first input ends and the second input terminal is allow to concentrate on the interface area at 200 back side of substrate.
In another embodiment, the substrate 200 includes front and the back side opposite with front, the back side packet of the substrate
Include interface area, several first output ends and second output terminal are located at the front of substrate 200, several first input ends and second defeated
First through hole interconnection structure and the through substrate 200 can be formed positioned at the back side of substrate 200, in the substrate 200 by entering end
Two through-hole interconnection structures, the first input end and the first output end pass through the first through hole interconnection structure in substrate 200
Electrical connection, second input terminal and second output terminal are electrically connected by the second through-hole interconnection structure in substrate 200；Institute
Stating on the back side of substrate 200 also has the several first interconnection metal layer and the second interconnection metal layers again again, and described first connects up again
One end of metal layer is electrically connected with first input end, and the other end of the first interconnection metal layer again is located in interface area, and described
Two again one end of interconnection metal layer be electrically connected with the second input terminal, the other end of the described second interconnection metal layer again is located at interface area
In domain, in interface area first again interconnection metal layer and second again interconnection metal layer pass through one or more interfaces with it is external
Test circuit is connected.
In other embodiments, test circuit (not shown), the test electricity are could be formed in the substrate 200
Road includes the first signal end and second signal end, and the first signal end is electrically connected with the first connecting pin of the first testing needle 201, and second
Signal end is electrically connected with the second connection end of the second testing needle 203.The test circuit is when being tested, to the first testing needle
201 and second testing needle 203 apply test signal (such as voltage signal or current signal), and to the electric signal of acquisition (such as
Current signal etc.) carry out processing acquisition test parameter (such as resistance etc.).
With reference to figure 4, Fig. 4 is structural schematic diagram when semiconductor test jig of the invention is used for electrical performance testing, first
First semiconductor test jig is placed in tester table；Then encapsulating structure 300a, 300b to be tested are respectively placed in semiconductor
On the first test zone 21a and the second test zone 21b of measurement jig, described encapsulating structure 300a, 300b to be tested are upper equal
With several tested terminals 31, in one embodiment, the tested terminal 31 is pin or pad, the tested terminal
31 part surface is contacted with the top surface of the test syringe needle 20 in rebound；Then it is surveyed in the first testing needle 201 and second
Apply test signal between test point 203, carries out the test of electric property.
Semiconductor test jig through the invention can carry out electric property to multiple encapsulating structures to be tested simultaneously
It tests, to carry out the test of electric property to encapsulating structure 300a, 300b to be tested simultaneously as an example, carrying out in the present embodiment
When test and can multiple tested terminals in encapsulating structure 300a, 300b to be tested be carried out at the same time with electric property survey
Examination, improves the efficiency of test and the accuracy of test.
It should be noted that the semiconductor test jig of the present invention can be applied to manual test and (manually load to be tested
Encapsulating structure) automatic test can also be applied to (mechanical hand loads encapsulating structure to be tested automatically).
The embodiment of the present invention additionally provide it is a kind of formed aforesaid semiconductor measurement jig method, specifically please refer to Fig. 5~
Figure 11.
Referring to FIG. 5, providing substrate 200, the substrate 200 includes several test zones (not indicated in figure)；Described
At least one, which is formed, on each test zone of substrate 200 arranges the first testing needle 201.
Quantity >=2 of the test zone, in each test zone, the row of the number of rows of the first testing needle 201 >=1 is each
Quantity >=2 of first testing needle 201 in row.
First testing needle 201 is cylinder, and the first testing needle 201 is obtained along the direction for being parallel to 200 surface of substrate
Section shape be circle, a diameter of 500 nanometers~500 microns of first testing needle 201.
It should be noted that the section shape of first testing needle can be other shapes, for example described first surveys
The shape of test point is regular polygon, such as equilateral triangle, square.
In one embodiment, the forming process of first testing needle 201 is：The first gold medal is formed in the substrate 200
Belong to layer (not shown)；Patterned mask layer is formed on the first metal layer；Using the patterned mask layer as mask,
The first metal layer is etched, forming at least one on each test zone of the substrate arranges the first testing needle 201；Removal institute
State patterned mask layer.
In another embodiment, the forming process of first testing needle 201 is：It is formed and is sacrificed in the substrate 200
Layer (not shown) has in the sacrificial layer on each test zone of the substrate and exposes 200 surface of substrate at least
One exhausting hole；Full the first metal layer is filled in the through-hole, forms several first testing needles；Remove the sacrificial layer.
In the through-hole fill the first metal layer technique be electroplating technology, in through-holes fill the first metal layer it
Before, further include：Conductive layer is formed in the side wall of the through-hole and bottom and the surface of sacrificial layer, the conductive layer is as plating
Cathode when technique.
The material of the conductive layer is one or more of Ti, Ta, TiN, TaN etc., and conductive layer can be single layer or more
Layer (>=2 layers) stacked structure.
In one embodiment, the conductive layer can be double stacked structure, the conductive layer packet of the double stacked structure
Ti layers and the TiN layer on Ti layers are included, or the TaN layers being located on Ta layers including Ta layers.
The thickness of the conductive layer is less than the radius of through-hole, and in one embodiment, the thickness of the conductive layer is 50~200
The formation process of nanometer, conductive layer is sputtering.
After forming conductive layer, electroplating technology is carried out, forms the first metal layer layer, the first metal layer is located at conductive layer
Through-hole is gone up and filled, after carrying out electroplating technology, further includes：Chemical mechanical milling tech is carried out, the of sacrificial layer surface is removed
One metal layer and conductive layer, form the first testing needle 201, and the first testing needle 201 includes the first metal layer and encirclement described first
The non-proliferation barrier layer of metal layer, the non-proliferation barrier layer is made of remaining conductive layer after chemical mechanical grinding, for preventing
Only the metal in metal layer is spread into the insulating layer being subsequently formed.
The material of the first metal layer is copper, gold, tungsten or alloy material or other suitable metal materials.
The surface (bottom surface) that first testing needle 201 is contacted with 200 surface of substrate is the first connecting pin, and first surveys
The surface (top surface) opposite with the first connecting pin of test point 201 is the first test lead.
It is formed with signal circuit in the substrate 200, the signal circuit includes first input end, first defeated
Outlet, the second input terminal and second output terminal, first output end are electrically connected with the first connecting pin of the first testing needle 201,
The second output terminal is electrically connected with the second connection end of the second testing needle 203, the first input end and the second input terminal point
It is not electrically connected with external test circuit.For the test circuit for providing test signal, the signal circuit is used for will
The test signal that test circuit generates is transmitted to the first testing needle 201 and the second testing needle 203, and will be obtained in test process
Electric signal transmission to test circuit, test circuit handles the electric signal of reception, obtains test parameter.
Material PCB resins of the substrate 200 etc., the first input end and the first output end are intrabasement by being located at
First metal wire is electrically connected, and second input terminal and second output terminal are electrically connected by being located at intrabasement second metal wire.
In one embodiment, the substrate 200 includes front and the back side opposite with front, and the back side of the substrate includes
Interface area, several first output ends and second output terminal are located at the front of substrate 200, with the first testing needle and the second testing needle
Position correspond to, several first input ends and the second input terminal can concentrate on the interface area at 200 back side of substrate so that several
First input end and the second input terminal can be connected by one or more interfaces with external test circuit, and semiconductor is simplified
Interface circuit between measurement jig and the test circuit of outside.In a specific embodiment, the substrate 200 can pass through
Multi-layer PCB resin substrate presses to be formed, and each layer of PCB resin substrate includes several interconnection structures, and each interconnection structure includes
It is connected with through-hole interconnection structure through the through-hole interconnection structure of the PCB resin substrates and on PCB resin substrates surface
Metal layer, when multi-layer PCB resin substrate presses, multiple interconnection structures are electrically connected to form the first metal wire or the second metal wire, because
And several first input ends and the second input terminal is allow to concentrate on the interface area at 200 back side of substrate.
In another embodiment, the substrate 200 includes front and the back side opposite with front, the back side packet of the substrate
Include interface area, several first output ends and second output terminal are located at the front of substrate 200, several first input ends and second defeated
First through hole interconnection structure and the through substrate 200 can be formed positioned at the back side of substrate 200, in the substrate 200 by entering end
Two through-hole interconnection structures, the first input end and the first output end pass through the first through hole interconnection structure in substrate 200
Electrical connection, second input terminal and second output terminal are electrically connected by the second through-hole interconnection structure in substrate 200；Institute
Stating on the back side of substrate 200 also has the several first interconnection metal layer and the second interconnection metal layers again again, and described first connects up again
One end of metal layer is electrically connected with first input end, and the other end of the first interconnection metal layer again is located in interface area, and described
Two again one end of interconnection metal layer be electrically connected with the second input terminal, the other end of the described second interconnection metal layer again is located at interface area
In domain, in interface area first again interconnection metal layer and second again interconnection metal layer pass through one or more interfaces with it is external
Test circuit is connected.
In other embodiments, test circuit (not shown), the test electricity are could be formed in the substrate 200
Road includes the first signal end and second signal end, and the first signal end is electrically connected with the first connecting pin of the first testing needle 201, and second
Signal end is electrically connected with the second connection end of the second testing needle 203.The test circuit is when being tested, to the first testing needle
201 and second testing needle 203 apply test signal (such as voltage signal or current signal), and to the electric signal of acquisition (such as
Current signal etc.) carry out processing acquisition test parameter (such as resistance etc.).In one embodiment, the substrate 200 includes
Semiconductor substrate (such as silicon substrate or substrate etc.) and the dielectric layer in semiconductor substrate are formed in the semiconductor substrate
There is a semiconductor devices (such as transistor etc.), forms metal interconnecting wires and passive device (such as resistance, capacitance in the dielectric layer
Deng), semiconductor devices and passive device are connected and composed test circuit, the first signal end and second signal by the metal interconnecting wires
End can be drawn by the first metal wire being electrically connected with test circuit in dielectric layer and the second metal wire.
In conjunction with reference to figure 6 and Fig. 7, insulating layer 202 is formed on the side wall of each first testing needle 201.
The forming process of the insulating layer 202 is：It is formed and covers the exhausted of each first testing needle, 201 side wall and top surface
Edge film layer 204；No mask etching technique etches the insulating thin layer 204 and forms insulation in the side wall of the first testing needle 201
Layer 202.
The thickness of the insulating layer 202 is 80 nanometers~400 microns, and the material of the insulating layer 202 can be that insulation is situated between
One or more of material, such as silica, silicon nitride, silicon oxynitride, fire sand, fire sand.
The insulating layer 202 can be single-layer or multi-layer (>=2 layers) stacked structure.
The no mask etching technique is anisotropic plasma etching industrial, in one embodiment, the plasma
The etching gas that etching technics uses is specifically as follows CF for fluorine-containing and carbon gas4、C2F6、C4F8、CHF3、CH2F2In one
Kind is several, and source power is 500~1000W, and bias power is 0~100W, and etching cavity pressure is 2~500mtorr.
In the present embodiment, the insulating layer 202 is the silicon oxide layer of single layer,
In other embodiments of the invention, the material of the insulating layer 202 can also be resin material, the resinous wood
Material can be epoxy resin, polyimide resin, polyvinyl resin, benzocyclobutane olefine resin or polybenzoxazoles resin.
The formation process of the insulating layer 202 is screen printing technique etc..
In conjunction with reference to figure 8 and Fig. 9, the second testing needle 203, second testing needle 203 are formed on the surface of insulating layer 202
Around corresponding first testing needle 201.
The forming process of second testing needle 203 is：It is formed and covers 202 and first testing needle 201 of the insulating layer top
The second metal layer 205 on portion surface；Without second metal layer 205 described in mask etching, the second test is formed on 202 surface of insulating layer
Needle 203.
The formation process of the second metal layer 205 is sputtering, and 205 material of second metal layer is copper, gold, tungsten or alloy
The thickness of material or other suitable metal materials, second metal layer 205 is 60 nanometers~300 microns.
The technique of second metal layer 205 described in no mask etching is anisotropic plasma etching industrial, is implemented one
In example, for one or more of SF6, NF3, Cl2, HBr, source power is the etching gas that the plasma etching industrial uses
500~1500W, bias power are 0~100W, and etching cavity pressure is 10~500mtorr.
Each first testing needle 201 constitutes a test syringe needle 20 with corresponding insulating layer 202 and the second testing needle 203.
In another embodiment of the invention, referring to FIG. 10, after forming test syringe needle 20, in the substrate 200
Dielectric layer 210 is formed, the dielectric layer 210 fills the space between adjacent test syringe needle 20 and the part of coverage test syringe needle 20
Sidewall surfaces, the surface of the dielectric layer 210 is less than the top surface for testing syringe needle 210.
The forming process of the dielectric layer 210 is：Form the medium material for covering 20 surface of the substrate 200 and test syringe needle
The bed of material；The layer of dielectric material is planarized using chemical mechanical milling tech, to test the top surface of syringe needle 20 as stopping
Layer；The dielectric layer being etched back to after planarization so that top surface of the surface of remaining dielectric layer less than test syringe needle.
The material of the dielectric layer 210 is silica, silicon nitride, silicon oxynitride, fire sand, fire sand or resin
(such as epoxy resin, polyimide resin etc.) or other suitable materials.
In one embodiment, the material of the dielectric layer 210 is silica, silicon nitride, silicon oxynitride, fire sand or nitrogen
When silicon carbide, the formation process of layer of dielectric material is chemical vapor deposition method；In another embodiment, the dielectric layer 210
Material be resin when, the layer of dielectric material formation process be wet film or printing technology.
In another embodiment of the invention, with reference to figure 11, after forming test syringe needle 20, the shape in the substrate 200
At dielectric layer 210, the dielectric layer 210 fills the space between adjacent test syringe needle 20 and the side wall table of coverage test syringe needle 20
The surface in face, the dielectric layer 210 is flushed with the top surface of test syringe needle 210；Isolation is formed on the dielectric layer 210
Layer, there are several openings for exposing test 20 top surface of syringe needle in the separation layer；Metal, shape are filled in said opening
At metal derby 401, the separation layer and metal derby 401 constitute rebound 400.
The material of the separation layer be silica, silicon nitride, silicon oxynitride, fire sand, fire sand or resin (such as
Epoxy resin, polyimide resin etc.) or other suitable materials.
Several openings are formed in the separation layer by etching technics, the size of the opening is more than test needle tip
The size on surface so that the top surface of test syringe needle 20 can be completely revealed by forming opening so that fill metal in the opening
The metal derby 401 of formation can be completely attached to the top surface of test syringe needle 20.
The forming process of the metal derby 401 is：The metal layer for covering the separation layer is formed, the metal layer filling is full
The opening；The metal layer of insulation surface is removed using chemical mechanical milling tech, forms metal derby 401 in the opening.
The formation process of the metal layer is sputtering or electroplating technology, the material of metal layer is W, Al, Cu, Ti, Ag, Au,
Pt, Ni or alloy material etc..
Another embodiment of the present invention additionally provides a kind of method forming semiconductor test jig above-mentioned, specifically please refers to
Figure 12~Figure 15.
2 are please referred to Fig.1, substrate 200 is provided；Dielectric layer 210, each survey of the substrate are formed in the substrate 200
It is formed at least one in dielectric layer 210 on examination region and arranges the first through-hole 208 and the annular through-hole around each first through hole 208
209, it is isolated by certain media layer between first through hole 208 and annular through-hole 209.
Quantity >=2 of the test zone, number of rows >=1 of first through hole 208 in the dielectric layer on each test zone
It arranges, quantity >=2 of first through hole 208 in each row.
The first through hole 208 and annular through-hole 209 expose the surface of substrate 200, follow-up in the first through hole 208
It fills metal and forms the first testing needle, metal is subsequently filled in second through-hole and forms the second testing needle.
Signal circuit or test circuit are formed in the substrate 200, about signal circuit or test circuit
Description please refers to previous embodiment, and details are not described herein.
With reference to figure 13, Figure 13 is the overlooking structure diagram of part-structure in Figure 12, and the first through hole 208 is circle,
Annular through-hole 209 is circular ring shape, annular through-hole 209 around the first through hole 208, first through hole 208 and annular through-hole 209 it
Between be isolated by certain media layer material.
In other embodiments of the invention, the shape of the first through hole can be other shapes, for example can be
Regular polygon is specifically as follows equilateral triangle, square etc..
In one embodiment, the material of the dielectric layer 210 is insulating dielectric materials, such as silica, silicon nitride, nitrogen oxygen
One or more of SiClx, fire sand, fire sand form medium on a substrate 200 by chemical gaseous phase deposition technique
Layer 210, then forms patterned photoresist layer on the dielectric layer 210, using the patterned photoresist layer as mask,
The dielectric layer 210 is etched, forms several first through hole 208 and the annular around each first through hole 208 in dielectric layer 210
Through-hole 209；After forming the annular through-hole 209 of first through hole 208, the patterned photoresist layer is removed.
In another embodiment, the material of the dielectric layer 210 is resin glue, and the resin glue is epoxide-resin glue, gathers
Imide resin glue, polyvinyl adhesive, benzocyclobutene resin glue or polybenzoxazoles resin glue, by dry film process, wet
Membrane process, printing technology or plastic roll technique form dielectric layer 210 in the substrate 200；Then pass through exposed and developed technique
Several first through hole 208 and the annular through-hole 209 around each first through hole 208 are formed in the dielectric layer.
With reference to figure 14, filling metal forms the first testing needle 201 in first through hole 208 (with reference to figure 12), logical in annular
Filling metal forms the second testing needle 203 in hole 209 (with reference to figure 12).
First testing needle, 201 and second testing needle 203 is formed by same processing step.
The technique that metal is filled in first through hole 208 and annular through-hole 209 is electroplating technology, in 208 He of first through hole
Before filling metal in annular through-hole 209, further include：The first through hole 208 and annular through-hole 209 side wall and bottom with
And the surface of sacrificial layer forms conductive layer, the cathode when conductive layer is as electroplating technology.
The material of the conductive layer is one or more of Ti, Ta, TiN, TaN etc., and conductive layer can be single layer or more
Layer (>=2 layers) stacked structure.
In one embodiment, the conductive layer can be double stacked structure, the conductive layer packet of the double stacked structure
Ti layers and the TiN layer on Ti layers are included, or the TaN layers being located on Ta layers including Ta layers.
The thickness of the conductive layer is less than smaller in both the radius of first through hole 208 and the radius of annular through-hole 209
Radius value, the formation process of conductive layer is sputtering.
After forming conductive layer, electroplating technology is carried out, forms metal layer, the metal layer is located on conductive layer and fills the
One through-hole 208 and annular through-hole 209 further include after carrying out electroplating technology：Chemical mechanical milling tech is carried out, medium is removed
The metal layer and conductive layer on 210 surface of layer, form the first testing needle 201 and the second testing needle 203, the first testing needle 201 and the
Two testing needles 203 include metal layer and surround the non-proliferation barrier layer of the metal layer, and the non-proliferation barrier layer is chemistry
Remaining conductive layer is constituted after mechanical lapping, for preventing the metal in metal layer from being spread into the insulating layer being subsequently formed.Institute
The dielectric layer between the first testing needle 201 and the second testing needle 203 is stated as insulating layer 202
The material of the metal layer is copper, gold, tungsten or alloy material or other suitable metal materials.
The first testing needle 201 and the second testing needle 203, the first testing needle are formed simultaneously by electroplating technology in the present embodiment
201 and second testing needle 203 will not be by the damage etched so that the surface shape of the first testing needle 201 and the second testing needle 203
Looks are preferable.
In other embodiments of the invention, further include being etched back to the dielectric layer 210 after forming test syringe needle 20,
So that surface of the surface of remaining dielectric layer less than test syringe needle 20.
In other embodiments of the invention, with reference to figure 15, after forming test syringe needle 20, in 210 He of the dielectric layer
Separation layer is formed on test syringe needle 20, and there are several openings for exposing test 20 top surface of syringe needle in the separation layer；
Metal is filled in the opening, forms metal derby 401, and the separation layer and metal derby 401 constitute rebound 400.
Each first testing needle 201 and corresponding insulating layer 202 and corresponding second testing needle 203 constitute a test
Syringe needle 20.
The material of the separation layer be silica, silicon nitride, silicon oxynitride, fire sand, fire sand or resin (such as
Epoxy resin, polyimide resin etc.) or other suitable materials.
Several openings are formed in the separation layer by etching technics, the size of the opening is more than test needle tip
The size on surface so that the top surface of test syringe needle 20 can be completely revealed by forming opening so that fill metal in the opening
The metal derby 401 of formation can be completely attached to the top surface of test syringe needle 20.
The forming process of the metal derby 401 is：The metal layer for covering the separation layer is formed, and the metal layer is filled
The full opening；The metal layer of insulation surface is removed using chemical mechanical milling tech, forms metal derby 401 in the opening.
The formation process of the metal layer is sputtering or electroplating technology, the material of metal layer is W, Al, Cu, Ti, Ag, Au,
Pt, Ni or alloy material etc..
Although present disclosure is as above, present invention is not limited to this.Any those skilled in the art are not departing from this
It in the spirit and scope of invention, can make various changes or modifications, therefore protection scope of the present invention should be with claim institute
Subject to the range of restriction.
Claims (9)
1. a kind of semiconductor test jig, which is characterized in that including：
Substrate, the substrate include >=2 test zones；
An at least row on each test zone of substrate tests syringe needle, and each syringe needle of testing includes the first testing needle, institute
It includes the first noumenon, positioned at first test lead of the first noumenon one end and positioned at the first noumenon other end to state the first testing needle
First connecting pin；Cover the insulating layer on the first noumenon surface of first testing needle；Positioned at surface of insulating layer around described the
Second testing needle of one testing needle, the second testing needle and the first test coaxial needle, the second testing needle include the second ontology, are located at the
Second test lead of two ontology one end and second connection end positioned at the second ontology other end, the second test end surfaces with
First test end surfaces flush；
Wherein, the test syringe needle is made by semiconductor integrated technique, including scheme a, scheme b and scheme c：
Scheme a, the process that test syringe needle is made by semiconductor integrated technique include：The first metal is formed on the substrate
Layer；The first metal layer is etched, forming at least one on each test zone of the substrate arranges the first testing needle；Formation is covered
Cover the insulating thin layer of each first testing needle side wall and top surface；No mask etching technique etches the insulating thin layer and exists
The side wall of first testing needle forms insulating layer；Form the second metal for covering the insulating layer and the first testing needle top surface
Layer；Without second metal layer described in mask etching, the second testing needle is formed in surface of insulating layer；
Scheme b, the process that test syringe needle is made by semiconductor integrated technique include：Sacrificial layer is formed on the substrate, institute
State at least exhausting hole for having in the sacrificial layer on each test zone of substrate and exposing substrate surface；In the through-hole
Full metal is filled, forming at least one on each test zone of substrate arranges the first testing needle；Remove the sacrificial layer；Formation is covered
Cover the insulating thin layer of each first testing needle side wall and top surface；No mask etching technique etches the insulating thin layer and exists
The side wall of first testing needle forms insulating layer；Form the second metal for covering the insulating layer and the first testing needle top surface
Layer；Without second metal layer described in mask etching, the second testing needle is formed in surface of insulating layer；
Scheme c, the process that test syringe needle is made by semiconductor integrated technique include：First testing needle, insulating layer, second
The forming process of testing needle and dielectric layer is：Dielectric layer is formed on the substrate, on each test zone of the substrate
It is formed at least one in dielectric layer and arranges the first through-hole and the annular through-hole around each first through hole, first through hole and annular through-hole
Between be isolated by certain media layer；Metal is filled in first through hole and forms the first testing needle, and gold is filled in annular through-hole
Belong to and form the second testing needle, certain media layer is as insulating layer between the first testing needle and the second testing needle.
2. semiconductor test jig as described in claim 1, which is characterized in that several test syringe needles on each test zone
Several tested terminals in one encapsulating structure to be tested are tested.
3. semiconductor test jig as described in claim 1, which is characterized in that quantity >=2 of the test zone, each
In test zone, the row of the number of rows of syringe needle >=1 is tested, quantity >=2 of syringe needle are tested in each row.
4. semiconductor test jig as described in claim 1, which is characterized in that receive a diameter of the 500 of first testing needle
The width of rice~500 microns, insulating layer is 80 nanometers~400 microns, and the width of the second testing needle is 60 nanometers~300 microns.
5. semiconductor test jig as claimed in claim 4, which is characterized in that the material of the insulating layer is silica, nitrogen
SiClx, silicon oxynitride, fire sand or resin.
6. semiconductor test jig as described in claim 1, which is characterized in that be formed with several signal transmissions in the substrate
Circuit, the signal circuit are suitable for transmitting test signal to test syringe needle when carrying out electrical performance testing, and will test
When the electric signal output that obtains of test syringe needle, each signal circuit is electrically connected with the test syringe needle in corresponding test zone
It connects, each signal circuit includes several first input ends, the first output end, the second input terminal and second output terminal, each
First output end is electrically connected with the first connecting pin of the first testing needle, and each second output terminal is connect with the second of the second testing needle
End electrical connection, the first input end and the second input terminal are electrically connected with external test circuit respectively.
7. semiconductor test jig as described in claim 1, which is characterized in that further include：Dielectric layer in substrate, institute
It states dielectric layer and fills the adjacent space tested between syringe needle and some or all of coverage test syringe needle sidewall surfaces.
8. semiconductor test jig as claimed in claim 7, which is characterized in that the dielectric layer covers the test syringe needle
When whole sidewall surfaces, the surface of the dielectric layer is flushed with the top surface of test syringe needle, further includes：Positioned at dielectric layer and survey
Rebound on test point head has several metal derbies with test needle tip electrical surface contact in the rebound.
9. semiconductor test jig as claimed in claim 7, which is characterized in that the material of the dielectric layer is silica, nitrogen
SiClx, silicon oxynitride, fire sand or resin.
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| CN201410605255.0A CN104407182B (en) | 2014-10-30 | 2014-10-30 | Semiconductor test jig |
| US14/927,693 US10001509B2 (en) | 2014-10-30 | 2015-10-30 | Semiconductor testing fixture and fabrication method thereof |
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| CN201410605255.0A CN104407182B (en) | 2014-10-30 | 2014-10-30 | Semiconductor test jig |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1781028A (en) * | 2003-04-25 | 2006-05-31 | 日本发条株式会社 | Examining instrument for liquid crystal panel |
| CN1936595A (en) * | 2006-09-05 | 2007-03-28 | 杭州高特电子设备有限公司 | Coaxial multi-detection-point detecting rod |
| CN101154609A (en) * | 2006-09-27 | 2008-04-02 | 台湾积体电路制造股份有限公司 | Apparatus and method for testing conductive bumps |
| CN101957389A (en) * | 2009-07-13 | 2011-01-26 | 巧橡科技有限公司 | Test device and manufacturing method thereof |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP5386769B2 (en) * | 2008-09-29 | 2014-01-15 | 日本電産リード株式会社 | Inspection jig |
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2014
- 2014-10-30 CN CN201410605255.0A patent/CN104407182B/en active Active
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1781028A (en) * | 2003-04-25 | 2006-05-31 | 日本发条株式会社 | Examining instrument for liquid crystal panel |
| CN1936595A (en) * | 2006-09-05 | 2007-03-28 | 杭州高特电子设备有限公司 | Coaxial multi-detection-point detecting rod |
| CN101154609A (en) * | 2006-09-27 | 2008-04-02 | 台湾积体电路制造股份有限公司 | Apparatus and method for testing conductive bumps |
| CN101957389A (en) * | 2009-07-13 | 2011-01-26 | 巧橡科技有限公司 | Test device and manufacturing method thereof |
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