CN104393035A - Heterojunction field effect transistor of composite source field plate based on medium modulation - Google Patents
Heterojunction field effect transistor of composite source field plate based on medium modulation Download PDFInfo
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- CN104393035A CN104393035A CN201410658333.3A CN201410658333A CN104393035A CN 104393035 A CN104393035 A CN 104393035A CN 201410658333 A CN201410658333 A CN 201410658333A CN 104393035 A CN104393035 A CN 104393035A
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- 230000005669 field effect Effects 0.000 title claims abstract description 22
- 239000002131 composite material Substances 0.000 title abstract 5
- 239000010410 layer Substances 0.000 claims abstract description 173
- 230000004888 barrier function Effects 0.000 claims abstract description 93
- 238000002161 passivation Methods 0.000 claims abstract description 70
- 238000000034 method Methods 0.000 claims abstract description 62
- 239000011241 protective layer Substances 0.000 claims abstract description 22
- 239000000758 substrate Substances 0.000 claims abstract description 17
- 229910052751 metal Inorganic materials 0.000 claims description 48
- 239000002184 metal Substances 0.000 claims description 48
- 238000000151 deposition Methods 0.000 claims description 29
- 239000000463 material Substances 0.000 claims description 21
- 230000007704 transition Effects 0.000 claims description 18
- 239000004065 semiconductor Substances 0.000 claims description 13
- 230000008021 deposition Effects 0.000 claims description 6
- 238000004151 rapid thermal annealing Methods 0.000 claims description 6
- 239000003989 dielectric material Substances 0.000 claims description 5
- 229910052594 sapphire Inorganic materials 0.000 claims description 5
- 239000010980 sapphire Substances 0.000 claims description 5
- 229910010271 silicon carbide Inorganic materials 0.000 claims description 5
- 239000012298 atmosphere Substances 0.000 claims description 4
- 239000002210 silicon-based material Substances 0.000 claims description 2
- 238000005516 engineering process Methods 0.000 abstract description 47
- 230000008569 process Effects 0.000 abstract description 34
- 230000015556 catabolic process Effects 0.000 abstract description 13
- 238000004519 manufacturing process Methods 0.000 abstract description 4
- 229910002601 GaN Inorganic materials 0.000 description 30
- 238000005530 etching Methods 0.000 description 18
- 230000005684 electric field Effects 0.000 description 17
- QGZKDVFQNNGYKY-UHFFFAOYSA-N Ammonia Chemical compound N QGZKDVFQNNGYKY-UHFFFAOYSA-N 0.000 description 14
- 238000001020 plasma etching Methods 0.000 description 14
- 238000005566 electron beam evaporation Methods 0.000 description 11
- 230000004907 flux Effects 0.000 description 11
- 238000004544 sputter deposition Methods 0.000 description 10
- 230000008020 evaporation Effects 0.000 description 9
- 238000001704 evaporation Methods 0.000 description 9
- 238000005229 chemical vapour deposition Methods 0.000 description 8
- UFHFLCQGNIYNRP-UHFFFAOYSA-N Hydrogen Chemical compound [H][H] UFHFLCQGNIYNRP-UHFFFAOYSA-N 0.000 description 7
- 229910021529 ammonia Inorganic materials 0.000 description 7
- 229910052739 hydrogen Inorganic materials 0.000 description 7
- 239000001257 hydrogen Substances 0.000 description 7
- GYHNNYVSQQEPJS-UHFFFAOYSA-N Gallium Chemical compound [Ga] GYHNNYVSQQEPJS-UHFFFAOYSA-N 0.000 description 6
- 229910052733 gallium Inorganic materials 0.000 description 6
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 description 6
- 229910052782 aluminium Inorganic materials 0.000 description 5
- 238000000231 atomic layer deposition Methods 0.000 description 5
- 238000001451 molecular beam epitaxy Methods 0.000 description 5
- 238000011160 research Methods 0.000 description 5
- 229910004298 SiO 2 Inorganic materials 0.000 description 4
- 239000012159 carrier gas Substances 0.000 description 4
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- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 3
- 238000009826 distribution Methods 0.000 description 3
- 230000000694 effects Effects 0.000 description 3
- 238000001465 metallisation Methods 0.000 description 3
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- 238000000407 epitaxy Methods 0.000 description 2
- 239000007789 gas Substances 0.000 description 2
- 229910052737 gold Inorganic materials 0.000 description 2
- 150000004678 hydrides Chemical class 0.000 description 2
- 229910052759 nickel Inorganic materials 0.000 description 2
- 229920006395 saturated elastomer Polymers 0.000 description 2
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 description 2
- 229910052719 titanium Inorganic materials 0.000 description 2
- 229910002704 AlGaN Inorganic materials 0.000 description 1
- JMASRVWKEDWRBT-UHFFFAOYSA-N Gallium nitride Chemical compound [Ga]#N JMASRVWKEDWRBT-UHFFFAOYSA-N 0.000 description 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical group [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
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- 229910052710 silicon Inorganic materials 0.000 description 1
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- 239000000126 substance Substances 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/402—Field plates
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/778—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface
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Abstract
The invention discloses a heterojunction field effect transistor of a composite source field plate based on medium modulation. The heterojunction field effect transistor of the composite source filed plate based on the medium modulation is mainly used for solving the problem that the process for realizing high breakdown voltage in the existing field plate technology is complex. The heterojunction field effect transistor comprises a substrate (1), a transitional layer (2), a barrier layer (3), a source electrode (4), a drain electrode (5), a table board (6), a passivation layer (9) and a protective layer (13), wherein a gate slot (7) is etched in the barrier layer between the source electrode and the drain electrode; a grid electrode (8) is deposited in the grid slot (7); a groove (10) is etched in the passivation layer (9) between the grid electrode and the drain electrode; a high dielectric constant medium (11) is completely filled in the groove (10); a source field plate (12) is deposited between the passivation layer (9) and the protective layer (13); the source field plate is electrically connected with a source electrode; and the source field plate (12) and the high dielectric constant medium (11) form a composite source field plate. The heterojunction field effect transistor of the composite source filed plate based on the medium modulation has the advantages of a simple manufacturing process, high breakthrough voltage, high field plate efficiency, high reliability and high yield.
Description
Technical field
The invention belongs to technical field of semiconductor device, particularly a kind of multiple source field plate heterojunction field effect transistor based on medium modulation, can be used as the basic device of power electronic system.
Technical background
Power semiconductor is the critical elements of power electronic system, is to carry out electric treatable effective tool.In recent years, along with becoming increasingly conspicuous of the energy and environmental problem, research and development novel high-performance, low-loss power device have become one of the effective way improving utilization rate of electrical, energy savings, alleviating energy crisis.But in power device research, at a high speed, there is serious restricting relation between high pressure and low on-resistance, rationally, effectively improving this restricting relation is the key improving overall device performance.Along with market constantly proposes the requirement of more high efficiency, more small size, higher frequency to power system, traditional Si base semiconductor power device performance has approached its theoretical limit.In order to chip area can be reduced further, improves operating frequency, improve working temperature, reduce conducting resistance, improve puncture voltage, reduce machine volume, improve overall efficiency, take gallium nitride as the semiconductor material with wide forbidden band of representative, by means of the electronics saturation drift velocity of its larger energy gap, higher critical breakdown electric field and Geng Gao, and the outstanding advantages such as stable chemical performance, high temperature resistant, radioresistance, show one's talent preparing in high performance power device, application potential is huge.Particularly adopt the High Electron Mobility Transistor of GaN base heterojunction structure, i.e. GaN base HEMT device, especially because of its characteristic such as low on-resistance, high operate frequency, can meet that electronics of future generation are more high-power to power device, the requirement of higher frequency, more small size and more severe hot operation, in economy and military field, there is wide and special application prospect.
But, there is inherent shortcoming in conventional GaN base HEMT device structure, device channel electric field strength can be caused in deformity distribution, especially near drain electrode, there is high peak electric field at device grids.Cause the puncture voltage of actual GaN base HEMT device often far below theoretical eapectation, and there is the integrity problem such as current collapse, inverse piezoelectric effect, seriously constrain the application and development in field of power electronics.In order to overcome the above problems, domestic and international researchers propose numerous method, and field plate structure be wherein effect significantly, the one that is most widely used.Field plate structure is successfully applied in GaN base HEMT power device by the people such as the N.Q.Zhang of U.S. UCSB in 2000 first, develop overlapping gate device, Saturated output electric current is 500mA/mm, and breakdown voltage can reach 570V, and this is the GaN device that reported puncture voltage is the highest at that time, see Highbreakdown GaN HEMT with overlapping gate structure, IEEE Electron Device Letters, Vol.21, No.9, pp.421-423,2000.Subsequently, research institution of various countries expands relevant research work one after another, and the U.S. and Japan are the main leaders in this field.In the U.S., mainly UCSB, Nan Ka university, Cornell University and famous IR company of power electronic device manufacturer etc. are engaged in the research.Japan starts late relatively, but they pay much attention to the work of this respect, fund input great efforts, and it is numerous to be engaged in mechanism, comprising: the major companies such as Toshiba, Furukawa, Panasonic, Toyota and Fuji.Along with going deep into of research, researchers find correspondingly to increase field plate length, can improve device electric breakdown strength.But the increase of field plate length can make field plate efficiency, namely puncture voltage compares field plate length, continuous reduction, the ability that namely field plate improves device electric breakdown strength is tending towards saturated gradually along with the increase of field plate length, see Enhancement of breakdown voltage in AlGaN/GaN highelectron mobility transistors using a field plate, IEEE Transactions on Electron Devices, Vol.48, No.8, pp.1515-1521, 2001, and Development and characteristic analysis of a field-platedAl
2o
3/ AlInN/GaN MOS HEMT, Chinese Physics B, Vol.20, No.1, pp.0172031-0172035,2011.Therefore, in order to improve device electric breakdown strength further, take into account field plate efficiency simultaneously, the people such as the Wataru Saito of Toshiba Corp in 2008 adopt the double-deck field plate structure of grid field plate and source field plate to have developed double-deck field plate insulated-gate type GaN base HEMT device, this device electric breakdown strength is up to 940V, maximum output current is up to 4.4A, see A 130-W Boost Converter OperationUsing a High-Voltage GaN-HEMT, IEEE Electron Device Letters, Vol.29, No.1, pp.8-10,2008.This double-deck field plate structure has become current being used in the world and has improved GaN base power device breakdown characteristics, improves the main flow field plate techniques of overall device performance.But the complex process of the double-deck field plate HEMT device of GaN base, manufacturing cost is higher, and the making of every one deck field plate all needs the processing steps such as photoetching, depositing metal, deposit dielectric passivation.And under will optimizing each layer field plate, dielectric material thickness maximizes to realize puncture voltage, must carry out loaded down with trivial details process debugging and optimization, therefore considerably increase the difficulty that device manufactures, reduce the rate of finished products of device.
Summary of the invention
The object of the invention is to the deficiency overcoming above-mentioned prior art, the multiple source field plate heterojunction field effect transistor based on medium modulation that a kind of manufacturing process is simple, puncture voltage is high, field plate efficiency is high and reliability is high is provided, to reduce the manufacture difficulty of device, improve breakdown characteristics and the reliability of device, improve the rate of finished products of device.
For achieving the above object, the heterojunction structure that device architecture provided by the invention adopts GaN base semiconductor material with wide forbidden band to form, comprise from bottom to top: substrate, transition zone, barrier layer, passivation layer and protective layer, source electrode, drain electrode is deposited with above barrier layer, table top is carved with in the side of barrier layer, and land depth is greater than the thickness of barrier layer, grid groove is carved with in barrier layer between the source and drain, grid is deposited with in grid groove, it is characterized in that: in passivation layer, be carved with groove, in groove, be filled with high dielectric constant completely; The active field plate of deposit between passivation layer and protective layer, this source field plate and source electrode are electrically connected, and source field plate and high dielectric constant form multiple source field plate structure.
As preferably, the degree of depth h of described grid groove is less than the thickness of barrier layer, the distance r between grid and grid groove left end
1be 0 ~ 2 μm, the distance r between grid and grid groove right-hand member
2be 0 ~ 3 μm, and r
1≤ r
2.
As preferably, described depth of groove s is 0.29 ~ 10.1 μm, and width b is 0.66 ~ 8.6 μm.
As preferably, the distance d between described bottom portion of groove and barrier layer is 0.087 ~ 0.99 μm.
As preferably, described groove is 0.84 ~ 10.4 μm near drain electrode one lateral edges and source field plate near the distance c drained between a lateral edges.
As preferably, described groove is s × (d+s × ε near grid one lateral edges and grid near the distance a drained between a lateral edges
1/ ε
2)
0.5, wherein s is depth of groove, and d is the distance between bottom portion of groove and barrier layer, ε
1for the relative dielectric constant of passivation layer, ε
2for the relative dielectric constant of high dielectric constant.
As preferably, the relative dielectric constant ε of described passivation layer
1with the relative dielectric constant ε of high dielectric constant
2span be 1.5 ~ 2000, and ε
1< ε
2.
For achieving the above object, the present invention makes the method based on the multiple source field plate heterojunction field effect transistor of medium modulation, comprises following process:
The first step, extension GaN base semiconductor material with wide forbidden band on substrate, forms transition zone;
Second step, extension GaN base semiconductor material with wide forbidden band on transition zone, forms barrier layer;
3rd step, on barrier layer, first time makes mask, utilizes this mask at the two ends depositing metal of barrier layer, then at N
2carry out rapid thermal annealing in atmosphere, make source electrode and drain electrode respectively;
4th step, on barrier layer, second time makes mask, and utilize this mask on the left of source electrode, the barrier layer on drain electrode right side etches, and the etched area degree of depth is greater than barrier layer thickness, forms table top;
5th step, on barrier layer, third time makes mask, utilizes in this mask barrier layer between the source and drain and etches, and make grid groove, the degree of depth h of grid groove is less than the thickness of barrier layer;
6th step, barrier layer makes mask the 4th time, utilizes this mask depositing metal in grid groove, make grid, the distance r of grid and grid groove left end
1be 0 ~ 2 μm, the distance r of grid and grid groove right-hand member
2be 0 ~ 3 μm, and r
1≤ r
2;
7th step, respectively on source electrode top, drain electrode top, grid top, other area top of grid groove and other area top deposit passivation layers of barrier layer;
8th step, make mask 5th time over the passivation layer, utilize in the passivation layer of this mask between grid and drain electrode and etch, it is 0.29 ~ 10.1 μm to make degree of depth s, width b is the groove of 0.66 ~ 8.6 μm, distance d between bottom portion of groove and barrier layer is 0.087 ~ 0.99 μm, and this groove is s × (d+s × ε near grid one lateral edges and the close distance a drained between a lateral edges of grid
1/ ε
2)
0.5, wherein s is depth of groove, and d is the distance between bottom portion of groove and barrier layer, ε
1for the relative dielectric constant of passivation layer, ε
2for the relative dielectric constant of high dielectric constant;
9th step, makes mask the 6th time over the passivation layer, utilizes this mask depositing high dielectric constant medium in groove, and the complete filling groove of high dielectric constant;
Tenth step, make mask 7th time over the passivation layer, to utilize on this mask passivation layer between the source and drain and on high dielectric constant all deposition thickness be the metal of 0.34 ~ 2.6 μm, the metal of institute's deposit is 0.84 ~ 10.4 μm near drain electrode one lateral edges and the close distance c drained between a lateral edges of groove, to form source field plate, source field plate and source electrode are electrically connected, this source field plate and high dielectric constant form multiple source field plate again;
11 step, at other area top deposit insulating dielectric materials of field plate top, source and passivation layer, forms protective layer, completes the making of whole device.
Device of the present invention with adopt the HFET of conventional source field plate to compare to have the following advantages:
1. further increase puncture voltage.
The present invention is owing to adopting the multiple source field plate structure based on medium modulation, make device in running order be especially in the operating state of OFF state time, barrier layer surface potential raises from grid gradually to drain electrode, thus add depletion region in barrier layer, i.e. high resistance area, area, improve the distribution of depletion region, impel the depletion region between grid and drain electrode in barrier layer to bear larger drain-source voltage, thus substantially increase the puncture voltage of device.
2. further reduce gate leakage current, improve device reliability.
The present invention is owing to adopting the multiple source field plate structure based on medium modulation, the distribution of electric field line in device barrier layer depletion region is made to obtain more effective modulation, in device, grid is near drain electrode one lateral edges, source field plate all can produce a peak electric field near drain electrode one lateral edges and groove near drain electrode one lateral edges, and pass through the thickness of adjustment source field plate underlying passivation layer, depth of groove and width, the type of high dielectric constant, groove near grid one lateral edges and grid near distance drain between a lateral edges and source field plate near a lateral edges and the close distance drained between a lateral edges of groove of draining, each peak electric field above-mentioned can be made equal and be less than the breakdown electric field of GaN base semiconductor material with wide forbidden band, thus decrease electric field line edge collected by of grid near drain electrode side to greatest extent, significantly reduce the electric field at this place, substantially reduce gate leakage current, the reliability of device and breakdown characteristics is made all to obtain remarkable enhancing.
3. technique is simple, is easy to realize, and improves rate of finished products.
In device architecture of the present invention, the making of source field plate only needs a step process just can complete, and avoids the process complications problem that traditional stack layers field plate structure brings, substantially increases the rate of finished products of device.
Simulation result shows, the puncture voltage of device of the present invention is far longer than the HFET adopting conventional source field plate.
Technology contents of the present invention and effect is further illustrated below in conjunction with drawings and Examples.
Accompanying drawing explanation
Fig. 1 is the structure chart of the HFET adopting conventional source field plate;
Fig. 2 is the structure chart of the multiple source field plate heterojunction field effect transistor that the present invention is based on medium modulation;
Fig. 3 is the Making programme figure of the multiple source field plate heterojunction field effect transistor that the present invention is based on medium modulation;
Fig. 4 is electric field curve diagram in the barrier layer to traditional devices and device simulation gained of the present invention;
Fig. 5 punctures curve chart to traditional devices and device simulation gained of the present invention.
Embodiment
With reference to Fig. 2; the present invention is that it comprises based on GaN base wide bandgap semiconductor heterojunction structure: substrate 1, transition zone 2, barrier layer 3, source electrode 4, drain electrode 5, table top 6, grid groove 7, grid 8, passivation layer 9, groove 10, high dielectric constant 11, source field plate 12 and protective layer 13.Substrate 1, transition zone 2 and barrier layer 3 are for distribute from bottom to top, source electrode 4 and drain electrode 5 are deposited on barrier layer 3, table top 6 is produced on the left of source electrode and drain electrode right side, this land depth is greater than barrier layer thickness, in the barrier layer of grid groove 7 between source electrode and drain electrode, its degree of depth h is less than barrier layer thickness, and grid 8 is deposited in grid groove 7, the distance r between grid and grid groove left end
1be 0 ~ 2 μm, the distance r between grid and grid groove right-hand member
2be 0 ~ 3 μm, and r
1≤ r
2; Passivation layer 9 covers source electrode top, drain electrode top, grid top, other area top of grid groove 7 and other area top of barrier layer respectively.Groove 10 is positioned at passivation layer 9, this depth of groove s is 0.29 ~ 10.1 μm, width b is 0.66 ~ 8.6 μm, distance d bottom groove 10 and between barrier layer is 0.087 ~ 0.99 μm, high dielectric constant 11 is filled in groove 10 completely, and near grid one lateral edges and grid, the distance d bottom the distance a, groove 10 degree of depth s that drain between a lateral edges, groove 10 and between barrier layer meets relation a=s × (d+s × ε to groove 10
1/ ε
2)
0.5, wherein ε
1for the relative dielectric constant of passivation layer, ε
2for the relative dielectric constant of high dielectric constant.Source field plate 12 is deposited between passivation layer 9 and protective layer 13, and this source field plate 12 is electrically connected with source electrode 4.Source field plate is 0.84 ~ 10.4 μm near drain electrode one lateral edges and the close distance c drained between a lateral edges of groove, and this source field plate 12 forms multiple source field plate structure with high dielectric constant 11.Protective layer 13 is positioned at other area top of source field plate 12 top and passivation layer 9.
The substrate 1 of above-mentioned device adopts sapphire or carborundum or silicon materials; Transition zone 2 is made up of the GaN base semiconductor material with wide forbidden band that some layers are identical or different, and its thickness is 1 ~ 5
μm; Barrier layer 3 is made up of the GaN base semiconductor material with wide forbidden band that some layers are identical or different, and its thickness is 5 ~ 50nm; Passivation layer 9 and protective layer 13 all can adopt SiO
2, SiN, Al
2o
3, HfO
2, La
2o
3, TiO
2in any one or other insulating dielectric materials, the thickness of passivation layer is the distance d sum bottom the degree of depth s of groove 10 and groove 10 and between barrier layer 3, namely 0.377 ~ 11.09
μm; The thickness of protective layer 13 is 0.36 ~ 6.4
μm; High dielectric constant 11 can adopt Al
2o
3, HfO
2, La
2o
3, TiO
2, SrTiO
3in any one or other high-k insulating dielectric materials; The relative dielectric constant ε of passivation layer 9
1with the relative dielectric constant ε of high dielectric constant 11
2span be 1.5 ~ 2000, and ε
1< ε
2; Source field plate 12 adopts the combination of three layers of different metal to form, and its thickness is 0.34 ~ 2.6 μm.
With reference to Fig. 3, the present invention makes the process based on the multiple source field plate heterojunction field effect transistor of medium modulation, provides following three kinds of embodiments:
Embodiment one: making substrate is sapphire, passivation layer is Al
2o
3, protective layer is SiO
2, high dielectric constant 11 is HfO
2, source field plate is the multiple source field plate heterojunction field effect transistor based on medium modulation of Ti/Mo/Au metallic combination.
Step 1. is the transition zone 2 of extension GaN material making from bottom to top in Sapphire Substrate 1, as Fig. 3 a.
Use metal organic chemical vapor deposition technology epitaxial thickness in Sapphire Substrate 1 is the transition zone 2 that do not adulterate of 1 μm, and the GaN material that this transition zone is respectively 30nm and 0.97 μm by thickness is from bottom to top formed.The process conditions that extension lower floor GaN material adopts are: temperature is 530 DEG C, and pressure is 45Torr, and hydrogen flowing quantity is 4400sccm, and ammonia flow is 4400sccm, and gallium source flux is 22 μm of ol/min; The process conditions that extension upper strata GaN material adopts are: temperature is 960 DEG C, and pressure is 45Torr, and hydrogen flowing quantity is 4400sccm, and ammonia flow is 4400sccm, and gallium source flux is 130 μm of ol/min.
Step 2. is the unadulterated Al of deposit in GaN transition layer 2
0.5ga
0.5n makes barrier layer 3, as Fig. 3 b.
Use metal organic chemical vapor deposition technology deposition thickness in GaN transition layer 2 to be 5nm, and al composition is the non-doped with Al of 0.5
0.5ga
0.5n barrier layer 3, its process conditions adopted are: temperature is 980 DEG C, and pressure is 45Torr, and hydrogen flowing quantity is 4400sccm, and ammonia flow is 4400sccm, and gallium source flux is 35 μm of ol/min, and aluminium source flux is 7 μm of ol/min.
Step 3. makes source electrode 4 and drain electrode 5, as Fig. 3 c at the two ends depositing metal Ti/Al/Ni/Au of barrier layer 3.
At Al
0.5ga
0.5on N barrier layer 3, first time makes mask, uses electron beam evaporation technique at its two ends depositing metal, then at N
2carry out rapid thermal annealing in atmosphere, make source electrode 4 and drain electrode 5, the metal of wherein institute's deposit is Ti/Al/Ni/Au metallic combination, is namely respectively Ti, Al, Ni and Au from bottom to top, and its thickness is 0.018 μm/0.135 μm/0.046 μm/0.052 μm.The process conditions that depositing metal adopts are: vacuum degree is less than 1.8 × 10
-3pa, power bracket is 200 ~ 1000W, and evaporation rate is less than
the process conditions that rapid thermal annealing adopts are: temperature is 850 DEG C, and the time is 35s.
Step 4. is carried out etching and is made table top 6, as Fig. 3 d on the barrier layer of the source electrode left side with drain electrode the right.
At Al
0.5ga
0.5on N barrier layer 3, second time makes mask, and use reactive ion etching technology to etch on the source electrode left side with the barrier layer on drain electrode the right, form table top 6, etching depth is 10nm.The process conditions that etching adopts are: Cl
2flow is 15sccm, and pressure is 10mTorr, and power is 100W.
Carry out etching in step 5. barrier layer between the source and drain and make grid groove 7, as Fig. 3 e.
At Al
0.5ga
0.5on N barrier layer 3, third time makes mask, and use in reactive ion etching technology barrier layer between the source and drain and etch, making grid groove 7, etching depth h is 2nm.The process conditions that etching adopts are: Cl
2flow is 15sccm, and pressure is 10mTorr, and power is 100W.
Step 6. depositing metal Ni/Au in grid groove 7 makes grid 8, as Fig. 3 f.
At Al
0.5ga
0.5n barrier layer 3 makes mask the 4th time, uses electron beam evaporation technique depositing metal in grid groove 7, make grid 8, wherein the metal of institute's deposit is Ni/Au metallic combination, namely lower floor is Ni, upper strata is Au, and its thickness is 0.039 μm/0.24 μm, the distance r between grid and grid groove left end
1be 0 μm, the distance r between grid and grid groove right-hand member
2it is 0 μm.The process conditions that depositing metal adopts are: vacuum degree is less than 1.8 × 10
-3pa, power bracket is 200 ~ 1000W, and evaporation rate is less than
Step 7. on source electrode top, drain electrode top, grid top, other area top of grid groove and other area top deposits Al of barrier layer
2o
3passivation layer 9, as Fig. 3 g.
Use atomic layer deposition technology to cover source electrode top, drain electrode top, grid top, other area top of grid groove and other area top of barrier layer respectively, complete the Al that deposition thickness is 0.377 μm
2o
3passivation layer 9.The process conditions that deposit passivation layer adopts are: with TMA and H
2o is reaction source, and carrier gas is N
2, carrier gas flux is 200sccm, and underlayer temperature is 300 DEG C, and air pressure is 700Pa.
Carry out etching in the passivation layer of step 8. between grid 8 and drain electrode 5 and make groove 10, as Fig. 3 h.
Passivation layer 9 makes mask the 5th time, use in the passivation layer of reactive ion etching technology between grid 8 and drain electrode 5 and etch, to make groove 10, its further groove 10 degree of depth s is 0.29 μm, width b is 0.66 μm, distance d bottom groove 10 and between barrier layer is 0.087 μm, and groove 10 is 0.127 μm near grid one lateral edges and the close distance a drained between a lateral edges of grid.The process conditions that etching adopts are: CF
4flow is 45sccm, O
2flow is 5sccm, and pressure is 15mTorr, and power is 250W.
Step 9. is deposit HfO in groove 10
2high dielectric constant 11, and complete filling groove 10, as Fig. 3 i.
Passivation layer 9 makes mask the 6th time, uses superconducting RF technology deposit HfO in groove 10
2high dielectric constant 11, institute deposit HfO
2high dielectric constant 11 wants complete filling groove 10.Deposit HfO
2the process conditions that high dielectric constant 11 adopts are: reative cell sputtering pressure remains on about 0.1Pa, O
2be respectively 1sccm and 8sccm with the flow of Ar, substrate temperature is fixed on 200 DEG C, and Hf target radio-frequency power is 150W.
Step 10. passivation layer top between the source and drain and high dielectric constant 11 top depositing metal Ti/Mo/Au make source field plate 12, as Fig. 3 j.
Passivation layer 9 makes mask the 7th time, use electron beam evaporation technique passivation layer top between the source and drain and high dielectric constant 11 top depositing metal, this metal is 0.84 μm near drain electrode one lateral edges and the close distance c drained between a lateral edges of groove, the metal of institute's deposit is Ti/Mo/Au metallic combination, namely lower floor is Ti, middle level is Mo, upper strata is Au, its thickness is 0.15 μm/0.12 μm/0.07 μm, to form source field plate 12, again source field plate and source electrode are electrically connected, this source field plate 12 forms multiple source field plate with high dielectric constant 11.The process conditions that depositing metal adopts are: vacuum degree is less than 1.8 × 10
-3pa, power bracket is 200 ~ 1000W, and evaporation rate is less than
Step 11. is at other area top deposit SiO of source field plate 12 top and passivation layer 9
2make protective layer 13, as Fig. 3 k.
Use plasma enhanced CVD technology at other area top deposit SiO of source field plate 12 top and passivation layer 9
2make protective layer 13, its thickness is 0.36 μm, thus completes the making of whole device, and the process conditions that deposit protective layer adopts are: N
2o flow is 850sccm, SiH
4flow is 200sccm, and temperature is 250 DEG C, and RF power is 25W, and pressure is 1100mTorr.
Embodiment two: making substrate is carborundum, passivation layer is SiO
2, protective layer is SiN, and high dielectric constant 11 is Al
2o
3, source field plate is the multiple source field plate heterojunction field effect transistor based on medium modulation of Ti/Ni/Au metallic combination.
Step one. in silicon carbide substrates 1, extension AlN and GaN material make transition zone 2 from bottom to top, as Fig. 3 a.
1.1) the unadulterated AlN material that metal organic chemical vapor deposition technology epitaxial thickness in silicon carbide substrates 1 is 50nm is used; The process conditions of its extension are: temperature is 1000 DEG C, and pressure is 45Torr, and hydrogen flowing quantity is 4600sccm, and ammonia flow is 4600sccm, and aluminium source flux is 5 μm of ol/min;
1.2) use metal organic chemical vapor deposition technology epitaxial thickness on AlN material to be the GaN material of 2.45 μm, complete the making of transition zone 2; The process conditions of its extension are: temperature is 1000 DEG C, and pressure is 45Torr, and hydrogen flowing quantity is 4600sccm, and ammonia flow is 4600sccm, and gallium source flux is 130 μm of ol/min.
The extension of this step is not limited to metal organic chemical vapor deposition technology, also can adopt molecular beam epitaxy technique or hydride gas-phase epitaxy technology.
Step 2. extension Al from bottom to top on transition zone 2
0.3ga
0.7n and GaN material make barrier layer 3, as Fig. 3 b.
2.1) use that metal organic chemical vapor deposition technology deposition thickness on transition zone 2 is 27nm, al composition is the Al of 0.3
0.3ga
0.7n material; The process conditions of its extension are: temperature is 1300 DEG C, and pressure is 45Torr, and hydrogen flowing quantity is 4600sccm, and ammonia flow is 4600sccm, and gallium source flux is 16 μm of ol/min, and aluminium source flux is 8 μm of ol/min;
2.2) use metal organic chemical vapor deposition technology at Al
0.3ga
0.7on N material, epitaxial thickness is the GaN material of 3nm, completes the making of barrier layer 3; The process conditions of its extension are: temperature is 1200 DEG C, and pressure is 46Torr, and hydrogen flowing quantity is 4650sccm, and ammonia flow is 4650sccm, and gallium source flux is 18 μm of ol/min.
The extension of this step is not limited to metal organic chemical vapor deposition technology, also can adopt molecular beam epitaxy technique or hydride gas-phase epitaxy technology.
Step 3. make source electrode 4 and drain electrode 5, as Fig. 3 c at the two ends depositing metal Ti/Al/Ni/Au of barrier layer 3.
3.1) on barrier layer 3, first time makes mask, use electron beam evaporation technique at its two ends depositing metal, the metal of deposit is Ti/Al/Ni/Au metallic combination, namely Ti, Al, Ni and Au is respectively from bottom to top, its thickness is 0.018 μm/0.135 μm/0.046 μm/0.052 μm, and its depositing metal process conditions are: vacuum degree is less than 1.8 × 10
-3pa, power bracket is 200 ~ 1000W, and evaporation rate is less than
3.2) at N
2carry out rapid thermal annealing in atmosphere, complete the making of source electrode 4 and drain electrode 5, the process conditions of its rapid thermal annealing are: temperature is 850 DEG C, and the time is 35s.
The Metal deposition of this step is not limited to electron beam evaporation technique, also can adopt sputtering technology.
Step 4. on the barrier layer 3 on the left side of source electrode and the right of drain electrode, carry out etching make table top 6, as Fig. 3 d.
On barrier layer 3, second time makes mask, and use reactive ion etching technology to etch on the source electrode left side with the barrier layer 3 on drain electrode the right, form table top 6, wherein etching depth is 100nm; The process conditions that reactive ion etching technology etching table top 6 adopts are: Cl
2flow is 15sccm, and pressure is 10mTorr, and power is 100W.
The etching of this step is not limited to reactive ion etching technology, also can adopt sputtering technology or plasma etching technology.
Step 5. carry out etching in barrier layer between the source and drain and make grid groove 7, as Fig. 3 e.
On barrier layer 3, third time makes mask, and use in reactive ion etching technology barrier layer between the source and drain and etch, making grid groove 7, etching depth h is 20nm.The process conditions that etching adopts are: Cl
2flow is 15sccm, and pressure is 10mTorr, and power is 100W.
The etching of this step is not limited to reactive ion etching technology, also can adopt sputtering technology or plasma etching technology.
Step 6. in grid groove 7, depositing metal Ni/Au makes grid 8, as Fig. 3 f.
Barrier layer 3 makes mask the 4th time, uses electron beam evaporation technique depositing metal in grid groove 7, make grid 8, the metal of wherein institute's deposit is Ni/Au metallic combination, and its thickness is 0.039 μm/0.24 μm, the distance r between grid and grid groove left end
1be 1 μm, the distance r between grid and grid groove right-hand member
2it is 2 μm.The process conditions that electron beam evaporation technique deposit Ni/Au adopts are: vacuum degree is less than 1.8 × 10
-3pa, power bracket is 200 ~ 1000W, and evaporation rate is less than
The Metal deposition of this step is not limited to electron beam evaporation technique, also can adopt sputtering technology.
Step 7. on source electrode top, drain top, grid top, other area top of grid groove 7 and other area top deposits SiO of barrier layer
2make passivation layer 9, as Fig. 3 g.
Use plasma enhanced CVD technology to cover source electrode top, drain electrode top, grid top, other area top of grid groove 7 and other area top of barrier layer respectively, complete the SiO that deposition thickness is 6.3 μm
2passivation layer 9; Its process conditions adopted are: N
2o flow is 850sccm, SiH
4flow is 200sccm, and temperature is 250 DEG C, and RF power is 25W, and pressure is 1100mTorr.
The deposit of the passivation layer of this step is not limited to plasma enhanced CVD technology, also can adopt evaporation technique or atomic layer deposition technology or sputtering technology or molecular beam epitaxy technique.
Step 8. carry out etching in the passivation layer 9 between grid 8 and drain electrode 5 and make groove 10, as Fig. 3 h.
Passivation layer 9 makes mask the 5th time, use in the passivation layer of reactive ion etching technology between grid 8 and drain electrode 5 and etch, to make groove 10, its further groove 10 degree of depth s is 5.8 μm, width b is 4.5 μm, distance d bottom groove 10 and between barrier layer is 0.5 μm, and groove 10 is 10.068 μm near grid one lateral edges and the close distance a drained between a lateral edges of grid; The process conditions that reactive ion etching technology etched recesses 10 adopts are: CF
4flow is 45sccm, O
2flow is 5sccm, and pressure is 10mTorr, and power is 100W.
The etching of this step is not limited to reactive ion etching technology, also can adopt sputtering technology or plasma etching technology.
Step 9. deposit Al in groove 10
2o
3high dielectric constant 11, and complete filling groove 10, as Fig. 3 i.
Passivation layer 9 makes mask the 6th time, uses atomic layer deposition technology deposit Al in groove 10
2o
3high dielectric constant 11, institute deposit Al
2o
3high dielectric constant 11 wants complete filling groove 10.Deposit Al
2o
3the process conditions that high dielectric constant 11 adopts are: with TMA and H
2o is reaction source, and carrier gas is N
2, carrier gas flux is 200sccm, and underlayer temperature is 300 DEG C, and air pressure is 700Pa.
The deposit of the high dielectric constant of this step is not limited to atomic layer deposition technology, also can adopt evaporation technique or plasma enhanced CVD technology or sputtering technology or molecular beam epitaxy technique.
Step 10. passivation layer top between the source and drain and high dielectric constant 11 top depositing metal Ti/Ni/Au make source field plate 12, as Fig. 3 j.
Passivation layer 9 makes mask the 7th time, use electron beam evaporation technique passivation layer top between the source and drain and high dielectric constant 11 top depositing metal, this metal is 7.1 μm near drain electrode one lateral edges and the close distance c drained between a lateral edges of groove, the metal of institute's deposit is Ti/Ni/Au metallic combination, namely lower floor is Ti, middle level is Ni, upper strata is Au, its thickness is 0.8 μm/0.6 μm/0.4 μm, to form source field plate 12, again source field plate and source electrode are electrically connected, this source field plate 12 forms multiple source field plate with high dielectric constant 11.The process conditions that electron beam evaporation technique deposit Ti/Ni/Au adopts are: vacuum degree is less than 1.8 × 10
-3pa, power bracket is 200 ~ 1000W, and evaporation rate is less than
The Metal deposition of this step is not limited to electron beam evaporation technique, also can adopt sputtering technology.
Step 11. make protective layer 13, as Fig. 3 k at other area top deposit SiN of source field plate 12 top and passivation layer 9.
Use plasma enhanced CVD technology to make protective layer 13 at other area top deposit SiN of source field plate 12 top and passivation layer 9, its thickness is 3.8 μm, thus completes the making of whole device; Its process conditions adopted are: gas is NH
3, N
2and SiH
4, gas flow is respectively 2.5sccm, 950sccm and 250sccm, and temperature, RF power and pressure are respectively 300 DEG C, 25W and 950mTorr.
The deposit of the protective layer of this step is not limited to plasma enhanced CVD technology, also can adopt evaporation technique or atomic layer deposition technology or sputtering technology or molecular beam epitaxy technique.
Embodiment three: making substrate is silicon, passivation layer is SiN, and protective layer is SiO
2, high dielectric constant 11 is HfO
2, source field plate is the multiple source field plate heterojunction field effect transistor based on medium modulation of Ti/Pt/Au metallic combination.
Steps A. on silicon substrate 1, extension AlN and GaN material make transition zone 2 from bottom to top, as Fig. 3 a.
A1) metal organic chemical vapor deposition technology is used to be 800 DEG C in temperature, pressure is 40Torr, and hydrogen flowing quantity is 4000sccm, and ammonia flow is 4000sccm, aluminium source flux is under the process conditions of 25 μm of ol/min, and on silicon substrate 1, epitaxial thickness is the AlN material of 200nm;
A2) metal organic chemical vapor deposition technology is used to be 980 DEG C in temperature, pressure is 45Torr, hydrogen flowing quantity is 4000sccm, ammonia flow is 4000sccm, gallium source flux is under the process conditions of 130 μm of ol/min, on AlN material, epitaxial thickness is the GaN material of 4.8 μm, completes the making of transition zone 2.
Step B. deposit Al from bottom to top on transition zone
0.1ga
0.9n and GaN material make barrier layer 3, as Fig. 3 b.
B1) metal organic chemical vapor deposition technology is used to be 1000 DEG C in temperature, pressure is 40Torr, hydrogen flowing quantity is 4000sccm, ammonia flow is 4000sccm, gallium source flux is 13 μm of ol/min, aluminium source flux is under the process conditions of 13 μm of ol/min, and on transition zone 2, epitaxial thickness is 46nm, al composition is the Al of 0.1
0.1ga
0.9n material;
B2) use metal organic chemical vapor deposition technology to be 1000 DEG C in temperature, pressure is 40Torr, and hydrogen flowing quantity is 4000sccm, and ammonia flow is 4000sccm, and gallium source flux is under the process conditions of 3 μm of ol/min, at Al
0.1ga
0.9on N material, epitaxial thickness is the GaN material of 4nm, completes the making of barrier layer 3.
Step C. makes source electrode 4 and drain electrode 5, as Fig. 3 c at barrier layer 3 two ends depositing metal Ti/Al/Ni/Au.
C1) on barrier layer 3, first time makes mask, uses electron beam evaporation technique to be less than 1.8 × 10 in vacuum degree
-3pa, power bracket is 200 ~ 1000W, and evaporation rate is less than
process conditions under, at its two ends depositing metal, the metal of wherein institute's deposit is Ti/Al/Ni/Au metallic combination, is namely respectively Ti, Al, Ni and Au from bottom to top, and its thickness is 0.018 μm/0.135 μm/0.046 μm/0.052 μm;
C2) at N
2atmosphere, temperature is 850 DEG C, and the time is carry out rapid thermal annealing under the process conditions of 35s, completes the making of source electrode 4 and drain electrode 5.
Step D. carries out etching and makes table top 6, as Fig. 3 d on the barrier layer 3 of the source electrode left side with drain electrode the right.
On barrier layer 3, second time makes mask, uses reactive ion etching technology at Cl
2flow is 15sccm, and pressure is 10mTorr, and power is under the process conditions of 100W, and the source electrode left side with the barrier layer 3 on drain electrode the right etch, and form table top 6, wherein etching depth is 200nm.
Step e. carry out etching in barrier layer between the source and drain and make grid groove 7, as Fig. 3 e.
On barrier layer 3, third time makes mask, uses reactive ion etching technology at Cl
2flow is 15sccm, and pressure is 10mTorr, and power is under the process conditions of 100W, etches in barrier layer between the source and drain, and making grid groove 7, its degree of depth h is 30nm.
Step F. in grid groove 7, depositing metal Ni/Au makes grid 8, as Fig. 3 f.
Barrier layer 3 makes mask the 4th time, uses electron beam evaporation technique to be less than 1.8 × 10 in vacuum degree
-3pa, power bracket is 200 ~ 1000W, and evaporation rate is less than
process conditions under, depositing metal in grid groove 7, make grid 8, the metal of institute's deposit is Ni/Au metallic combination, and namely lower floor is Ni, upper strata is Au, and its thickness is 0.039 μm/0.24 μm, the distance r between grid and grid groove left end
1be 2 μm, the distance r between grid and grid groove right-hand member
2it is 3 μm.
Step G. on source electrode top, drain electrode top, grid top, other area top of grid groove and barrier layer other area top deposits SiN material make passivation layer 9, as Fig. 3 g.
Plasma enhanced CVD technology is used to be NH at gas
3, N
2and SiH
4gas flow is respectively 2.5sccm, 950sccm and 250sccm, temperature, RF power and pressure are respectively 300 DEG C, under the process conditions of 25W and 950mTorr, and on source electrode top, drain electrode top, grid top, other area top of grid groove and other area top deposition thicknesses of barrier layer are that the SiN of 11.09 μm makes passivation layer 9.
Carry out etching in the passivation layer 9 of step H. between grid 8 and drain electrode 5 and make groove 10, as Fig. 3 h.
Passivation layer 9 makes mask the 5th time, uses reactive ion etching technology at CF
4flow is 45sccm, O
2flow is 5sccm, pressure is 10mTorr, power is under the process conditions of 100W, etch in passivation layer between grid 8 and drain electrode 5, to make groove 10, its further groove 10 degree of depth s is 10.1 μm, and width b is 8.6 μm, distance d bottom groove 10 and between barrier layer is 0.99 μm, and groove 10 is 19.735 μm near grid one lateral edges and the close distance a drained between a lateral edges of grid.
Step I. is deposit HfO in groove 10
2high dielectric constant 11, and complete filling groove, as Fig. 3 i.
Passivation layer 9 makes mask the 6th time, uses superconducting RF technology to remain on about 0.1Pa at reative cell sputtering pressure, O
2be respectively 1sccm and 8sccm with the flow of Ar, substrate temperature is fixed on 200 DEG C, and Hf target radio-frequency power is under the process conditions of 150W, deposit HfO in groove 10
2high dielectric constant 11, institute deposit HfO
2high dielectric constant 11 wants complete filling groove 10.
Passivation layer top and the high dielectric constant 11 top depositing metal Ti/Pt/Au of step J. between source electrode and drain electrode, making source field plate 12, as Fig. 3 j.
Passivation layer 9 makes mask the 7th time, uses electron beam evaporation technique to be less than 1.8 × 10 in vacuum degree
-3pa, power bracket is 200 ~ 1000W, and evaporation rate is less than
process conditions under, passivation layer top between source electrode and drain electrode and high dielectric constant 11 top depositing metal, this metal is 10.4 μm near drain electrode one lateral edges and the close distance c drained between a lateral edges of groove, the metal of institute's deposit is the metallic combination of Ti/Pt/Au, namely lower floor is Ti, middle level is Pt, upper strata is Au, its thickness is 1.1 μm/0.9 μm/0.6 μm, to form source field plate 12, source field plate and source electrode are electrically connected, source field plate and high dielectric constant 11 form multiple source field plate again.
Step K. at other area top deposit SiO of source field plate 12 top and passivation layer 9
2, make protective layer 13, as Fig. 3 k.
Plasma enhanced CVD technology is used to be N at gas
2o and SiH
4, gas flow is respectively 850sccm and 200sccm, and temperature is 250 DEG C, and RF power is 25W, and pressure is under the process conditions of 1300mTorr, at other area top deposit SiO of source field plate 12 top and passivation layer 9
2make protective layer 13, its thickness is 6.4 μm, thus completes the making of whole device.
Effect of the present invention further illustrates by following emulation.
Emulation 1: emulate the electric field adopted in the barrier layer of HFET of conventional source field plate and the barrier layer of device of the present invention, result is as Fig. 4, and wherein conventional source field plate effective length L is equal with the source of the present invention effective total length of field plate.
As seen from Figure 4: adopt the electric field curve of HFET in barrier layer of conventional source field plate only to define 2 approximately equalised peak electric field, the area that its electric field curve in barrier layer covers is very little, and the electric field curve of device of the present invention in barrier layer defines 3 approximately equalised peak electric field, the area that the electric field curve of device of the present invention in barrier layer is covered increases greatly, the area approximation covered due to the electric field curve in barrier layer equals the puncture voltage of device, illustrate that the puncture voltage of device of the present invention is far longer than the puncture voltage of the HFET adopting conventional source field plate.
Emulation 2: emulate the breakdown characteristics of the HFET and device of the present invention that adopt conventional source field plate, result is as Fig. 5.
As seen from Figure 5, the HFET of conventional source field plate is adopted to puncture, namely drain current increases sharply, time drain-source voltage greatly about 620V, and the drain-source voltage of device of the present invention when puncturing is greatly about 1710V, prove that the puncture voltage of device of the present invention is far longer than the puncture voltage of the HFET adopting conventional source field plate, this conclusion is consistent with the conclusion of accompanying drawing 4.
For those skilled in the art; after having understood content of the present invention and principle; can when not deviating from the principle and scope of the present invention; carry out various correction in form and details and change according to method of the present invention, but these are based on correction of the present invention with change still within claims of the present invention.
Claims (10)
1. the multiple source field plate heterojunction field effect transistor based on medium modulation; comprise from bottom to top: substrate (1), transition zone (2), barrier layer (3), passivation layer (9) and protective layer (13); source electrode (4) and drain electrode (5) is deposited with above barrier layer (3); table top (6) is carved with in the side of barrier layer (3); and land depth is greater than the thickness of barrier layer; grid groove (7) is carved with in barrier layer between the source and drain; in grid groove (7), be deposited with grid (8), it is characterized in that:
Be carved with groove (10) in passivation layer (9), in groove (10), be filled with high dielectric constant (11) completely;
The active field plate of deposit (12) between passivation layer (9) and protective layer (13); this source field plate (12) and source electrode (4) are electrically connected, and source field plate (12) and high dielectric constant (11) form multiple source field plate structure.
2. the multiple source field plate heterojunction field effect transistor based on medium modulation according to claim 1, is characterized in that the degree of depth h of grid groove (7) is less than the thickness of barrier layer, the distance r between grid and grid groove left end
1be 0 ~ 2 μm, the distance r between grid and grid groove right-hand member
2be 0 ~ 3 μm, and r
1≤ r
2.
3. the multiple source field plate heterojunction field effect transistor based on medium modulation according to claim 1, it is characterized in that the degree of depth s of groove (10) is 0.29 ~ 10.1 μm, width b is 0.66 ~ 8.6 μm; Distance d between groove (10) bottom and barrier layer (3) is 0.087 ~ 0.99 μm, and source field plate (12) is 0.84 ~ 10.4 μm near drain electrode one lateral edges and the close distance c drained between a lateral edges of groove (10).
4. the multiple source field plate heterojunction field effect transistor based on medium modulation according to claim 1, the relative dielectric constant ε of its feature passivation layer
1with the relative dielectric constant ε of high dielectric constant
2span be 1.5 ~ 2000, and ε
1< ε
2.
5. the multiple source field plate heterojunction field effect transistor based on medium modulation according to claim 1, is characterized in that groove (10) is s × (d+s × ε near grid one lateral edges and the close distance a drained between a lateral edges of grid (8)
1/ ε
2)
0.5, wherein s is depth of groove, and d is the distance between bottom portion of groove and barrier layer, ε
1for the relative dielectric constant of passivation layer, ε
2for the relative dielectric constant of high dielectric constant.
6. the multiple source field plate heterojunction field effect transistor based on medium modulation according to claim 1, is characterized in that substrate (1) adopts sapphire or carborundum or silicon materials.
7. make the method based on the multiple source field plate heterojunction field effect transistor of medium modulation, comprise the steps:
The first step, at the upper extension GaN base semiconductor material with wide forbidden band of substrate (1), forms transition zone (2);
Second step, at the upper extension GaN base semiconductor material with wide forbidden band of transition zone (2), forms barrier layer (3);
3rd step, made mask in barrier layer (3) upper first time, and utilized this mask at the two ends depositing metal of barrier layer (3), then at N
2carry out rapid thermal annealing in atmosphere, make source electrode (4) and drain electrode (5) respectively;
4th step, makes mask, utilize this mask on the left of source electrode, the barrier layer on drain electrode right side etches, and the etched area degree of depth is greater than barrier layer thickness, forms table top (6) in the upper second time of barrier layer (3);
5th step, mask was made in barrier layer (3) upper third time, utilize in the barrier layer (3) of this mask between source electrode (4) and drain electrode (5) and etch, make grid groove (7), the degree of depth h of grid groove (7) is less than the thickness of barrier layer;
6th step, makes mask upper 4th time at barrier layer (3), utilizes this mask depositing metal in grid groove (7), make grid (8), the distance r of grid and grid groove left end
1be 0 ~ 2 μm, the distance r of grid and grid groove right-hand member
2be 0 ~ 3 μm, and r
1≤ r
2;
7th step, respectively on source electrode top, drain electrode top, grid top, other area top of grid groove and other area top deposit passivation layers (9) of barrier layer;
8th step, mask is made upper 5th time at passivation layer (9), utilize in the passivation layer (9) of this mask between grid and drain electrode and etch, it is 0.29 ~ 10.1 μm to make degree of depth s, width b is the groove (10) of 0.66 ~ 8.6 μm, distance d between groove (10) bottom and barrier layer (3) is 0.087 ~ 0.99 μm, and this groove is s × (d+s × ε near grid one lateral edges and the close distance a drained between a lateral edges of grid
1/ ε
2)
0.5, wherein s is depth of groove, and d is the distance between bottom portion of groove and barrier layer, ε
1for the relative dielectric constant of passivation layer, ε
2for the relative dielectric constant of high dielectric constant;
9th step, mask is made upper 6th time at passivation layer (9), utilize this mask depositing high dielectric constant medium (11) in groove (10), and high dielectric constant (11) filling groove (10) completely;
Tenth step, mask is made upper 7th time at passivation layer (9), upper and the high dielectric constant (11) of this mask passivation layer between the source and drain (9) is utilized to go up the metal that equal deposition thickness is 0.34 ~ 2.6 μm, the metal of institute's deposit is 0.84 ~ 10.4 μm near drain electrode one lateral edges and the close distance c drained between a lateral edges of groove (10), to form source field plate (12), source field plate (12) and source electrode (4) are electrically connected, this source field plate (12) and high dielectric constant (11) form multiple source field plate again;
11 step, at other area top deposit insulating dielectric materials of source field plate (12) top and passivation layer (9), forms protective layer (13), completes the making of whole device.
8. method according to claim 7, to it is characterized in that in described tenth step that the metal of passivation layer top between the source and drain and the deposit of high dielectric constant top adopts three-layer metal combination Ti/Mo/Au, namely lower floor is Ti, middle level is Mo, upper strata is Au, and its thickness is 0.15 ~ 1.1 μm/0.12 ~ 0.9 μm/0.07 ~ 0.6 μm.
9. method according to claim 7, to it is characterized in that in described tenth step the metal of passivation layer top between the source and drain and the deposit of high dielectric constant top institute, adopt three-layer metal combination Ti/Ni/Au, namely lower floor is Ti, middle level is Ni, upper strata is Au, and its thickness is 0.15 ~ 1.1 μm/0.12 ~ 0.9 μm/0.07 ~ 0.6 μm.
10. method according to claim 7, to it is characterized in that in described tenth step the metal of passivation layer top between the source and drain and the deposit of high dielectric constant top, further employing three-layer metal combination Ti/Pt/Au, namely lower floor is Ti, middle level is Pt, upper strata is Au, and its thickness is 0.15 ~ 1.1 μm/0.12 ~ 0.9 μm/0.07 ~ 0.6 μm.
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
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| CN111834455A (en) * | 2020-07-28 | 2020-10-27 | 西安电子科技大学 | Enhanced high electron mobility transistor and manufacturing method thereof |
| CN111863961A (en) * | 2020-07-28 | 2020-10-30 | 西安电子科技大学 | Heterojunction field effect transistor |
| CN112466928A (en) * | 2020-12-15 | 2021-03-09 | 南京工业职业技术大学 | GaN HEMT device capable of optimizing breakdown characteristic and reverse characteristic simultaneously |
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| CN107123593A (en) * | 2017-04-11 | 2017-09-01 | 山东大学 | One kind mixes germanium carborundum Ohmic contact forming method |
| CN111834455A (en) * | 2020-07-28 | 2020-10-27 | 西安电子科技大学 | Enhanced high electron mobility transistor and manufacturing method thereof |
| CN111863961A (en) * | 2020-07-28 | 2020-10-30 | 西安电子科技大学 | Heterojunction field effect transistor |
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| CN112466928A (en) * | 2020-12-15 | 2021-03-09 | 南京工业职业技术大学 | GaN HEMT device capable of optimizing breakdown characteristic and reverse characteristic simultaneously |
| CN112466928B (en) * | 2020-12-15 | 2021-11-30 | 南京工业职业技术大学 | GaN HEMT device capable of optimizing breakdown characteristic and reverse characteristic simultaneously and manufacturing process thereof |
| CN113437136A (en) * | 2021-06-28 | 2021-09-24 | 深圳市时代速信科技有限公司 | Semiconductor device and preparation method thereof |
| WO2024016219A1 (en) * | 2022-07-20 | 2024-01-25 | Innoscience (suzhou) Semiconductor Co., Ltd. | Nitride-based semiconductor device and method for manufacturing the same |
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