CN104378818A - Clock synchronization method and device and base station subsystem - Google Patents
Clock synchronization method and device and base station subsystem Download PDFInfo
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- CN104378818A CN104378818A CN201310351739.2A CN201310351739A CN104378818A CN 104378818 A CN104378818 A CN 104378818A CN 201310351739 A CN201310351739 A CN 201310351739A CN 104378818 A CN104378818 A CN 104378818A
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
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- H04W56/0035—Synchronisation arrangements detecting errors in frequency or phase
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Abstract
The invention provides a clock synchronization method and device for BTSs and a base station subsystem. The clock synchronization method comprises the steps that a reference BTS and a target BTS to be synchronized are determined, the clock difference parameter between the reference BTS and the target BTS is calculated, a clock synchronization function is obtained according to the clock difference parameter, and clock synchronization is conducted on the target BTS according to the clock synchronization function. According to the clock synchronization method and device and the base station subsystem, the reference BTS and the target BTS are selected from multiple BTSs, the clock synchronization function for the target BTS is obtained according to the clock difference parameter between the reference BTS and the target BTS, clock synchronization is conducted on the target BTS according to the clock synchronization function, in this way, the clock of the target BTS and the clock of the reference BTS are made consistent, and the effect that the clocks of all BTSs in a BSS are completely synchronous with the clock of the reference BTS is achieved; due to the fact that no equipment needs to be additionally arranged, cost for clock synchronization of the BTSs is reduced.
Description
Technical field
The present invention relates to the communications field, particularly relate to a kind of for the clock synchronizing method between base transceiver station and device, base station sub-system.
Background technology
Along with the development of the communication technology, the function of communication network is also day by day perfect, and as communication functions such as DFCA, IRC, SAIC, but the realization of these functions depends on the steady operation of communication base station.For gsm system, gsm system comprises multiple base station sub-system BSS, known with reference to Fig. 1, and each base station sub-system BSS divides into a base station controller BSC and plural base transceiver station BTS(as BTS1, BTS2 and the BTS3 in Fig. 1);
Because the crystal oscillator of each BTS is different, after a period of operation, the clock of each BTS just there will be difference, when the clock of BTS1, BTS2 and BTS3 is inconsistent, the random overlapping of communication data between different time-gap will be caused, bring unnecessary and unpredictable and interference that is that evade, some technology cannot be implemented (as DFCA), and the Be very effective of other technology declines (as IRC, SAIC).
At present, solve each BTS clock diverse ways mainly increases GPS device respectively in each BTS, corrects self clock, utilizes the consistency of clock between GPS device, reach the effect of clock synchronous between each BTS according to each gps clock; But this scheme needs, for each BTS increases a GPS device, to cause the job costs realizing the program excessive.
Therefore, providing the method for clock synchronous between a kind of BTS to solve the excessive problem of prior art cost, is those skilled in the art's technical problems urgently to be resolved hurrily.
Summary of the invention
The invention provides a kind of clock synchronizing method for BTS and device, base station sub-system, the problem that the cost existed when solving clock synchronous between each BTS of existing techniques in realizing is excessive.
The invention provides a kind of clock synchronizing method for BTS, in one embodiment, the method comprises: the target base transceiver station determining Reference BTS transceiver station and a process to be synchronized; Clock difference parameter between Calculation Basis base transceiver station and target base transceiver station; Clock synchronous function is obtained according to clock difference parameter; According to clock synchronous function, clock synchronous process is carried out to target base transceiver station.
Further, the clock synchronous function in above-described embodiment is n rank linear functions, n≤1.
Further, the clock difference parameter in above-described embodiment comprises: Reference BTS transceiver station is to the clock difference parameter in target base transceiver station direction and/or target base transceiver station to the clock difference parameter in Reference BTS transceiver station direction.
Further, the clock synchronizing method in above-described embodiment also comprised before carrying out linear regression processing to clock difference parameter: carry out merging treatment to clock difference parameter, and/or carried out correcting process to clock difference parameter.
Further, in the above-described embodiments, the step that clock difference parameter carries out linear regression processing is specially: carry out linear regression processing the computing time respective with it to clock difference parameter and obtain clock synchronous function; Clock synchronous function is first order linear function: Y=a+b*t, wherein, Y represents the clock adjustment value of target base transceiver station, t represents time parameter when synchronously processing target base transceiver station, a is the intercept parameter obtained according to clock difference parameter, and b is the Slope Parameters obtained according to clock difference parameter.
Further, the step that target base transceiver station carries out clock synchronous process is comprised according to clock synchronous function in above-described embodiment: clock synchronous process is carried out to the initial clock of target base transceiver station, be specially, using the current time value of target base transceiver station as time parameter t, the current time value of clock adjustment value Y to target base transceiver station according to calculating is revised; And/or, periodically clock synchronous process is carried out to the present clock of target base transceiver station, be specially: using the difference between the current time of target base transceiver station and front time of once carrying out clock synchronization operation as time parameter t, the present clock of clock adjustment value Y to target base transceiver station according to calculating is revised.
The invention provides a kind of clock synchronization apparatus for base transceiver station, in one embodiment, this device comprises: for determining the selection module of the target base transceiver station of Reference BTS transceiver station and a process to be synchronized; For the computing module of the clock difference parameter between Calculation Basis base transceiver station and target base transceiver station; For obtaining the processing module of clock synchronous function according to clock difference parameter; And, for carrying out the synchronization module of clock synchronous process to target base transceiver station according to clock synchronous function.
Simultaneously, present invention provides a kind of base station sub-system, in one embodiment, this base station sub-system comprises: comprise base station controller and at least two base transceiver stations, wherein, base station controller comprises memory, one or more processor, and one and multiple module, one or more modules of base station controller to be stored in the memory of base station controller and to be configured to be performed by one or more processors of base station controller, one or more modules of base station controller comprise the instruction for performing following steps: the target base transceiver station determining Reference BTS transceiver station and a process to be synchronized from all base transceiver stations, clock difference parameter between Calculation Basis base transceiver station and target base transceiver station, and obtain clock synchronous function according to clock difference parameter, target base transceiver station comprises memory, one or more processor, and one and multiple module, one or more modules of target base transceiver station to be stored in the memory of target base transceiver station and to be configured to be performed by one or more processors of target base transceiver station, and one or more modules of target base transceiver station comprise the instruction for performing following steps: carry out clock synchronous process according to clock synchronous function to target base transceiver station.
Beneficial effect of the present invention:
Clock synchronizing method provided by the invention and device, base station sub-system, selection reference BTS and one target BTS in multiple BTS, the clock synchronous function of target BTS is obtained according to the clock difference parameter between benchmark BTS and target BTS, and utilize this clock synchronous function to carry out clock synchronous process to target BTS, make target BTS consistent with benchmark BTS clock, successively clock synchronous process is carried out to all BTS removing benchmark BTS in this BSS according to the method, reach the effect of all BTS clocks and benchmark BTS clock Complete Synchronization in BSS, because the present invention only needs to increase corresponding software or program in BSC and/or BTS, and do not need to increase GPS device to each BTS, reduce the cost realizing BTS clock synchronous.
Accompanying drawing explanation
Fig. 1 is the structural representation of base station sub-system;
The schematic diagram of the clock synchronizing method that Fig. 2 provides for one embodiment of the invention;
The schematic diagram of the clock synchronization apparatus that Fig. 3 provides for one embodiment of the invention;
The schematic diagram of the clock synchronizing method that Fig. 4 provides for the present invention one application example.
Embodiment
Clock synchronizing method provided by the present invention can be applied to the synchronous of clock between the BTS in all communications network systems in base station sub-system BSS, and existing being made the present invention by embodiment mode by reference to the accompanying drawings further annotates explanation.
The schematic diagram of the clock synchronizing method that Fig. 2 provides for one embodiment of the invention, as shown in Figure 2, in the present embodiment, the clock synchronizing method for BTS clock synchronous provided by the invention comprises the following steps:
S201: the target base transceiver station determining Reference BTS transceiver station and a process to be synchronized;
Composition graphs 1, this step selects the target BTS of an a benchmark BTS and process to be synchronized from BTS1, BTS2 and BTS3; The mode of selection reference BTS can the less BTS of numbering as benchmark BTS, as using BTS1 as benchmark BTS, so, BTS2 and BTS3 is the BTS of process to be synchronized, and this step selects one from BTS2 and BTS3, as BTS2, as target BTS;
S202: the clock difference parameter between Calculation Basis base transceiver station and target base transceiver station;
Accept step S201, this step calculates the clock difference parameter between BTS1 and BTS2;
Preferably, this clock difference parameter comprises: benchmark BTS to target BTS direction (BTS1 → BTS2) clock difference parameter and/or, target BTS is to the clock difference parameter in benchmark BTS direction (BTS2 → BTS1), because clock is not identical between two BTS, so the clock difference parameter of both direction is also not necessarily identical;
Preferably, this clock difference parameter is the difference of clock between benchmark BTS to target BTS, and for ease of calculating, in application example of the present invention, the unit of this clock difference parameter is taken as " half symbolic number ";
Preferably, in order to ensure the validity of the clock difference parameter calculated, periodically can calculate the clock difference parameter between BTS1 and BTS2, for ease of counting, in application example of the present invention, this cycle is taken as " 100ms ";
S203: obtain clock synchronous function according to clock difference parameter;
Preferably, the clock synchronous function that this step S203 obtains is n rank linear functions, n≤1.
Preferably, this step S203 can comprise: carry out linear regression processing to clock difference parameter and obtain clock synchronous function;
Preferably, this step S203 also comprised before carrying out linear regression processing to clock difference parameter: carry out merging treatment to clock difference parameter, and/or carried out correcting process to clock difference parameter, concrete, when clock difference parameter comprises target base transceiver station to the clock difference parameter in Reference BTS transceiver station direction, step S203 also comprised before carrying out correcting process to clock difference parameter: carry out merging treatment to clock difference parameter, be specially, be the clock difference parameter of Reference BTS transceiver station to target base transceiver station direction (BTS1 → BTS2) by target base transceiver station to the clock difference Parameter Switch in Reference BTS transceiver station direction (BTS2 → BTS1), the object of such conversion is the consistency in order to ensure clock difference parametric direction, and benchmark BTS is the uniqueness of BTS1, when clock difference parameter comprises excessive clock difference parameter value (as being greater than 500 half symbolic numbers), in order to avoid the excessive impact on subsequent calculations of data, step S203 also comprised before carrying out correcting process to clock difference parameter: carry out correcting process to clock difference parameter, being specially excessive clock difference Parameter Switch is a less new clock difference parameter, and the object revised like this is the stability in order to ensure the clock synchronous function calculated.
Due in gsm networks, the free oscillation clock of each BTS is stable, and therefore, the clock difference between target BTS with benchmark BTS becomes first-order linear to change; So, preferably, the clock synchronous function in step S203 is first order linear function: Y=a+b*t; Wherein, Y represents the clock correction value of target base transceiver station, and t represents time parameter when synchronously processing target base transceiver station, and a is the intercept parameter obtained according to clock difference parameter, and b is the Slope Parameters obtained according to clock difference parameter; The step of clock difference parameter being carried out to linear regression processing is specially: carry out linear regression processing the computing time respective with it to clock difference parameter and obtain clock synchronous function.
S204: clock synchronous process is carried out to target base transceiver station according to clock synchronous function;
The clock synchronous process of this step S204 to target BTS comprises: initial clock carries out synchronously, periodic clock synchronous;
For both of these case, when the clock synchronous function in step S203 is first order linear function Y=a+b*t, the step of the initial clock of target BTS being carried out to clock synchronous process specifically comprises, using the current time value of target base transceiver station as time parameter t, the current time value of clock correction value Y to target base transceiver station according to calculating is revised; Carry out clock synchronous process (can be periodic clock synchronous) to the present clock of target BTS specifically to comprise, using the difference between the current time of target base transceiver station and front time of once carrying out clock synchronization operation as time parameter t(when for periodically carrying out clock synchronous, t is this synchronizing cycle), the present clock of clock correction value Y to target base transceiver station according to calculating is revised.
Predictably, for other BTS, as the BTS3 in Fig. 1, step S201 to step S204(can be performed successively and only BTS2 wherein need be replaced with BTS3), also the synchronous of clock between BTS3 with benchmark BTS can be realized, so, the synchronous of clock between BTS1, BTS2 and BTS3 is also just realized on this basis.
The schematic diagram of the clock synchronization apparatus that Fig. 3 provides for one embodiment of the invention; As shown in Figure 3, in this embodiment, clock synchronization apparatus 3 provided by the invention comprises: select module 31, computing module 32, processing module 33 and synchronization module 34, wherein,
Select module 31 for determining the target base transceiver station of Reference BTS transceiver station and a process to be synchronized;
Computing module 32 is for the clock difference parameter between Calculation Basis base transceiver station and target base transceiver station;
Processing module 33 is for obtaining clock synchronous function according to clock difference parameter;
Synchronization module 34 is for carrying out clock synchronous process according to clock synchronous function to target base transceiver station.
Preferably, the clock synchronous function that the processing module 33 in Fig. 3 obtains is n rank linear functions, n≤1.
Preferably, the clock difference parameter that the computing module 32 in Fig. 3 calculates comprises: Reference BTS transceiver station is to the clock difference parameter in target base transceiver station direction and/or target base transceiver station to the clock difference parameter in Reference BTS transceiver station direction; Further, this clock difference parameter is the difference of clock between Reference BTS transceiver station and target base transceiver station.
Preferably, in one embodiment, the processing module 33 in Fig. 3 comprises: for carrying out the first submodule that linear regression processing obtains clock synchronous function to clock difference parameter.
Preferably, in another embodiment, the processing module 33 in above-described embodiment also comprises: for carrying out the second submodule of merging treatment to clock difference parameter, and/or, for carrying out the 3rd submodule of correcting process to clock difference parameter.
Preferably, in one embodiment, the clock synchronous function that the processing module 33 in Fig. 3 obtains is first order linear function: Y=a+b*t; Wherein, Y represents the clock correction value of target base transceiver station, and t represents time parameter when synchronously processing target base transceiver station, and a is the intercept parameter obtained according to clock difference parameter, and b is the Slope Parameters obtained according to clock difference parameter; Concrete, the first submodule in processing module 33 obtains clock synchronous function specifically for carrying out linear regression processing the computing time respective with it to clock difference parameter.
Preferably, in one embodiment, synchronization module 34 in Fig. 3 comprises: for carrying out the first synchronous submodule of clock synchronous process to the initial clock of target base transceiver station, first synchronous submodule specifically for using the current time value of target base transceiver station as time parameter t, the current time value of clock correction value Y to target base transceiver station according to calculating is revised.
Preferably, in one embodiment, synchronization module 34 in Fig. 3 comprises: for periodically carrying out the second synchronous submodule of clock synchronous process to the present clock of target base transceiver station, second synchronous submodule specifically for using the difference between the current time of target base transceiver station and front time of once carrying out clock synchronization operation as time parameter t, the present clock of clock correction value Y to target base transceiver station according to calculating is revised.
Predictably, clock synchronization apparatus 3 shown in Fig. 3 can be an independently device, can also be the part-structure in BSC and/or BTS in BSS, as selected module 31, computing module 32 and processing module 33 to be arranged in BSC, synchronization module 34 be arranged in target BTS.
Existing composition graphs 1 and Fig. 4 illustrate application example of the present invention, and in following application example, setting BSS is a base station sub-system in GSM network; With reference to Fig. 1, base station sub-system BSS provided by the invention comprises: base station controller and at least two base transceiver stations, wherein,
Base station controller comprises memory, one or more processor, and one and multiple module, one or more modules of base station controller to be stored in the memory of base station controller and to be configured to be performed by one or more processors of base station controller, one or more modules of base station controller comprise the instruction for performing following steps: the target base transceiver station determining Reference BTS transceiver station and a process to be synchronized from all base transceiver stations, clock difference parameter between Calculation Basis base transceiver station and target base transceiver station, and obtain clock synchronous function according to clock difference parameter,
Target base transceiver station comprises memory, one or more processor, and one and multiple module, one or more modules of target base transceiver station to be stored in the memory of target base transceiver station and to be configured to be performed by one or more processors of target base transceiver station, and one or more modules of target base transceiver station comprise the instruction for performing following steps: carry out clock synchronous process according to clock synchronous function to target base transceiver station.
Preferably, the clock synchronous function that one or more modules of the base station controller in above-described embodiment obtain is n rank linear functions, n≤1.
Preferably, the clock difference parameter that one or more modules of the base station controller in above-described embodiment calculate comprises: Reference BTS transceiver station is to the clock difference parameter in target base transceiver station direction and/or target base transceiver station to the clock difference parameter in Reference BTS transceiver station direction.
Preferably, one or more modules of the base station controller in above-described embodiment also comprise the instruction for performing following steps: carry out linear regression processing to clock difference parameter and obtain clock synchronous function.
Preferably, one or more modules of the base station controller in above-described embodiment also comprise the instruction for performing following steps: carry out merging treatment to clock difference parameter, and/or, correcting process is carried out to clock difference parameter.
Preferably, one or more modules of the base station controller in above-described embodiment also comprise the instruction for performing following steps: carry out linear regression processing the computing time respective with it to clock difference parameter and obtain clock synchronous function; The clock synchronous function that one or more modules of base station controller calculate is first order linear function: Y=a+b*t, wherein, Y represents the clock adjustment value of target base transceiver station, t represents time parameter when synchronously processing target base transceiver station, a is the intercept parameter obtained according to clock difference parameter, and b is the Slope Parameters obtained according to clock difference parameter.
Preferably, one or more modules of the target base transceiver station in above-described embodiment comprise the instruction for performing following steps: carry out clock synchronous process to the initial clock of target base transceiver station, be specially, using the current time value of target base transceiver station as time parameter t, the current time value of clock adjustment value Y to target base transceiver station according to calculating is revised; And/or, periodically clock synchronous process is carried out to the present clock of target base transceiver station, be specially: using the difference between the current time of target base transceiver station and front time of once carrying out clock synchronization operation as time parameter t, the present clock of clock adjustment value Y to target base transceiver station according to calculating is revised.
The schematic diagram of the clock synchronizing method that Fig. 4 provides for the present invention one application example, as shown in Figure 4, in this application example, clock synchronizing method provided by the invention comprises the following steps:
S401: determine that BTS1 be benchmark BTS, BTS2 is target BTS;
S402: the clock difference parameter between Calculation Basis BTS and target BTS;
For describing the present invention in detail, be set in the clock difference parameter simultaneously calculating BTS1 → BTS2 and BTS2 → BTS1 direction in step S402, the unit of this clock difference parameter is " half symbolic number ", periodically calculate 12 clock difference parameters, and it was sorted according to computing time, ranking results is as shown in table 1 below:
Table 1
| Website direction | Time point (ms) | Clock difference parameter (Y) |
| BTS1→BTS2 | 0 | 6789119996 |
| BTS1→BTS2 | 102 | 6789119998 |
| BTS1→BTS2 | 198 | 6789119997 |
| BTS1→BTS2 | 300 | 6789119999 |
| BTS1→BTS2 | 402 | 0 |
| BTS1→BTS2 | 504 | 1 |
| BTS2→BTS1 | 602 | 1 |
| BTS2→BTS1 | 695 | 6789119999 |
| BTS2→BTS1 | 800 | 6789119998 |
| BTS2→BTS1 | 902 | 6789119997 |
| BTS2→BTS1 | 1004 | 6789119996 |
| BTS2→BTS1 | 1103 | 6789119996 |
As shown in Table 1, the clock difference parameter calculated includes the clock difference parameter of target BTS to benchmark BTS direction, so just needing target BTS to the clock difference Parameter Switch in benchmark BTS direction is the clock difference parameter of benchmark BTS to target BTS direction, namely performs step S403; If do not comprise the clock difference parameter of target BTS to benchmark BTS direction in table 1, so, after step S402, skip step S403, directly perform step S404;
S403: the merging treatment carrying out clock difference parameter;
In gsm networks, the frame number that BTS send/receive the Frame that data use is circulate in the cycle with 2048*26*51, and each Frame comprises 8 subframes, each subframe comprises 156.25 symbolic numbers, also be, in gsm networks, the maximum of the clock difference parameter Y of two BTS is 2048*26*51*156.25*2 half symbolic number; Also namely, at a time Ti, there is following relation in the clock difference parameter between two BTS:
Yi(BTS1→BTS2)+Yi(BTS2→BTS1)=2048*26*51*156.25*2=6789120000；
According to above-mentioned relation, be that after the clock difference parameter in BTS1 → BTS2 direction, table 1 is updated to following table 2 by the clock difference Parameter Switch in BTS2 → BTS1 direction in table 1:
Table 2
| Website direction | Time point (ms) | Clock difference parameter (Y) |
| BTS1→BTS2 | 0 | 6789119996 |
| BTS1→BTS2 | 102 | 6789119998 |
| BTS1→BTS2 | 198 | 6789119997 |
| BTS1→BTS2 | 300 | 6789119999 |
| BTS1→BTS2 | 402 | 0 |
| BTS1→BTS2 | 504 | 1 |
| BTS1→BTS2 | 602 | 6789119999 |
| BTS1→BTS2 | 695 | 1 |
| BTS1→BTS2 | 800 | 2 |
| BTS1→BTS2 | 902 | 3 |
| BTS1→BTS2 | 1004 | 4 |
| BTS1→BTS2 | 1103 | 4 |
S404: the correcting process of carrying out clock difference parameter;
When measurement data is near clock difference parameter maximum (26 × 51 × 2048 × 8 × 156.25 × 2), the scope of clock difference parameter excessive (as table 2, excursion is 0--6789119999) can be caused so that affect the Slope Parameters of subsequent clock synchronous function and the calculating of intercept parameter; As shown in table 2, can be seen by table 2, the excursion of its clock difference parameter is excessive, needs to carry out correcting process to eliminate the calculation deviation produced because of computing cycle to some of clock difference parameter; Computational algorithm is as follows:
ifY
max-Y
min<Δ
Y
i=Y
i
else
for(i=1;i≤n;i++)
ifY
i-Y
min<Δ
Y
i=Y
i
else
Y
i=Y
i-2048×26×51×8×156.25×2
end
end
end
Above-mentioned algorithm relates to Ymax and Ymin, in all n calculated clock difference parameters shown in table 2, and Ymax=6789119999, Ymin=0; In this application example, n=12;
Wherein Δ can be set to some half symbolic numbers, its implication is the excursion allowed in initial clock difference calculation of parameter time window internal clock difference parameter, 2048 × 26 × 51 × 8 × 156.25 × 2 represent half symbolic number that a Hyperframe comprises, in reality, we get Δ=500, and the difference thinking between clock difference parameter is greater than 500 and causes owing to exceeding Hyperframe half symbolic number maximum;
Carry out correction according to above-mentioned algorithm his-and-hers watches 2 and obtain following table 3:
Table 3
| Website direction | Time point (ms) | Clock difference parameter (Y) |
| BTS1→BTS2 | 0 | -4 |
| BTS1→BTS2 | 102 | -2 |
| BTS1→BTS2 | 198 | -3 |
| BTS1→BTS2 | 300 | -1 |
| BTS1→BTS2 | 402 | 0 |
| BTS1→BTS2 | 504 | 1 |
| BTS1→BTS2 | 602 | -1 |
| BTS1→BTS2 | 695 | 1 |
| BTS1→BTS2 | 800 | 2 |
| BTS1→BTS2 | 902 | 3 |
| BTS1→BTS2 | 1004 | 4 |
| BTS1→BTS2 | 1103 | 4 |
Predictably, if when the difference between clock difference parameters all in table 2 is all not more than 500, so, after step S403, skip step S404, directly perform step S405;
S405: linear regression processing is carried out to result and obtains clock synchronous function;
Due in gsm networks, clock synchronous function is first order linear function: Y=a+b × t; Only need to calculate intercept parameter a, Slope Parameters b, the present invention is also exemplary gives a kind of algorithm, and this algorithm is as follows:
Wherein, Y
irepresent i-th clock difference parameter, t
irepresent some computing time of i-th clock difference parameter,
represent the mean value of all clock difference parameters,
representative calculates the mean value of clock difference parameter temporal point; The data that property provides exemplified by above-mentioned algorithm and table 3, calculate:
a=-3.515715267；b=0.006985569
Y=0.006985569×t-3.515715267
S406: clock synchronous process is carried out to target BTS according to clock synchronous function;
This step can be performed by BSC, and also can be performed by target BTS self, when being performed by target BTS self, the parameter a in above-mentioned function, b are transferred to target BTS by BSC;
This step comprises: initial clock carries out synchronously, periodic clock synchronous; Wherein,
Initial clock carry out Synchronization Example as: according to current point in time and clock synchronous function, calculate the clock correction value of current point in time, as at t
1=1200ms time point carries out synchronously, and calculating clock correction value is 4.866967533, and round number adjusts 5 half symbolic numbers;
Periodic clock synchronous exemplary as: due to the existence of each BTS crystal oscillator difference and measure error, along with the accumulation of time, between BTS, clock produces deviation gradually, need to carry out the calculating of periodic clock deviation and adjustment, when the clock adjustment cycle T preset arrives, BTS calculates clock correction value according to adjustment cycle T and clock synchronous function; Because periodically adjustment is carried out, as above at t after initial clock synchronously
1moment carried out adjustment, so at t
2moment (t
2-t
1=T=1200ms) when adjusting, if directly calculate according to clock synchronous function, the clock correction value obtained is 13, therefore at t
1moment carried out adjustment, at t
2the moment clock correction value of actual needs adjustment is 8 (13-5=8) individual half symbolic number, at t
3moment (t
3-t
2=T=1200ms) when adjusting, if directly calculate according to clock synchronous function, the clock correction value obtained is 21, therefore at t
2moment carried out adjustment, at t
3the moment clock correction value of actual needs adjustment is 8 (21-13=8) individual half symbolic number; It can thus be appreciated that, after adjustment cycle is determined, the clock correction value in its each cycle is also determined, therefore, in other embodiments, also can directly calculate clock correction value according to cycle T, because overcome a clock difference the synchronous of initial time, also namely have modified the intercept parameter in clock synchronous function, the computing formula of the clock correction value in each cycle is: Y=b × T.
In summary, by enforcement of the present invention, at least there is following beneficial effect:
First, selection reference BTS and one target BTS in multiple BTS, the clock synchronous function of target BTS is obtained according to the clock difference parameter between benchmark BTS and target BTS, and utilize this clock synchronous function to carry out clock synchronous process to target BTS, make target BTS consistent with benchmark BTS clock, successively clock synchronous process is carried out to all BTS removing benchmark BTS in this BSS according to the method, reach the effect of all BTS clocks and benchmark BTS clock Complete Synchronization in BSS, because the present invention only needs to increase corresponding software or program in BSC and/or BTS, and do not need to increase GPS device to each BTS, reduce the cost realizing BTS clock synchronous,
Secondly, by carrying out merging treatment to the clock difference parameter calculating band, ensure that the uniqueness of benchmark BTS;
Again, by carrying out correcting process to the clock difference parameter calculating band, ensure that the accuracy of the clock synchronous function obtained by clock difference parameter;
Finally, by periodically carrying out clock synchronous, ensure that the consistency of clock between each BTS in BSS.
Below be only the specific embodiment of the present invention; not any pro forma restriction is done to the present invention; every above execution mode is done according to technical spirit of the present invention any simple modification, equivalent variations or modification, all still belong to the protection range of technical solution of the present invention.
Claims (21)
1. for a clock synchronizing method for base transceiver station, it is characterized in that, comprising:
Determine the target base transceiver station of Reference BTS transceiver station and a process to be synchronized;
Calculate the clock difference parameter between described Reference BTS transceiver station and described target base transceiver station;
Clock synchronous function is obtained according to described clock difference parameter;
According to described clock synchronous function, clock synchronous process is carried out to described target base transceiver station.
2. clock synchronizing method as claimed in claim 1, it is characterized in that, described clock synchronous function is n rank linear functions, n≤1.
3. clock synchronizing method as claimed in claim 2, it is characterized in that, described clock difference parameter comprises: described Reference BTS transceiver station is to the clock difference parameter in described target base transceiver station direction and/or described target base transceiver station to the clock difference parameter in described Reference BTS transceiver station direction.
4. clock synchronizing method as claimed in claim 2, it is characterized in that, the described step obtaining clock synchronous function according to described clock difference parameter comprises: carry out linear regression processing to described clock difference parameter and obtain described clock synchronous function.
5. clock synchronizing method as claimed in claim 4, is characterized in that, also comprise: carry out merging treatment to described clock difference parameter, and/or carried out correcting process to described clock difference parameter before carrying out linear regression processing to described clock difference parameter.
6. the clock synchronizing method as described in claim 4 or 5, it is characterized in that, the step that described clock difference parameter carries out linear regression processing is specially: carry out linear regression processing the computing time respective with it to described clock difference parameter and obtain described clock synchronous function; Described clock synchronous function is first order linear function: Y=a+b*t, wherein, Y represents the clock adjustment value of described target base transceiver station, t represents time parameter when synchronously processing described target base transceiver station, a is the intercept parameter obtained according to described clock difference parameter, and b is the Slope Parameters obtained according to described clock difference parameter.
7. clock synchronizing method as claimed in claim 6, it is characterized in that, describedly according to described clock synchronous function, the step that described target base transceiver station carries out clock synchronous process to be comprised: clock synchronous process is carried out to the initial clock of described target base transceiver station, be specially, using the current time value of described target base transceiver station as described time parameter t, calculate the current time value of clock adjustment value Y to described target base transceiver station according to Y=a+b*t and revise; And/or, periodically clock synchronous process is carried out to the present clock of described target base transceiver station, be specially: using the difference between the current time of described target base transceiver station and front time of once carrying out clock synchronization operation as described time parameter t, calculate the present clock of clock adjustment value Y to described target base transceiver station according to Y=b*t and revise.
8. for a clock synchronization apparatus for base transceiver station, it is characterized in that, comprising:
For determining the selection module of the target base transceiver station of Reference BTS transceiver station and a process to be synchronized;
For calculating the computing module of the clock difference parameter between described Reference BTS transceiver station and described target base transceiver station;
For obtaining the processing module of clock synchronous function according to described clock difference parameter; And,
For carrying out the synchronization module of clock synchronous process to described target base transceiver station according to described clock synchronous function.
9. clock synchronization apparatus as claimed in claim 8, it is characterized in that, the clock synchronous function that described processing module obtains is n rank linear functions, n≤1.
10. clock synchronization apparatus as claimed in claim 9, it is characterized in that, the clock difference parameter that described computing module calculates comprises: described Reference BTS transceiver station is to the clock difference parameter in described target base transceiver station direction and/or described target base transceiver station to the clock difference parameter in described Reference BTS transceiver station direction.
11. clock synchronization apparatus as claimed in claim 9, it is characterized in that, described processing module comprises: for carrying out to described clock difference parameter the first submodule that linear regression processing obtains described clock synchronous function.
12. clock synchronization apparatus as claimed in claim 11, it is characterized in that, described processing module also comprises: for carrying out the second submodule of merging treatment to described clock difference parameter, and/or, for carrying out the 3rd submodule of correcting process to described clock difference parameter.
13. clock synchronization apparatus as described in claim 11 or 12, it is characterized in that, described first submodule obtains described clock synchronous function specifically for carrying out linear regression processing the computing time respective with it to described clock difference parameter; The clock synchronous function that described processing module obtains is first order linear function: Y=a+b*t; Wherein, Y represents the clock adjustment value of described target base transceiver station, t represents time parameter when synchronously processing described target base transceiver station, and a is the intercept parameter obtained according to described clock difference parameter, and b is the Slope Parameters obtained according to described clock difference parameter.
14. clock synchronization apparatus as claimed in claim 13, it is characterized in that, described synchronization module comprises: for carrying out the first synchronous submodule of clock synchronous process to the initial clock of described target base transceiver station, described first synchronous submodule specifically for using the current time value of described target base transceiver station as described time parameter t, calculate the current time value of clock adjustment value Y to described target base transceiver station according to Y=a+b*t and revise; And/or, periodically the present clock of described target base transceiver station is carried out to the second synchronous submodule of clock synchronous process, described second synchronous submodule specifically for using the difference between the current time of described target base transceiver station and front time of once carrying out clock synchronization operation as described time parameter t, calculate the present clock of clock adjustment value Y to described target base transceiver station according to Y=b*t and revise.
15. 1 kinds of base station sub-systems, comprise base station controller and at least two base transceiver stations, it is characterized in that,
Described base station controller comprises memory, one or more processor, and one and multiple module, one or more modules of described base station controller to be stored in the memory of described base station controller and to be configured to be performed by one or more processors of described base station controller, one or more modules of described base station controller comprise the instruction for performing following steps: the target base transceiver station determining Reference BTS transceiver station and a process to be synchronized from all base transceiver stations, calculate the clock difference parameter between described Reference BTS transceiver station and described target base transceiver station, and obtain clock synchronous function according to described clock difference parameter,
Described target base transceiver station comprises memory, one or more processor, and one and multiple module, one or more modules of described target base transceiver station to be stored in the memory of described target base transceiver station and to be configured to be performed by one or more processors of described target base transceiver station, and one or more modules of described target base transceiver station comprise the instruction for performing following steps: carry out clock synchronous process according to described clock synchronous function to described target base transceiver station.
16. base station sub-systems as claimed in claim 15, is characterized in that, the clock synchronous function that one or more modules of described base station controller obtain is n rank linear functions, n≤1.
17. base station sub-systems as claimed in claim 16, it is characterized in that, the clock difference parameter that one or more modules of described base station controller calculate comprises: described Reference BTS transceiver station is to the clock difference parameter in described target base transceiver station direction and/or described target base transceiver station to the clock difference parameter in described Reference BTS transceiver station direction.
18. base station sub-systems as claimed in claim 16, is characterized in that, one or more modules of described base station controller also comprise the instruction for performing following steps: carry out linear regression processing to described clock difference parameter and obtain described clock synchronous function.
19. base station sub-systems as claimed in claim 18, it is characterized in that, one or more modules of described base station controller also comprise the instruction for performing following steps: carry out merging treatment to described clock difference parameter, and/or, correcting process is carried out to described clock difference parameter.
20. base station sub-systems as described in claim 18 or 19, it is characterized in that, one or more modules of described base station controller also comprise the instruction for performing following steps: carry out linear regression processing the computing time respective with it to described clock difference parameter and obtain described clock synchronous function; The clock synchronous function that one or more modules of described base station controller calculate is first order linear function: Y=a+b*t, wherein, Y represents the clock adjustment value of described target base transceiver station, t represents time parameter when synchronously processing described target base transceiver station, a is the intercept parameter obtained according to described clock difference parameter, and b is the Slope Parameters obtained according to described clock difference parameter.
21. base station sub-systems as claimed in claim 20, it is characterized in that, one or more modules of described target base transceiver station comprise the instruction for performing following steps: carry out clock synchronous process to the initial clock of described target base transceiver station, be specially, using the current time value of described target base transceiver station as described time parameter t, calculate the current time value of clock adjustment value Y to described target base transceiver station according to Y=a+b*t and revise; And/or, periodically clock synchronous process is carried out to the present clock of described target base transceiver station, be specially: using the difference between the current time of described target base transceiver station and front time of once carrying out clock synchronization operation as described time parameter t, revise according to the present clock of clock adjustment value Y to described target base transceiver station that Y=b*t calculates.
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| CN201310351739.2A CN104378818A (en) | 2013-08-13 | 2013-08-13 | Clock synchronization method and device and base station subsystem |
| PCT/CN2014/084204 WO2015021911A1 (en) | 2013-08-13 | 2014-08-12 | Clock synchronization method and device, and base station system |
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