CN104346307A - System and Method for Direct Memory Access Transfers - Google Patents
System and Method for Direct Memory Access Transfers Download PDFInfo
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- CN104346307A CN104346307A CN201410456571.6A CN201410456571A CN104346307A CN 104346307 A CN104346307 A CN 104346307A CN 201410456571 A CN201410456571 A CN 201410456571A CN 104346307 A CN104346307 A CN 104346307A
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/14—Handling requests for interconnection or transfer
- G06F13/20—Handling requests for interconnection or transfer for access to input/output bus
- G06F13/28—Handling requests for interconnection or transfer for access to input/output bus using burst mode transfer, e.g. direct memory access DMA, cycle steal
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/317—Testing of digital circuits
- G01R31/3181—Functional testing
- G01R31/319—Tester hardware, i.e. output processing circuits
- G01R31/3193—Tester hardware, i.e. output processing circuits with comparison between actual response and known fault free response
- G01R31/31937—Timing aspects, e.g. measuring propagation delay
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/14—Handling requests for interconnection or transfer
- G06F13/16—Handling requests for interconnection or transfer for access to memory bus
- G06F13/18—Handling requests for interconnection or transfer for access to memory bus based on priority control
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/14—Handling requests for interconnection or transfer
- G06F13/20—Handling requests for interconnection or transfer for access to input/output bus
- G06F13/28—Handling requests for interconnection or transfer for access to input/output bus using burst mode transfer, e.g. direct memory access DMA, cycle steal
- G06F13/287—Multiplexed DMA
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
- G06F13/4265—Bus transfer protocol, e.g. handshake; Synchronisation on a point to point bus
- G06F13/4269—Bus transfer protocol, e.g. handshake; Synchronisation on a point to point bus using a handshaking protocol, e.g. Centronics connection
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- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Bus Control (AREA)
Abstract
A system and method for transferring data between a memory and peripheral units via a plurality of direct memory access (DMA) transactions, wherein a respective timestamp is assigned and/or appended to at least two of the plurality of the DMA transactions.
Description
Technical field
The specific embodiment of present disclosure relates to a kind of system and method for direct memory access transmission.More specifically, the specific embodiment of present disclosure relates to a kind of system and method for transmitting data between storer and peripheral cell via multiple direct memory access issued transaction.
Background technology
Direct memory access (DMA) is the feature of modern computer, and the specific hardware subsystem access system memory in its permission computing machine is to carry out reading and/or writing independent of CPU (central processing unit) (CPU).Many hardware systems use the DMA comprising disk drive controller, video card, network interface card and sound card.Compared to the computing machine without DMA passage, the computing machine providing DMA passage usually can transfer data to device and transmit data from device when considerably less CPU overhead.
DMA is commonly used to allow device transmission data, and does not make CPU be exposed to heavy load.If each data block must be copied to destination from source by CPU, then this usually will be slower than copying normal memory block, because generally slow than normal system RAM to the access of I/O device by peripheral bus.During this period, CPU for relate to cpu bus access other task will be unavailable, although it can proceed any work not requiring bus access.
Memory block is copied to another device from a device by DMA transmission in essence.Although CPU initiates transmission, it does not perform transmission.Transmission is performed by the dma controller of the part usually used as board chip set usually.The typical usage of DMA is the buffer zone copied to from system RAM by memory block device, or copy memory block from the buffer zone device, wherein, this operation does not need too many processor capacity, and result is that described processor can be arranged to perform other task.Therefore, DMA is absolutely necessary to high performance embedded system.
Data are generally transferred to data destination locations from data source location by dma controller.In some applications, DMA transmission is used in Safety-Critical System, and wherein, importantly, DMA transmission performs correct transmission operation.Due to the supervision that the autonomous characteristic requirements of process is a large amount of, dma operation may be difficult to check especially.
Particularly, when DMA is used for automatic from autonomous peripheral cell (such as serial line interface, analog to digital converter (ADC) in a periodic manner, or input capture system) when unloading data, it is often configured to data to move to one or more storage buffer from peripheral cell.Appear at data in storage buffer usually by the real-time control of control system for system actuators and communication interface.Therefore, these data have temporal characteristics, because system should only use the current data be just transmitted, instead of historical data.Importantly, know that data buffer is refreshed since upper secondary data is used.Therefore, CPU must transmit operation, the low latency service that this requires CPU intensive by real-time inspection DMA.
Usually, in the embedded system also comprising a host CPU, known DMA peripherals performs data transactions.CPU is responsible for the proper operation supervising DMA.The DMA transaction sequence of link is correctly sorted by configuration DMA and interruption router, the beginning of the DMA issued transaction that triggering is new after the described interruption router issued transaction be used in the sequence completes.The DMA transaction sequence of link is sorted by any one method in following method usually:
Configuration dma controller and interrupt router, has made a lasting DMA issued transaction initiate the beginning of next DMA issued transaction via hardware trigger.
CPU gets involved between DMA issued transaction, and triggers the beginning initiating next DMA issued transaction via software when receiving DMA issued transaction completed DMA traffic management marker above.
US2009/0271536 discloses a kind of dma controller performing I/O descriptor conditionally, and wherein, the list items of link is included in the School Affairs that descriptor field calculates.When take out link list items time, on descriptor calculation check and.If two School Affairs are equal, then the list items of this link is considered to effective, and performs this descriptor.In the ending of DMA I/O, take out the next descriptor in the list items of link.When School Affairs failure, then destroy descriptor, stop passage, and to operating system reporting errors.
These known methods comprise following shortcoming:
When DMA transaction sequence is underway, the checking of DMA data mobile seasonal effect in time series requires the intervention of CPU, to confirm the sequence of event.
The aftertreatment of dma state does not ensure correct operation.
The aftertreatment of the destination data be moved is that CPU is intensive.
Present disclosure is in the face of being used for providing for the problems referred to above the challenge of solution.
Summary of the invention
According to an embodiment, present disclosure provides a kind of system and method, and it for transmitting data via direct memory access (DMA) issued transaction, operation or event between storer and peripheral cell.This system and method comprises the distribution or additional to the respective timestamp of DMA issued transaction, makes it possible to the relative timing of more different DMA issued transaction.This mechanism and that distribute or additional timestamp can be used to support to follow the tracks of different DMA events or issued transaction.
According to another embodiment, present disclosure provides a kind of system and device, and it distributes or an additional corresponding timestamp to destination data for the ending in DMA affairs.Distribute or be added to DMA affairs, the timestamp of destination data of operation or event provides the mode completed for more respective DMA affairs relative time.
According to another embodiment again, present disclosure provides a kind of for the system of host CPU report DMA timestamp and mechanism.This report to the DMA timestamp of host CPU allows CPU to check the inter-process of DMA event or issued transaction.Thus, the correct sequence of DMA affairs can be confirmed.This CPU also can detect the incorrect rate of dma operation, the such as stand-by period, arrival rate, loses and/or repetitive sequence.
According to an embodiment of present disclosure, respective timestamp is affixed to final purpose data, and these data are written into during the last DMA write of DMA issued transaction is mobile.
According to another embodiment of present disclosure, timestamp is generated by the binary sequence increased progressively (binary counter of such as free-running operation), and can support to compare and arithmetical operation.
According to another embodiment of present disclosure, when last DMA of sequence is transmitted, an additional transmission can be automatically performed to catch the currency of the timer counter of free-running operation, and currency is moved to the next address in destination memory structure.
According to another embodiment of present disclosure, timestamp can carry out aftertreatment, to check the time series of DMA issued transaction.This aftertreatment of timestamp can make it possible to the time check carrying out DMA transaction sequence.
According to another embodiment of present disclosure, the destination address of timestamp can calculate from DMA issued transaction control group.This timestamp can be asked the sequence determining a series of DMA affairs.
According to another embodiment of present disclosure, the destination address of timestamp can calculate from DMA transaction controller or control group.This timestamp can be asked the sequence determining a series of DMA issued transaction in this application.
According to another embodiment, present disclosure can be used in the Motor control Application of vehicle.If ADC is used for such as sampling to effective current of electric via divertor or hall effect sensor, then electric current associates with instantaneous motor torque phase.Because motor torque is a crucial due care, so timestamp illustrates that ADC is successfully triggered at correct time place and changes.
According to another embodiment of present disclosure, timestamp is assigned to the data will transmitted between storer and one or more peripheral cell, wherein, these data with distribute together with/the timestamp that is added to each DMA issued transaction, operation or event, control to transmit between this storer and one or more peripheral cell by direct memory access (DMA).
In this application, ADC needs to be triggered in time at the some place synchronous with pulse-length modulation (PWM) phasing of motor, because if motor is sampled at the time place of mistake, then and control loop potentially unstable, and the torque reported may be incorrect.Therefore, ADC is triggered by timer, motor phasing too, but if relatively or timer disturbed, or be not in correct speed place, then may causing trouble.
Present disclosure provides a kind of dma controller realizing timestamp function.Present disclosure provides a kind of making it possible to carry out the New function for following unique method:
Prove that the operation of DMA is triggered by correct event.
Prove that destination data is refreshed by new data block.
Therefore, the current realization of present disclosure to this area provides favourable contribution, and wherein, except the interrupt service routine that non-usage is real, the truthlikeness of ADC is also difficult to determine so far.In known application, CPU only can unload ADC, also can read independently timer, to verify that trigger event appears at correct time place.Under normal circumstances, motor phasing is 50 μ s speed, this creates a large amount of interruptions and loads, and especially when each motor commutation cycle request 2 or 3 ADC are measured, and application can have the multiple motors controlled by a core.
From following description and accompanying drawing, these and other advantage of present disclosure, aspect and the feature of novelty and the details of its illustrated embodiment will be understood more all sidedly.
Accompanying drawing explanation
The involved further understanding provided present disclosure of accompanying drawing, and to be merged in this instructions and to form the part of this instructions.Accompanying drawing illustrates the embodiment of present disclosure, and is used for together with the description explaining the principle of present disclosure.The advantage of other embodiment of present disclosure and many intentions of present disclosure will easily be understood, because by reference to the following detailed description, they become better understood.Element in accompanying drawing may not relative to each other be drawn in proportion.The identical part that identical reference number instruction is corresponding.
Fig. 1 be a diagram that the schematic diagram generated according to the timestamp of the embodiment of present disclosure; And
Fig. 2 be a diagram that to have according to the embodiment of present disclosure the schematic diagram transmitted the DMA of the timestamp annex of 32 bit source data.
Fig. 3 be a diagram that to have according to another embodiment of present disclosure the schematic diagram transmitted the DMA of the timestamp annex of 16 bit source data.
Fig. 4 be a diagram that to have according to another embodiment of present disclosure the schematic diagram transmitted the DMA of the timestamp annex of the destination address successively decreased.
Embodiment
In the following detailed description, with reference to the accompanying drawing forming its part, and the specific embodiment wherein can putting into practice present disclosure is shown in the drawing by the mode of illustration.Will be appreciated that under the spirit and scope not departing from present disclosure, other embodiment can be utilized and structure or logical changes can be made.Therefore, the following detailed description, should not be taken as limited significance, and the scope of present disclosure is defined by the appended claims.
Present disclosure relates to employing direct memory access and controls (DMA), between storer and peripheral cell (such as such as serial line interface, switch or router etc.), transmit data.
Fig. 1 show diagram according to present disclosure the schematic diagram of embodiment.In this embodiment of present disclosure, the generation of timestamp can perform as follows:
System clock divided by 8 with generate be used for 32 upwards synchronous counter carry out the slower timestamp fundamental clock of timing.Automatically start after this counter resets, and 32 binary temporal stamps increase progressively on each rising edge of timestamp fundamental clock.While system clock runs with the uniqueness ensured each timestamp value, these 32 binary temporal stamps constantly increase progressively.
Timestamp can only change by requiring to reset, and it makes timestamp get back to its initial value.When discharging reset, timestamp recovers upwards counting sequence.When timestamp overflows predetermined threshold value, timestamp switches back initial value, and recovers upwards counting sequence.Timestamp value reads by such as suitable software.
With reference to figure 1, the system clock frequency f provided
sYSfor 100MHz, subsequently, the timestamp input clock of 12.5MHz can be generated by 8 frequency divider frequency divisions.Therefore 32 binary temporal stamp counter every 80ns increase progressively second.In one embodiment, timestamp is with the increasing rate consistent with DMA transaction rate.If timestamp is with the increasing rate faster than DMA transaction rate, then it may overflow too continually, and it consumes too much power.If timestamp is with the increasing rate lower than DMA transaction rate, DMA issued transaction may not be provided with unique timestamp.
Fig. 2 shows diagram according to the DMA event of the embodiment of present disclosure or the schematic diagram of transmission.In Fig. 2, show source memory and destination memory, it has the source address 1C increased progressively respectively
h, 18
h, 14
h, 10
h, 0
h, 08C
h, 04C
h, 0OC
h.In the example shown in the series of figures, during DMA transmission, operation or issued transaction, transmitted via DMA by the illustrated operation of bit number 0-15 and 16-31 or issued transaction two 16 half-words, operation or issued transaction be from having the source address 1C increased progressively
h, 18
h, 14
h, 10
h, 0
h, 08C
h, 04C
h, 0OC
hsource memory to having the destination address 1C increased progressively
h, 18
h, 14
h, 10
h, 0
h, 08C
h, 04C
h, 0OC
hdestination memory transmit.In this DMA transmits, in the ending of DMA issued transaction destination data, respective timestamp is attached to the destination address place of Next 32 higher alignment immediately.In the example shown in the series of figures, timestamp is stored in destination address O8
hplace.
Fig. 2 be a diagram that to have according to the embodiment of present disclosure the schematic diagram transmitted the DMA of the timestamp annex of 32 bit source data, referring to Fig. 2, describes timestamp annex by example.
DMA passage is configured to perform and moves by four DMA the DMA issued transaction formed.Each DMA moves and 16 bit data samplings is transferred to destination address from source address.Two 32 words are repacked at continuous print destination address place in four 16 bit data samplings at source address place.The transmission of four data samplings undertaken by dma controller is tasks of repetition.DMA issued transaction control group is configured to cyclic buffer.As hi the example shown, DMA passage is configured to add respective timestamp in the ending of DMA issued transaction.The timestamp that the timestamp added in the ending of current DMA issued transaction and the ending in next DMA issued transaction add is different.DMA moves four data samplings, as shown in following exemplary table:
| Data sampling | Source | Destination |
| Data sampling Dn0 | SADR+00 H | DADR+00 H |
| Data sampling Dn1 | SADR+08 H | DADR+02 H |
| Data sampling Dn2 | SADR+10 H | DADR+04 H |
| Data sampling Dn3 | SADR+18 H | DADR+08 H |
The each repetition of DMA issued transaction causes four DMA to move the data sampling rewriteeing and be stored in destination address place.Each DMA moves the data sampling being overwritten in source address place.
Assuming that four data samplings are analyzed by CPU, during each analysis, timestamp can be copied to another address by CPU.When CPU performs next analysis, it can compare timestamp to check any discrepant value.If timestamp does not have difference, then CPU checks whether new data sampling is loaded.If timestamp is different, then CPU checks that current time stabs the timestamp before whether being greater than.Usually, the timestamp before current timestamp is greater than, unless binary temporal stamp counter overflows.Consequently, analyzing the timestamp generated according to present disclosure allows user to determine whether to occur DMA issued transaction.
Fig. 3 is that diagram has according to another embodiment of present disclosure the schematic diagram transmitted the DMA of the timestamp annex of 16 bit source data.In this embodiment, in the ending of DMA issued transaction destination data, timestamp is attached to the destination address place of Next 32 higher alignment immediately.
DMA issued transaction is by the destination address place of four 32 samples storages 32 alignment, and timestamp is written in the destination address place of 32 next higher alignment.
Fig. 4 is that diagram has according to another embodiment again of present disclosure the schematic diagram transmitted the DMA of the timestamp annex of the destination address successively decreased.As shown in Figure 4, in this embodiment, timestamp is at destination address DADR+0C
hplace is affixed to the address of Next 32 lower alignment immediately.In this example of present disclosure, successively decrease in source and destination address and DMA moves four data samplings, as shown in following exemplary table:
| Data sampling | Source | Destination |
| Data sampling Dn0 | SADR+1C H | DADR+1C H |
| Data sampling Dn1 | SADR+14 H | DADR+18 H |
| Data sampling Dn2 | SADR+0C H | DADR+14 H |
| Data sampling Dn3 | SADR+04 H | DADR+10 H |
The timestamp function that present disclosure provides makes it possible to carry out for proving that dma operation to be triggered by correct event and to prove destination data by new ability that new data block refreshes.
According to present disclosure, to a kind of method that the timestamp annex of the destination data of DMA issued transaction, operation or event can also provide the DMA of tracking issued transaction to complete.At this, carry out proving time stamp by comparing two timestamp value.In addition, can calculate two DMA issued transaction complete between time cycle.Therefore, the repetition of transmission, loss, incorrect arrival rate and/or stand-by period can be determined.Relatively the completing of DMA transmission of sequence can testbus pirority inversion and other data transmission timing problems.
Although describe present disclosure with reference to specific embodiment, it will be appreciated by those skilled in the art that and can to make a variety of changes without departing from the spirit and scope in the present disclosure and equivalents can be replaced.In addition, when not departing from its scope, for the instruction of present disclosure, many amendments can be made to adapt to special situation or material.Therefore, it is intended that present disclosure is not limited to disclosed special embodiment, but present disclosure will comprise all embodiments fallen in the scope of claims.
Claims (15)
1., for transmitting a method for data between storer and peripheral cell via multiple direct memory access (DMA) issued transaction, described method comprises:
Perform multiple DMA issued transaction; And
Distribute or additional respective timestamp at least two DMA issued transaction in described multiple DMA issued transaction.
2. method according to claim 1, comprises further:
The described timestamp being attached to described DMA issued transaction is used to carry out the relative timing of more different DMA issued transaction.
3. method according to claim 1, comprises further:
Use the tracking that the described timestamp being attached to described DMA issued transaction is supported described DMA issued transaction.
4. method according to claim 1, comprises further:
Timestamp is attached to the destination data of DMA issued transaction.
5. method according to claim 4, comprises further:
Use the described timestamp being attached to the described destination data of different DMA issued transaction, complete with the relative time of more respective DMA issued transaction.
6. method according to claim 4, wherein said timestamp is affixed to final destination data, and described final destination data is written into during the last DMA write operation of described DMA issued transaction.
7. method according to claim 4, comprises further:
Process is attached to the described timestamp of described DMA issued transaction, to prove whether described destination data is refreshed by new data block.
8. method according to claim 1, comprises further:
The described timestamp being attached to described DMA issued transaction is reported to host Central Processing Unit (CPU) (CPU).
9. method according to claim 1, comprises further:
Described timestamp is generated, to support to compare and arithmetical operation from the timer counter of the binary sequence increased progressively or free-running operation.
10. method according to claim 1, comprises further:
When the last DMA of DMA transfer sequence is transmitted, perform additional transmission to latch the currency of timer counter and described currency is moved to the next address in destination memory structure.
11. methods according to claim 1, comprise further:
Process is attached to the described timestamp of described DMA issued transaction, to check the time series of DMA issued transaction.
12. 1 kinds, for the system using multiple direct memory access (DMA) issued transaction to transmit data, comprising:
Allocation component, it is configured to distribute and/or additional respective timestamp to described data waiting for transmission; And
Transmission assembly, it is configured to control described data to transmit together with the timestamp distributed and/or be attached to each DMA issued transaction by DMA.
13. systems according to claim 12, comprise further:
Host Central Processing Unit (CPU) (CPU), it is configured to use the described timestamp being attached to described DMA issued transaction to check the inter-process of described DMA issued transaction, and be configured to further use the described timestamp of described DMA issued transaction to check the correct sequence of DMA issued transaction, and/or be also configured to use the described timestamp of described DMA issued transaction to detect the incorrect rate of described DMA issued transaction, stand-by period, arrival rate, loss and/or repetitive sequence further.
14. systems according to claim 12, comprise further:
Analog to digital converter (ADC), it is configured to sample via described multiple direct memory access DMA issued transaction and send one or more operating parameter, wherein,
Described CPU is configured to use the described timestamp being attached to described DMA issued transaction to check whether described ADC is triggered at predetermined time point place and/or changes.
15. 1 kinds of direct memory access (DMA) controllers, comprising:
Hop, it is configured to via multiple direct memory access DMA issued transaction transmission data; And
Allocation component, it is configured to distribute or additional respective timestamp at least two DMA issued transaction in described multiple DMA issued transaction.
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US13/951518 | 2013-07-26 | ||
| US13/951,518 US9727502B2 (en) | 2013-07-26 | 2013-07-26 | System and method for direct memory access transfers |
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| CN104346307B CN104346307B (en) | 2017-08-18 |
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| US (1) | US9727502B2 (en) |
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| DE (1) | DE102014011021B4 (en) |
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| CN109840224A (en) * | 2017-11-29 | 2019-06-04 | 爱思开海力士有限公司 | Storage system and its operating method |
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| DE202017104362U1 (en) * | 2017-07-21 | 2017-08-07 | Robert Bosch Gmbh | Timestamp unit and communication control unit for a subscriber station of a communication network |
| US11277269B2 (en) * | 2017-12-13 | 2022-03-15 | Arista Networks, Inc. | System and methods for generating and authenticating verifiable network traffic |
| CN109933413A (en) * | 2017-12-15 | 2019-06-25 | 北京嘀嘀无限科技发展有限公司 | Service implementation method and device, electronic equipment, storage medium |
| US11099966B2 (en) * | 2020-01-09 | 2021-08-24 | International Business Machines Corporation | Efficient generation of instrumentation data for direct memory access operations |
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Also Published As
| Publication number | Publication date |
|---|---|
| DE102014011021A1 (en) | 2015-02-26 |
| CN104346307B (en) | 2017-08-18 |
| DE102014011021B4 (en) | 2022-08-25 |
| US20150032914A1 (en) | 2015-01-29 |
| US9727502B2 (en) | 2017-08-08 |
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