CN104332405B - Germanium nano wire field effect transistor and preparation method thereof - Google Patents
Germanium nano wire field effect transistor and preparation method thereof Download PDFInfo
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- 229910052732 germanium Inorganic materials 0.000 title claims abstract description 48
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 title claims abstract description 48
- 239000002070 nanowire Substances 0.000 title claims abstract description 47
- 238000002360 preparation method Methods 0.000 title claims abstract description 38
- 238000002353 field-effect transistor method Methods 0.000 title description 3
- 239000010410 layer Substances 0.000 claims abstract description 130
- 229910000577 Silicon-germanium Inorganic materials 0.000 claims abstract description 71
- 230000005669 field effect Effects 0.000 claims abstract description 47
- 229910052751 metal Inorganic materials 0.000 claims abstract description 47
- 239000002184 metal Substances 0.000 claims abstract description 47
- 238000000034 method Methods 0.000 claims abstract description 47
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 40
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 40
- 239000010703 silicon Substances 0.000 claims abstract description 40
- 239000000758 substrate Substances 0.000 claims abstract description 40
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims abstract description 38
- 239000000377 silicon dioxide Substances 0.000 claims abstract description 31
- 229910052681 coesite Inorganic materials 0.000 claims abstract description 29
- 229910052906 cristobalite Inorganic materials 0.000 claims abstract description 29
- 229910052682 stishovite Inorganic materials 0.000 claims abstract description 29
- 229910052905 tridymite Inorganic materials 0.000 claims abstract description 29
- WABPQHHGFIMREM-UHFFFAOYSA-N lead(0) Chemical compound [Pb] WABPQHHGFIMREM-UHFFFAOYSA-N 0.000 claims abstract description 24
- 239000011241 protective layer Substances 0.000 claims abstract description 24
- 230000008569 process Effects 0.000 claims abstract description 20
- 229910052581 Si3N4 Inorganic materials 0.000 claims abstract description 18
- 238000005530 etching Methods 0.000 claims abstract description 14
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 claims description 35
- 239000001301 oxygen Substances 0.000 claims description 35
- 229910052760 oxygen Inorganic materials 0.000 claims description 35
- 239000012141 concentrate Substances 0.000 claims description 9
- 238000006243 chemical reaction Methods 0.000 claims description 6
- 239000002253 acid Substances 0.000 claims description 5
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- 240000007594 Oryza sativa Species 0.000 claims 1
- 239000007789 gas Substances 0.000 claims 1
- 229910052738 indium Inorganic materials 0.000 claims 1
- 235000012239 silicon dioxide Nutrition 0.000 abstract description 5
- 238000000151 deposition Methods 0.000 abstract description 3
- 238000009776 industrial production Methods 0.000 abstract description 3
- 238000009833 condensation Methods 0.000 abstract 1
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- YCKRFDGAMUMZLT-UHFFFAOYSA-N Fluorine atom Chemical compound [F] YCKRFDGAMUMZLT-UHFFFAOYSA-N 0.000 description 1
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 1
- WGLPBDUCMAPZCE-UHFFFAOYSA-N Trioxochromium Chemical compound O=[Cr](=O)=O WGLPBDUCMAPZCE-UHFFFAOYSA-N 0.000 description 1
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- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 239000001257 hydrogen Substances 0.000 description 1
- 229910052739 hydrogen Inorganic materials 0.000 description 1
- 125000004435 hydrogen atom Chemical class [H]* 0.000 description 1
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Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0657—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape of the body
- H01L29/0665—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape of the body the shape of the body defining a nanostructure
- H01L29/0669—Nanowires or nanotubes
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66439—Unipolar field-effect transistors with a one- or zero-dimensional channel, e.g. quantum wire FET, in-plane gate transistor [IPG], single electron transistor [SET], striped channel transistor, Coulomb blockade transistor
Abstract
The invention provides a preparation method of a germanium nano wire field effect transistor. The method comprises the following steps: 1), providing an SGOI substrate structure; 2), etching an SiGe layer, and forming an SiGe nano wire array; 3), performing germanium condensation on a structure in step 2) to obtain a germanium nano wire array with a surface wrapped by an SiO2 layer; 4), removing the SiO2 layer wrapping the surface of the two ends of a nano wire to expose the two ends of the germanium nano wire; 5), depositing a metal lead wire, a source electrode and a drain electrode on the extension line of the germanium nano wire; and preparing a grid electrode on a silicon substrate; 6), forming an Si3N4 protective layer on the surface of the structure formed in step 5); and 7), removing the Si3N4 protective layer in a nano wire pattern area and a metal electrode pattern area until the germanium nano wire, the source electrode and the drain electrode are exposed latelytely. According to the invention, the germanium nano wire is prepared based on a top-down method, the technical process is simple, the controllability is high, the method is completely compatible with a conventional CMOS process, and the cost is quite low. Therefore, the germanium nano wire field effect transistor and the preparation method are suitable for industrial production.
Description
Technical field
The invention belongs to the manufacture field of semiconductor device, it is related to a kind of Ge nanoline field-effect transistor and its preparation side
Method.
Background technology
With constantly reducing of integrated circuit feature size, the short-channel effect of field-effect transistor (MOSFET) is increasingly
Seriously.Because double grid, three grid, Ω grid and enclosing structure can effectively increase the device drive current of MOS, suppression device short channel is imitated
Should and off-state current, thus receiving the extensive concern of academia and industry.
In recent years, monodimension nanometer material is had not available for traditional material due to it as nano wire, nanotube, nanometer rods
The properties such as skin effect, small-size effect, quantum size effect, macro quanta tunnel effect are just becoming nano science, micro-
The focus of the cross discipline research such as electronics and biomedicine.The change in electrical charge of planar electrode surface only can cause its surface current-carrying
The exhausting or accumulate of son, nano wire due to high surface volume than and adjustable electron transport property, the slight electric charge in its surface disturbs
Dynamic all can cause exhausting or accumulating, thus causing the strong change of its electric property of its internal carrier.Theoretical upper surface list
The change of individual electric charge will cause the very big change of nano wire electric property, and this change is orientation, background noise
The interference producing to surrounding dispersion change much smaller than planar electrode surface electric charge, this carries out high sensitivity for us using nano wire
Nucleic acid amplification real-time quantitative Electrochemical Detection provides new approaches.
Germanium as one of important semi-conducting material, its have Bohr radius big (for 24.3nm, much larger than silicon
4.9nm), intrinsic carrier concentration height is (for 2.4 × 1013/cm3, much larger than the 1.45 × 10 of silicon10/cm3), intrinsic carrier moves
Shifting rate is high, and (under room temperature, the mobility in electronics and hole is respectively 3900cm2/ V s and 1900cm2/ V s, and silicon be respectively
1500cm2/ V s and 450cm2/ V s) the advantages of, for the nano wire compared to the general semi-conducting material such as silicon, Ge nanoline
Sensitivity is higher, the detection response time faster, be easier to assume the novel electro-optical properties such as quantum limitation effect, in nanometer field effect
The nano-device aspect such as transistor is answered to have good application prospect.Additionally, germanium and the III-V such as GaAs etc. have close lattice normal
Number, germanium is easier to mate with III-V material, so Ge nanoline has in fields such as novel nano device, nanometer connecting wires
Important potential using value.
At present, the method preparing Ge nanoline mainly has laser ablation method, chemical reduction method, solution thermal synthesis method, chemistry
Vapour deposition process (CVD), template, gold catalysis thermal evaporation and supercritical solution method etc..But, above-mentioned preparation method all exists
Defective：Laser ablation method, as relatively early realizing the method for preparing Ge nanoline in a large number, has that operation is simple, product yield is larger
And purity high the features such as, but apparatus expensive, preparation temperature is high, and product cost is higher.CVD then reduces very on preparation temperature
Many, but the diameter Distribution scope of gained Ge nanoline is larger.Although and adopt solvent process for thermosynthesizing preparation temperature relatively low,
That in product, nano-particle is more, the purity of Ge nanoline relatively low although can be prepared uniform and straight using template
Ge nanoline array, but yield is relatively low.Meanwhile, the above-mentioned method preparing Ge nanoline is (Bottom-Up) from bottom to top
Method, that is, be primarily based on chemical reactive synthesis Ge nanoline, then these nano wires transferred to the ad-hoc location shape of substrate
Become functional device, the Ge nanoline that this kind of method prepares is completely incompatible with traditional CMOS technology, and homogeneity is poor, difficult
In operation and arrangement, be difficult to integrated with field-effect transistor etc., leverage in Ge nanoline scene effect transistor should
With.
Content of the invention
The shortcoming of prior art in view of the above, it is an object of the invention to provide a kind of Ge nanoline field effect transistor
The preparation method of pipe, for solving to be bottom-to-top method so that described due to the existing method preparing Ge nanoline
The Ge nanoline of preparation is completely incompatible with traditional CMOS technology, and homogeneity difference is it is difficult to operating and arranging, and is difficult to and field effect
Answer transistor integrated etc., and then leverage the problem of application in Ge nanoline scene effect transistor.
For achieving the above object and other related purposes, the present invention provides a kind of preparation of Ge nanoline field-effect transistor
Method, methods described at least includes：
1) provide a SGOI substrat structure, described SGOI substrat structure includes silicon substrate, is located at described silicon substrate upper surface
Oxygen buried layer and be located at described oxygen buried layer on SiGe layer；
2) etching technics is utilized to etch described SiGe layer, to form the SiGe nano-wire array of preliminary dimension；
3) to described step 2) structure that obtains carries out germanium concentration, and control the process conditions that germanium concentrates to obtain surface quilt
SiO2The Ge nanoline array of the preliminary dimension that layer is wrapped up；
4) remove the SiO being wrapped in described Ge nanoline two end surfaces2Layer, to expose the two ends of described Ge nanoline；
5) deposited metal lead, source electrode and drain electrode on the extended line of described Ge nanoline, described metal draws
One end of line is connected with one end of the described Ge nanoline exposing, and the other end is connected with described source electrode or drain electrode
Connect；Gate electrode is made on described silicon substrate；
6) in described step 5) surface of structure that obtains forms Si3N4Protective layer；
7) graphical described Si3N4Protective layer, to form described Ge nanoline graphics field and metal electrode graphics field,
Remove the Si in described nano wire graphics field and described metal electrode graphics field3N4Protective layer, until expose described completely
Ge nanoline, described source electrode and drain electrode.
Alternatively, in step 1) in, the thickness of described oxygen buried layer is 100nm～150nm；The thickness of described SiGe layer is
100nm～110nm.
Preferably, the thickness of described oxygen buried layer is 130nm；The thickness of described SiGe layer is 105nm.
Preferably, in step 1) in, in described SiGe layer, the group of Ge is divided into 20%～40%.
Alternatively, in step 2) in, the width of the SiGe nano wire that the described SiGe layer of etching is formed is 150nm～200nm.
Preferably, the width of the SiGe nano wire that the described SiGe layer of etching is formed is 180nm.
Preferably, formed by SiO2During the Ge nanoline array of layer parcel, described step 3) comprise the following steps：
3-1) by described step 2) structure that obtains puts in 600 DEG C of reacting furnaces, then passes to the N of 5000ccm2As guarantor
Shield atmosphere, is passed through N with the speed heating reaction furnace rising 10 DEG C per minute to reaching stopping after 950 DEG C2；
3-2) it is passed through the O of 4000ccm2Stop after keeping 45 minutes；
3-3) it is passed through the N of 5000ccm2Stop after keeping 45 minutes；
3-4) in N2Reacting furnace temperature is made to drop to 825 DEG C from 950 DEG C in 1 hour under atmosphere；
3-5) it is passed through the O of 4000ccm2Stop after keeping 60 minutes；
3-6) it is passed through the N of 5000ccm2Stop after keeping 30 minutes；
3-7) in N2Make reacting furnace temperature be down to 600 DEG C from 825 DEG C in 1 hour under atmosphere, complete germanium and concentrate, formed
Include silicon substrate, oxygen buried layer and by SiO successively2The stepped construction of the described Ge nanoline array of layer parcel.
Preferably, the thickness wrapping up the SiO2 layer of described each Ge nanoline is 80-100nm.
Preferably, described Ge nanoline is cylinder, a diameter of 75nm of described Ge nanoline.
Preferably, in step 4) in, the SiO being wrapped in described Ge nanoline two end surfaces is removed using wet etching2Layer,
The etchant solution being used is the Fluohydric acid. of dilution.
Preferably, in step 5) in, described gate electrode deposition is in the lower surface of described silicon substrate.
The present invention also provides a kind of Ge nanoline field-effect transistor, and described Ge nanoline field-effect transistor at least wraps
Include：Silicon substrate；Oxygen buried layer, positioned at the upper surface of described silicon substrate；The Ge nanoline array structure that multiple Ge nanolines are formed, shape
On oxygen buried layer described in Cheng Yu；Described Ge nanoline is coated with SiO2Layer, and described Ge nanoline two ends exposed described
SiO2Outside layer；Multiple metal lead wires, are located at the two ends of described Ge nanoline respectively, and are connected with exposed described Ge nanoline
Connect；Source electrode, is connected with the described metal lead wire positioned at described Ge nanoline one end；Drain electrode, and positioned at described germanium
The described metal lead wire of the nano wire other end is connected；Si3N4Protective layer, is covered in described metal lead wire and described exposed germanium
On the surface of nano wire；Gate electrode, positioned at the lower surface of described silicon substrate.
Preferably, wrap up the SiO of described each Ge nanoline2The thickness of layer is 80-100nm.
Preferably, described Ge nanoline is cylinder, a diameter of 75nm of described Ge nanoline.
As described above, the preparation method of the Ge nanoline field-effect transistor of the present invention, have the advantages that：This
Bright employing Ge nanoline as the raceway groove of field-effect transistor, because germanium is easier, compared to traditional semi-conducting material, the amount of presenting
Sub- restriction effect, can make prepared field-effect transistor have higher sensitivity, detect the response time faster.This
Bright Ge nanoline is based on top-to-bottom method, and technical process is simple, and controllability is strong, completely simultaneous with traditional CMOS technology
Hold, cost relatively low it is adaptable to large-scale industrial production；Meanwhile, using the Ge nanoline surface parcel of germanium concentration technique preparation
The SiO of one layer of stable performance2Layer, is limitedly passivated to Ge nanoline surface, can be protected the steady of Ge nanoline performance
Qualitative；Form one layer of SiO on described Ge nanoline surface2Layer, can adopt existing SiO2Modify repairing of reagent and comparative maturity
The decorations SiO to described Ge nanoline surface for the technique2Modified, for being applied to described Ge nanoline field-effect transistor afterwards
The fields such as biosensor lay the first stone.
Brief description
The flow chart that Fig. 1 is shown as the preparation method of Ge nanoline field-effect transistor of the present invention.
Fig. 2 is shown as the preparation method step 1 of the Ge nanoline field-effect transistor of the present invention) three dimensional structure that presented
Schematic diagram.
Fig. 3～Fig. 4 is shown as the preparation method step 2 of the Ge nanoline field-effect transistor of the present invention) presented three
Dimension structural representation.
Fig. 5 is shown as the preparation method step 3 of the Ge nanoline field-effect transistor of the present invention) three dimensional structure that presented
Schematic diagram.
Fig. 6 is shown as the preparation method step 4 of the Ge nanoline field-effect transistor of the present invention) plan structure that presented
Schematic diagram.
Fig. 7～Fig. 9 is shown as the preparation method step 5 of the Ge nanoline field-effect transistor of the present invention) knot that presented
Structure schematic diagram, wherein, Fig. 7 is located at the overlooking the structure diagram of silicon substrate lower surface for gate electrode, and Fig. 8 is Fig. 7 along AA ' direction
Schematic cross-section, Fig. 9 for gate electrode be located at silicon substrate upper surface schematic cross-section.
Figure 10 is shown as the preparation method step 6 of the Ge nanoline field-effect transistor of the present invention) structure that presented shows
It is intended to.
Figure 11～Figure 12 is shown as the preparation method step 7 of the Ge nanoline field-effect transistor of the present invention) presented
Structural representation, wherein, Figure 11 is the schematic cross-section along BB ' direction for the Figure 12, and Figure 12 is step 7) plan structure that presented
Schematic diagram.
Component label instructions
20 SGOI substrat structures
201 silicon substrates
202 oxygen buried layers
203 SiGe layer
21 mask layers
22 SiGe nano wires
23 Ge nanolines
24 SiO2Layer
25 metal lead wires
26 source electrodes
27 drain electrodes
28 gate electrodes
29 Si3N4Protective layer
Specific embodiment
Below by way of specific instantiation, embodiments of the present invention are described, those skilled in the art can be by this specification
Disclosed content understands other advantages and effect of the present invention easily.The present invention can also be by addition different concrete realities
The mode of applying is carried out or applies, and the every details in this specification can also be based on different viewpoints and application, without departing from
Carry out various modifications and changes under the spirit of the present invention.
Refer to Fig. 1 to Figure 12.It should be noted that the diagram provided in the present embodiment only illustrates this in a schematic way
The basic conception of invention, though only show the assembly relevant with the present invention rather than according to package count during actual enforcement in schema
Mesh, shape and size are drawn, and during its actual enforcement, the kenel of each assembly, quantity and ratio can be a kind of random change, and its
Assembly layout kenel is likely to increasingly complex.
As shown in Figures 1 to 12, the present invention provides a kind of preparation method of Ge nanoline field-effect transistor, and described germanium is received
The preparation method of rice noodle field-effect transistor at least includes：
1) provide a SGOI substrat structure 20, described SGOI substrat structure 20 includes silicon substrate 201, is located at described silicon substrate
The oxygen buried layer 202 of 201 upper surfaces and the SiGe layer 203 being located on described oxygen buried layer 202；
2) etching technics is utilized to etch described SiGe layer 203, to form SiGe nano wire 22 array of preliminary dimension；
3) to described step 2) structure that obtains carries out germanium concentration, and control the process conditions that germanium concentrates to obtain surface quilt
SiO2Ge nanoline 23 array of the preliminary dimension that layer 24 is wrapped up；
4) remove the SiO being wrapped in described 23 liang of end surfaces of Ge nanoline2Layer 24, to expose described Ge nanoline 23
Two ends；
5) deposited metal lead 25, source electrode 26 and drain electrode 27, institute on the extended line of described Ge nanoline 23
The one end stating metal lead wire 25 is connected with one end of the described Ge nanoline 23 exposing, the other end and described source electrode 26
Or drain electrode 27 is connected；Gate electrode 28 is made on described silicon substrate 201；
6) in described step 5) surface of structure that obtains forms Si3N4Protective layer 29；
7) graphical described Si3N4Protective layer 29, to form described Ge nanoline graphics field and metal electrode graph area
Domain, removes the Si in described nano wire graphics field and described metal electrode graphics field3N4Protective layer 29, until completely exposed
Go out described Ge nanoline 23, described source electrode 26 and drain electrode 27.
In step 1) in, refer to S1 step and Fig. 2 of Fig. 1, a SGOI substrat structure 20, described SGOI substrate knot are provided
Structure 20 includes silicon substrate 201, the oxygen buried layer 202 being located at described silicon substrate 201 upper surface and is located on described oxygen buried layer 202
SiGe layer 203.
Specifically, described SGOI substrat structure 20 can be obtained by smart-cut process or other process preparation
?.
Specifically, described SGOI substrat structure 20 include silicon substrate 201, be located at described silicon substrate 201 upper surface bury oxygen
Layer 202 and the SiGe layer 203 being located on described oxygen buried layer 202.Wherein, the thickness of described oxygen buried layer 202 is 100nm～150nm；
The thickness of described SiGe layer 203 is 100nm～110nm it is preferable that in the present embodiment, the thickness of described oxygen buried layer 202 is
130nm；The thickness of described SiGe layer 203 is 105nm.
Specifically, in described SiGe layer 203, the content of Ge will directly affect Ge nano wire formed in subsequent technique
Size, if the content of Ge very little or too much, all would become hard to obtain the Ge nano wire of required size, therefore, described SiGe layer 203
The content of middle Ge should be maintained at a comparison rational within the scope of it is preferable that in the present embodiment, Ge in described SiGe layer 203
Content be 20%～40%.
Specifically, the material of described oxygen buried layer 202 is including but not limited to silicon dioxide.
In step 2) in, refer to S2 step and Fig. 3 to Fig. 4 of Fig. 1, etch described SiGe layer 203 using etching technics,
To form SiGe nano wire 22 array of preliminary dimension.
Specifically, referring initially to Fig. 3, by beamwriter lithography (EBL) technique described SGOI substrat structure 20 institute
State SiGe layer surface and form one layer of mask layer 21 with preset pattern, define window to be etched.Secondly, refer to Fig. 4,
With described mask layer 21 as mask, etch described SiGe layer 203, to form SiGe nano wire 22 array with preliminary dimension.
Specifically, the width etching the SiGe nano wire 22 that described SiGe layer 203 is formed is 150nm～200nm, preferably
Ground, in the present embodiment, the width of described SiGe nano wire 22 is 180nm.
Specifically, the structure being formed after the completion of this step is to include silicon substrate 201, oxygen buried layer 202 and successively from the bottom to top
The structure of SiGe nano wire 22.
It should be noted that completing the etching to described SiGe layer 203, form the SiGe nano wire with preliminary dimension
After 22 arrays, the step that also includes the described mask layer of a removal 21.
Need explanation, completing step 2) after, carry out step 3) before, also tackle described step 2) structure that obtains
Surface is carried out, to remove described step 2) impurity that remained in etching process of the body structure surface that obtains is it is ensured that described
Oxygen buried layer 202 and the cleannes on described SiGe nano wire 22 surface.
In step 3) in, referring to S3 step and Fig. 5 of Fig. 1, to described step 2) structure that obtains carries out germanium concentration, and
Control the process conditions that germanium concentrates to obtain surface by SiO2Ge nanoline 23 array of the preliminary dimension that layer 24 is wrapped up.
Specifically, this step is by described step 2) structure of gained carries out germanium concentration, specifically includes following steps：
3-1) by described step 2) structure that obtains puts in 600 DEG C of reacting furnaces, then passes to the N of 5000ccm2As guarantor
Shield atmosphere, is passed through N with the speed heating reaction furnace rising 10 DEG C per minute to reaching stopping after 950 DEG C2；
3-2) it is passed through the O of 4000ccm2Stop after keeping 45 minutes；
3-3) it is passed through the N of 5000ccm2Stop after keeping 45 minutes；
3-4) in N2Reacting furnace temperature is made to drop to 825 DEG C from 950 DEG C in 1 hour under atmosphere；
3-5) it is passed through the O of 4000ccm2Stop after keeping 60 minutes；
3-6) it is passed through the N of 5000ccm2Stop after keeping 30 minutes；
3-7) in N2Make reacting furnace temperature be down to 600 DEG C from 825 DEG C in 1 hour under atmosphere, complete germanium and concentrate, finally
Formed and include described silicon substrate 201, described oxygen buried layer 202 and by SiO successively2The described Ge nanoline 23 of layer 24 parcel
The stepped construction of array.
Specifically, in the technique that above-mentioned germanium concentrates, carry out thermal oxidative reaction at 950 DEG C and 825 DEG C respectively, this be due to
After 950 DEG C carry out thermal oxidative reaction, the germanium component in described process SiGe nano wire 22 raises, and causes the fusing point of SiGe to reduce,
Therefore after a period of time, need to be further thermal oxide at 825 DEG C in relatively low temperature, to improve Ge nanoline 23 after germanium concentrates
Purity, finally forms very high Ge nanoline 23 array of purity on described oxygen buried layer 202 surface and each described germanium of parcel is received
The SiO on the surface of rice noodle 232Layer 24.In the present embodiment, obtained Ge nanoline 23 can be cylinder, and diameter can be
75nm, wraps up the SiO on each described nano wire 23 surface2The thickness of layer 24 can be 80-100nm, but is not limited to this, described germanium
The shape and size diameter of nano wire 23 can be adjusted according to the needs of actual process, specifically, can exist as needed
Step 1) the middle described SiGe layer 203 forming different-thickness, and then in step 2) the middle SiGe nanometer forming different size width
Line 22, then passes through step 3 again) germanium concentration technology can get required various sizes of Ge nanoline 23.
Specifically, with the thickness of described SiGe layer 203, the size of described SiGe nano wire 22 and germanium described
The size of the described Ge nanoline 23 of the change of the component in SiGe layer 203, above-mentioned process conditions and formation also changes therewith,
And these process conditions are controlled.Therefore, the quality of the Ge nanoline 23 of the method preparation has very high controllability.
It should be noted that in above-mentioned germanium concentration technology, being passed through N2Effect have two, one is as protective atmosphere, separately
One act as making concentrated after SiGe layer or germanium layer in everywhere component uniformly, this be due near surface region can preferential with
O2Reaction, the content of germanium is higher relative to lower floor, thus forming a gradient in SiGe layer, is unfavorable for finally being condensed into germanium.
In step 4) in, refer to S4 step and Fig. 6 of Fig. 1, remove and be wrapped in described 23 liang of end surfaces of Ge nanoline
SiO2Layer 24, to expose the two ends of described Ge nanoline 23.
Specifically, because described Ge nanoline 23 subsequently will be connected with the source electrode of metal and drain electrode, outer layer
Wrap up described SiO2Layer 24 inherently affects the connection between them.So, before carrying out subsequent technique, need described germanium
Nano wire 23 is from described SiO2An exposed out part in layer 24.In the present embodiment, by the two ends of described Ge nanoline 23 from institute
State SiO2Layer 24 in exposed out.
Specifically, can be removed using dry etching or wet-etching technology and be wrapped in described 23 liang of end surfaces of Ge nanoline
SiO2Layer 24 is it is preferable that in the present embodiment, being removed using wet etching and be wrapped in described 23 liang of end surfaces of Ge nanoline
SiO2Layer 24, to expose the two ends of described Ge nanoline 23, the etchant solution being used is the Fluohydric acid. of dilution.
Specifically, remove, in the Fluohydric acid. using dilution, the SiO being wrapped in described 23 liang of end surfaces of Ge nanoline2Layer 24 with
Afterwards, deionized water etc. should be used to clean described step 4) obtained by structure, to remove the hydrogen fluorine remaining in described body structure surface
Acid.
In step 5) in, refer to S5 step and Fig. 7 to Fig. 9 of Fig. 1, the extended line of described Ge nanoline 23 deposits
Metal lead wire 25, source electrode 26 and drain electrode 27, one end of described metal lead wire 25 and the described Ge nanoline exposing
23 one end is connected, and the other end is connected with described source electrode 26 or drain electrode 27；Described silicon substrate 201 makes
Gate electrode 28.
Specifically, naked in each described Ge nanoline 23 using any one metal deposition process in existing semicon industry
Difference deposited metal lead 25 on the two ends of dew, described metal lead wire 25 is located on the same line with described Ge nanoline 23,
And one end that described metal lead wire 25 one end is exposed with described Ge nanoline 23 is connected, the other end is respectively directed to described germanium and receives
The outside of rice noodle 23.The part that described metal lead wire 25 is contacted with described Ge nanoline 23 is the source of described field-effect transistor
Polar region domain or drain region.
Specifically, the material of described metal lead wire 25 can be for Ti, Au, Pt, Gr, Cu or Al it is preferable that the present embodiment
In, the material of described metal lead wire 25 is Al.
Specifically, using any one metal deposition process in existing semicon industry in described metal lead wire 25 away from described
One end of Ge nanoline 23 deposits described source electrode 26 and described drain electrode 27, described source electrode 26 and described drain electrode electricity
Pole 27 is located at the relative two ends of described Ge nanoline 23 respectively.
Specifically, described source electrode 26 and described drain electrode 27 are metal electrode, described source electrode 26 and institute
The material stating drain electrode 27 can be Ti, Au, Pt, Gr, Cu or Ti/Au.Preferably, in the present embodiment, described source electrode
26 and the material of described drain electrode 27 be Ti/Au.
Because exposed described Ge nanoline 23 surface easily forms unstable chromium oxide, described whole field can be imitated
The performance answering transistor produces impact.So that described field-effect transistor has more stable performance it is necessary to exposed
Described Ge nanoline 23 on deposit layer protective layer.So, in the present embodiment, by the source region of described field-effect transistor
Drawn by described metal lead wire 25 with drain region, and form corresponding source electrode 26 and drain electrode in corresponding position
27, such design can protect described Ge nanoline 23, and does not affect the carrying out of follow-up test.
Specifically, described gate electrode 28 is to be obtained by deposit metal electrodes on described silicon substrate 201, to be obtained
Required backgate field-effect transistor.Described gate electrode 28 i.e. can be as shown in Figure 8 be formed at described silicon substrate 201
Lower surface, again can be as shown in Figure 9, removes the described oxygen buried layer 202 of described source electrode 26 side by etching, then exists
Formed on the described silicon substrate 201 exposing.
Specifically, described gate electrode 28 is also metal electrode, the material of described gate electrode 28 can for Ti, Au, Pt,
Gr, Cu or Ti/Au.Preferably, in the present embodiment, the material of described gate electrode 28 is Ti/Au.
In step 6) in, referring to S6 step and Figure 10 of Fig. 1, in described step 5) surface of structure that obtains formed
Si3N4Protective layer 29.
Specifically, can be using chemical vapour deposition technique (CVD) or physical vaporous deposition (PVD) in described step 5)
The body structure surface arriving deposits described Si3N4Protective layer 29.Described Si3N4Protective layer 29 covers entirely described step 5) knot that obtains
The upper surface of structure.
In step 7) in：Refer to S7 step and Figure 11 to Figure 12 of Fig. 1, graphically described Si3N4Protective layer 29, with shape
Become described Ge nanoline graphics field and metal electrode graphics field, remove described nano wire graphics field and described metal electrode
Si in graphics field3N4Protective layer 29, until expose described Ge nanoline 23, described source electrode 26 and drain electrode electricity completely
Pole 27.
Specifically, can described Si now3N4One layer of mask layer with opening, described mask layer are formed on protective layer 29
Opening correspond to the region that the region that described Ge nanoline 23 is located and described source electrode 26 and drain electrode 27 are located；
Then according to described mask layer be barrier layer, etch described Si3N4Protective layer 29, until completely expose described Ge nanoline 23,
Described source electrode 26 and drain electrode 27；Finally remove described mask layer.
Refer to Figure 11 to Figure 12, wherein, Figure 12 is overlooking the structure diagram, Figure 11 is the section along BB ' direction for the Figure 12
Schematic diagram, the present invention also provides a kind of described Ge nanoline field-effect transistor, and institute's Ge nanoline field-effect transistor at least wraps
Include：
Silicon substrate 201；
Oxygen buried layer 202, described oxygen buried layer 202 is located at the upper surface of described silicon substrate 201；
Ge nanoline 23 array structure that multiple Ge nanolines 23 are formed, described Ge nanoline 23 array structure is formed at institute
State on oxygen buried layer 202；Described Ge nanoline 23 is coated with SiO2Layer 24, and described Ge nanoline 23 two ends exposed in institute
State SiO2Outside layer 24；
Multiple metal lead wires 25, described metal lead wire 25 respectively be located at described Ge nanoline 23 two ends, and with exposed
Described Ge nanoline 23 is connected；
Source electrode 26, described source electrode 26 is connected with the described metal lead wire 25 positioned at described Ge nanoline 23 one end
Connect；
Drain electrode 27, described drain electrode 27 is connected with the described metal lead wire 25 positioned at described Ge nanoline 23 other end
Connect；
Si3N4Protective layer 29, described Si3N4Protective layer 29 is covered in described metal lead wire 25 and described exposed germanium nanometer
On the surface of line 23；
Gate electrode 25, described gate electrode 25 is located at the lower surface of described silicon substrate 201.
Specifically, the material of described oxygen buried layer 202 is including but not limited to silicon dioxide；The thickness of described oxygen buried layer 202
For 100nm～150nm.Preferably, in the present embodiment, the thickness of described oxygen buried layer 202 is 130nm.
Specifically, described Ge nanoline 23 is cylinder, and a diameter of 75nm, wraps up each described nano wire 23 surface
SiO2The thickness of layer 24 is 80-100nm.
Specifically, the material of described metal lead wire 25 can be for Ti, Au, Pt, Gr, Cu or Al it is preferable that the present embodiment
In, the material of described metal lead wire 25 is Al.
Specifically, described source electrode 26, described drain electrode 27 and described gate electrode 28 are metal electrode, described
The material of source electrode 26, described drain electrode 27 and described gate electrode 28 can be Ti, Au, Pt, Gr, Cu or Ti/Au.Excellent
Selection of land, in the present embodiment, the material of described source electrode 26, described drain electrode 27 and described gate electrode 28 is Ti/Au.
In sum, the present invention adopts Ge nanoline as the raceway groove of field-effect transistor, because germanium is compared to traditional
Semi-conducting material is easier to assume quantum limitation effect, can make prepared field-effect transistor have higher sensitivity,
The detection response time faster.The Ge nanoline of the present invention is based on top-to-bottom method, and technical process is simple, and controllability is strong,
Completely compatible with traditional CMOS technology, cost relatively low it is adaptable to large-scale industrial production；Meanwhile, by controlling in advance
The size of the SiGe nano wire being formed in the thickness of SiGe layer and etching process in SGOI substrate, can be using germanium concentration technique
During obtain required various sizes of Ge nanoline；One layer of performance is wrapped up on Ge nanoline surface using the preparation of germanium concentration technique
Stable SiO2Layer, is limitedly passivated to Ge nanoline surface, can be protected the stability of Ge nanoline performance；Institute
State Ge nanoline surface and form one layer of SiO2Layer, can adopt existing SiO2Modify the modification process pair of reagent and comparative maturity
The SiO on described Ge nanoline surface2Modified, for afterwards described Ge nanoline field-effect transistor being applied to bio-sensing
The fields such as device lay the first stone.
Above-described embodiment only principle of the illustrative present invention and its effect, not for the restriction present invention.Any ripe
The personage knowing this technology all can carry out modifications and changes without prejudice under the spirit and the scope of the present invention to above-described embodiment.Cause
This, those of ordinary skill in the art is complete with institute under technological thought without departing from disclosed spirit such as
All equivalent modifications becoming or change, must be covered by the claim of the present invention.
Claims (14)
1. a kind of preparation method of Ge nanoline field-effect transistor is it is characterised in that the method comprises the following steps：
1) provide a SGOI substrat structure, described SGOI substrat structure includes silicon substrate, is located at burying of described silicon substrate upper surface
Oxygen layer and the SiGe layer being located on described oxygen buried layer；
2) etching technics is utilized to etch described SiGe layer, to form SiGe nano-wire array；
3) to described step 2) structure that obtains carries out germanium concentration, and control the process conditions that germanium concentrates to obtain surface by SiO2
The Ge nanoline array that layer is wrapped up；
4) remove the SiO being wrapped in described Ge nanoline two end surfaces2Layer, to expose the two ends of described Ge nanoline；
5) deposited metal lead, source electrode and drain electrode on the extended line of described Ge nanoline, described metal lead wire
One end is connected with one end of the described Ge nanoline exposing, and the other end is connected with described source electrode or drain electrode；
Gate electrode is made on described silicon substrate；
6) in described step 5) surface of structure that obtains forms Si3N4Protective layer；
7) graphical described Si3N4Protective layer, to form described Ge nanoline graphics field and metal electrode graphics field, removes
Si in described nano wire graphics field and described metal electrode graphics field3N4Protective layer, until expose described germanium completely receive
Rice noodle, described source electrode and drain electrode.
2. Ge nanoline field-effect transistor according to claim 1 preparation method it is characterised in that：In step 1)
In, the thickness of described oxygen buried layer is 100nm～150nm；The thickness of described SiGe layer is 100nm～110nm.
3. Ge nanoline field-effect transistor according to claim 2 preparation method it is characterised in that：Described oxygen buried layer
Thickness be 130nm；The thickness of described SiGe layer is 105nm.
4. Ge nanoline field-effect transistor according to claim 1 preparation method it is characterised in that：In step 1)
In, in described SiGe layer, the group of Ge is divided into 20%～40%.
5. Ge nanoline field-effect transistor according to claim 1 preparation method it is characterised in that：In step 2)
In, the width of the SiGe nano wire that the described SiGe layer of etching is formed is 150nm～200nm.
6. Ge nanoline field-effect transistor according to claim 5 preparation method it is characterised in that：Etching is described
The width of the SiGe nano wire that SiGe layer is formed is 180nm.
7. Ge nanoline field-effect transistor according to claim 1 preparation method it is characterised in that：Formed by SiO2
During the Ge nanoline array of layer parcel, described step 3) comprise the following steps：
3-1) by described step 2) structure that obtains puts in 600 DEG C of reacting furnaces, then passes to the N of 5000ccm2As shielding gas
Atmosphere, is passed through N with the speed heating reaction furnace rising 10 DEG C per minute to reaching stopping after 950 DEG C2；
3-2) it is passed through the O of 4000ccm2Stop after keeping 45 minutes；
3-3) it is passed through the N of 5000ccm2Stop after keeping 45 minutes；
3-4) in N2Reacting furnace temperature is made to drop to 825 DEG C from 950 DEG C in 1 hour under atmosphere；
3-5) it is passed through the O of 4000ccm2Stop after keeping 60 minutes；
3-6) it is passed through the N of 5000ccm2Stop after keeping 30 minutes；
3-7) in N2Make reacting furnace temperature be down to 600 DEG C from 825 DEG C in 1 hour under atmosphere, complete germanium and concentrate, formed successively
Include silicon substrate, oxygen buried layer and by SiO2The stepped construction of the described Ge nanoline array of layer parcel.
8. Ge nanoline field-effect transistor according to claim 7 preparation method it is characterised in that：Wrap up each described
The SiO of Ge nanoline2The thickness of layer is 80-100nm.
9. Ge nanoline field-effect transistor according to claim 7 preparation method it is characterised in that：Described germanium nanometer
Line is cylinder, a diameter of 75nm of described Ge nanoline.
10. Ge nanoline field-effect transistor according to claim 1 preparation method it is characterised in that：In step 4)
In, the SiO being wrapped in described Ge nanoline two end surfaces is removed using wet etching2Layer, the etchant solution being used is dilution
Fluohydric acid..
The preparation method of 11. Ge nanoline field-effect transistors according to claim 1 it is characterised in that：In step 5)
In, described gate electrode deposition is in the lower surface of described silicon substrate.
A kind of 12. Ge nanoline field-effect transistors are it is characterised in that include：
Silicon substrate；
Oxygen buried layer, positioned at the upper surface of described silicon substrate；
The Ge nanoline array structure that multiple Ge nanolines are formed, is formed on described oxygen buried layer；Described Ge nanoline surface bag
It is wrapped with SiO2Layer, and described Ge nanoline two ends exposed in described SiO2Outside layer；
Multiple metal lead wires, are located at the two ends of described Ge nanoline respectively, and are connected with exposed described Ge nanoline；
Source electrode, is connected with the described metal lead wire positioned at described Ge nanoline one end；
Drain electrode, is connected with the described metal lead wire positioned at the described Ge nanoline other end；
Si3N4Protective layer, is covered on described metal lead wire and the surface of described exposed Ge nanoline；
Gate electrode, positioned at the lower surface of described silicon substrate.
13. Ge nanoline field-effect transistors according to claim 12 it is characterised in that：Wrap up each described Ge nanoline
SiO2The thickness of layer is 80-100nm.
14. Ge nanoline field-effect transistors according to claim 12 it is characterised in that：Described Ge nanoline is cylinder
Shape, a diameter of 75nm of described Ge nanoline.
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| CN102082096A (en) * | 2010-10-09 | 2011-06-01 | 北京大学 | Method for preparing Ge or SiGe nanowire field effect transistor |
| CN103187249A (en) * | 2011-12-30 | 2013-07-03 | 中国科学院物理研究所 | Semiconductor nanomaterial device and manufacturing method thereof |
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| CN102082096A (en) * | 2010-10-09 | 2011-06-01 | 北京大学 | Method for preparing Ge or SiGe nanowire field effect transistor |
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