CN104320135A - High-purity frequency source - Google Patents
High-purity frequency source Download PDFInfo
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- CN104320135A CN104320135A CN201410611959.9A CN201410611959A CN104320135A CN 104320135 A CN104320135 A CN 104320135A CN 201410611959 A CN201410611959 A CN 201410611959A CN 104320135 A CN104320135 A CN 104320135A
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Abstract
The invention discloses a high-purity frequency source, and belongs to the technical field of wireless communication. The high-purity frequency source comprises a reference source, a single chip microcomputer, phase-locked loop (PLL) modules and an isolation and amplification circuit. The PLL modules comprise the first PLL module and the second PLL module, the constitution and the parameter of the first PLL module are completely the same as the constitution and the parameter of the second PLL module, and the first PLL module and the second PLL module are both controlled by the same single chip microcomputer. The input end of the first PLL module and the input end of the second PLL module are together connected with the output end of the reference source, and the output end of the first PLL module and the output end of the second PLL module are together connected with a diverter switch and are output finally. The high-purity frequency source can simultaneously meet the demands for high spurious suppression degrees, high-speed frequency switching, low power consumption and small sizes, provide high-quality signal sources for radar and a communication system, and therefore improve the overall performance of the radar and the communication system.
Description
Technical field
The invention belongs to wireless communication technology field, be specifically related to a kind of high-purity frequency source.
Background technology
Frequency source is the important component part of contemporary electronic systems, is called as " heart " of many electronic systems.In the equipment such as communication, radar and navigation, it is the exciting signal source of transmitter, is again the local oscillator of receiver; In a test device, it can as standard signal source.Along with the development of modern electrical and electronic technology, the requirement of people to frequency source is more and more higher, and the performance index of frequency source directly produce basic impact to the overall performance of radar system and communication system.
The main performance index of frequency source is: the purity (i.e. noise restraint), phase noise, frequency switching time etc. of frequency spectrum.The frequency source that high-purity low spurious and fast frequency switch is the difficult point of design and development, and the frequency source of performance brilliance is all realized by the technology of frequency synthesis.
Current frequency source scheme as depicted in figs. 1 and 2.
The solution principle of Fig. 1 is direct synthesis type frequency source, its scheme is: with the constant-temperature crystal oscillator of the low phase noise of a 100MHz as with reference to source, the clock signal of 1GHz is obtained, for DDS (Direct Digital Synthesizer Direct Digital Synthesizer) provides clock after 10 frequencys multiplication.The parallel frequency hopping control code that FPGA (high-speed programmable Digital Logical Circuits) inputs according to outside, programming Control DDS exports corresponding frequency, again by producing the frequency of needs after n frequency multiplication, finally by the frequency range exporting needs after variable connector Choose filtering.Adopt the program, although good phase noise can be reached, within Hopping time can accomplish 1 μ s, but spuious index can not accomplish good level (>=70dBc), and larger, the overall power consumption of its volume is comparatively large, caloric value is comparatively large, affects its reliability to a certain extent.
The solution principle of Fig. 2 is PLL phase-locked loop frequency source, its scheme is: adopt the constant-temperature crystal oscillator of the low phase noise of a 100MHz as with reference to source, for PLL (Phase Locked Loop phase-locked loop) digital phase-locked loop chip provides phase-locked required reference clock signal.VCO (voltage controlled oscillator) produces the free oscillation signal needed in frequency range, a road is divided to feed back to phase-locked loop chip through frequency division to phase demodulation frequency f1,100MHz reference clock is also input to phase-locked loop chip frequency division and carries out phase demodulation (phase compare) to phase demodulation frequency f2, f1 and f2.The optimum configurations such as concrete frequency step, reference frequency output and phase demodulation frequency by FPGA single-chip microcomputer by the configuration of programming realization to PLL digital phase-locked loop chip, after single-chip microcomputer receives parallel frequency hopping control code, phase-locked loop chip is configured, makes its requirement by frequency hopping control code carry out work.The clock signal of 100MHz and the signal of VCO voltage controlled oscillator carry out phase demodulation at PLL chip internal after frequency division, by PLL chip output phase error electric current, in the frequency required at frequency hopping control code by the Frequency Locking of the spuious rear control VCO of LF loop filter filtering phase demodulation.Thus obtain a signal that can be controlled by frequency hopping control code.
The scheme of Fig. 2 is carried out key index and is analyzed as follows:
(1) to make an uproar mutually index analysis
The key affecting phase-locked loop phase noise specifications is the normalization low noise of digital phase-locked loop chip, the phase noise of 100MHz reference clock and the phase noise of voltage controlled oscillator.Wherein the phase noise of voltage controlled oscillator mainly has an impact to the phase noise outside loop bandwidth, as long as select the voltage controlled oscillator of low phase noise, then the phase noise level outside PLL loop bandwidth all can accomplish good level.Herein for the digital phase-locked loop chip ADF4106 of AD company, mainly the phase noise in loop bandwidth is analyzed.
The normalization low noise of phase discriminator is-219dBc/Hz
The phase noise of 100MHz constant-temperature crystal oscillator can reach-155dBc/Hz@1KHz at 1KHz
Phase noise computing formula in the loop bandwidth of phase-locked loop is:
Lfloor+20Log(f0/fpD)+10LogfPD
Wherein Lfloor is the normalization low noise of PLL chip, f0/fPD be output frequency divided by phase demodulation frequency and frequency multiplication times N, fPD is phase demodulation frequency.Phase noise in loop bandwidth can be calculated as follows:
Above-mentioned parameter is brought into formula can calculate (calculating by 1160MHz output frequency):
Phase noise in loop band is:
-219+20Log(1160/10)+10Log(10×106)≈-108dBc/Hz。
Reference source phase noise frequency multiplication worsens
The deterioration computing formula of the phase noise of reference source is:
20Log(f0/fPD)
Being-155dBc/Hz@1KHz by the phase noise of reference to calculate the phase noise after deterioration is:
-155+20Log(1160/10)≈-113.7dBc/Hz@1KHz
Because the phase noise in loop band is higher than the phase noise after reference source deterioration, the final phase noise exported still depends on the phase noise i.e.-108dBc/Hz@1KHz in loop;
(2) Hopping time analysis
Owing to adopting phase-locked loop manner, the principal element affecting Hopping time is the setup time of phase-locked loop chip and the RC time constant of loop filter.Wherein the setup time of phase-locked loop chip is 10 μ about s, and the time of loop filter is then main influencing factor.When frequency hopping wider range, can only accomplish 30 μ about s, in the setup time adding phase-locked loop chip, then the frequency switching time of this kind of scheme is 40 μ about s.The requirement that fast frequency switches can not be met.
(3) spurious reduction analysis
The spuious index of digital phase-locked loop depends primarily on the bandwidth of phase demodulation frequency and loop filter.Have employed the ADF4106 chip of integral frequency divisioil in scheme, its frequency step exported is 10MHz, and its phase demodulation frequency can only get 10MHz, so the final spurious signal exported is that phase demodulation is spuious, namely departs from the spurious signal of output frequency ± 10MHz.Because the bandwidth of loop filter can be accomplished narrow, as 200KHz, the degree of suppression so for the spurious signal of ± 10MHz all can be accomplished very high, therefore noise restraint can reach the level of more than 75dBc.But when the bandwidth of loop filter is narrower, the time constant of its RC is longer, causes the frequency switching time of phase-locked loop to lengthen.So adopt the Hopping time of this scheme and noise restraint index not to take into account.
(4) analysis of other side
The simple volume of realizing circuit of the program is little, and components and parts power consumption is less, and caloric value is low, and reliability is higher.But its frequency error factor can not accomplish quick switching.
Comprehensively above-mentioned Analysis and summary, frequency source scheme traditional at present all can not meet the index of high noise restraint and fast frequency switching and the requirement of low power consumption and small volume simultaneously, impacts the overall performance of radar and communication system.
Summary of the invention
The object of the invention is to design a kind of high-purity frequency source, it can realize high noise restraint simultaneously and fast frequency switches and the requirement of low power consumption and small volume, for radar and communication system provide high-quality signal source, thus promote the overall performance of radar and communication system.
The present invention takes following technical scheme
A kind of high-purity frequency source, it comprises reference source, single-chip microcomputer, phase-locked loop module, isolating amplifier circuit, and described PLL phase-locked loop module is primarily of PLL phase-locked loop chip, LF loop filter, VCO voltage controlled oscillator composition, it is also provided with diverter switch, described phase-locked loop module comprises a PLL phase-locked loop module, 2nd PLL phase-locked loop module, a described PLL phase-locked loop module is identical with parameter with the composition of the 2nd PLL phase-locked loop module, a described PLL phase-locked loop module and the 2nd PLL phase-locked loop module are all by described Single-chip Controlling, input and the input of the 2nd PLL phase-locked loop module of the one PLL phase-locked loop module are connected the output of described reference source jointly, the output of the one PLL phase-locked loop module is connected described diverter switch jointly with the output of the 2nd PLL phase-locked loop module, its signal is after described diverter switch switches, finally export after postpositive disposal module again.
Further technical scheme is: described postpositive disposal module comprises the isolating amplifier circuit, the large circuit of power, the harmonic filter circuit that connect successively.
Further technical scheme is: described phase-locked loop module is at least set to two groups.
Further technical scheme is: described diverter switch is single-pole double-throw switch (SPDT) (SPDT).
Further technical scheme is: in a described PLL phase-locked loop module or the 2nd PLL phase-locked loop module, the output of VCO voltage controlled oscillator is also connected with single-pole single-throw switch (SPST).
Further technical scheme is: the VCO voltage controlled oscillator in a described PLL phase-locked loop module or the 2nd PLL phase-locked loop module is also connected with low-dropout regulator.
The present invention compared with prior art, has following beneficial effect: present invention employs the frequency that two groups of PLL phase-locked loops carry out phase-locked generation similar frequency bands, parameter and the device of two groups of PLL phase-locked loops are completely the same; Utilize one 2 and select the single-pole double-throw switch (SPDT) of 1 to carry out carrying out selection switching to output frequency; Two groups of PLL phase-locked loops are for work simultaneously, make use of the advantage of switch energy high speed switching channel, the high speed achieving frequency switches, because the spuious index of traditional digital phase-locked loop can accomplish higher level, and its volume and power consumption all can be accomplished very little, so the program has high noise restraint and fast frequency switches and the advantage of low power consumption and small volume.
Accompanying drawing explanation
Fig. 1 is direct synthesis type frequency source theory diagram;
Fig. 2 is PLL phase-locked loop frequency source theory diagram;
Fig. 3 is system block diagram of the present invention;
Fig. 4 is circuit block diagram of the present invention;
Fig. 5 a is control code of the present invention and power supply schematic diagram;
Fig. 5 b is single chip machine controlling circuit schematic diagram of the present invention;
Fig. 5 c is PLL phase-locked loop module circuit theory diagrams of the present invention;
Fig. 5 d is the 2nd PLL phase-locked loop module circuit theory diagrams of the present invention;
Fig. 5 e is rearmounted output processing module circuit theory diagrams of the present invention;
Fig. 6 a is this single PLL frequency switching time schematic diagram;
Fig. 6 b is medium frequency schematic diagram switching time of the present invention.
Embodiment
Below in conjunction with embodiments of the invention, the invention will be further elaborated.
Principle of the present invention: as shown in Figure 3, the operation principle of single group phase-locked loop part of the present invention is consistent with traditional digital phase-locked loop operation principle, and its difference is the working method that have employed dicyclo " table tennis ":
When frequency source works on power, FPGA Single-chip Controlling two digital phase-locked loops work simultaneously, and produce parallel frequencies control code D
0, D
1.。。D
nthe output frequency controlled, FPGA single-chip microcomputer produces switch and selects control code S simultaneously
1also control the diverter switch that 2 select 1, acquiescence selects the signal of wherein any one PLL phase-locked loop to export.Another one is not selected the PLL digital phase-locked loop exported just can be undertaken preset by the control of outside.Its preset mode is: by initialize switch S
0set high level, frequency hopping control code is preset on the Frequency point of needs simultaneously, now do not selected the output frequency of the PLL digital phase-locked loop exported to jump on preset Frequency point.Due to S
0set high level, FPGA is to selecting the phase-locked loop frequency exported to carry out change configuration.When needs frequency error factor by S
0set low level, change S simultaneously
1logic level, make diverter switch select the preset digital phase-locked loop that completes to export.At this moment again can by S
0set high level, change frequency hopping control code simultaneously and carry out the preset of next frequency.Cyclically carry out switching that is preset and frequency thus;
The control of frequency and the control of switch all have employed high speed programmable logic circuit FPGA, therefore its time can accomplish ns magnitude, owing to have employed the preset working method of Double-number phase-locked loop " table tennis ", the preset generation when another phase-locked loop operation of next frequency, this does not just need the locking time considering single phase-locked loop.And the switching time of two frequency bins only depends on the select time of switch.And the select time of switch can reach ns magnitude, so adopt this kind of scheme, frequency switching time can accomplish 1 below μ s, achieves the function that fast frequency switches.Because the spuious index of traditional digital phase-locked loop can accomplish higher level, and its volume and power consumption all can be accomplished very little.So the program has high noise restraint and fast frequency switches and the advantage of low power consumption and small volume.
Composition graphs 4, Fig. 5 a and specific embodiment, be described as follows:
100MHz reference signal from constant-temperature crystal oscillator is supplied to two PLL phase-locked loop chips respectively.Each PLL phase-locked loop chip is inner carries out PLL frequency phase demodulation by 100MHz reference signal and VCO output signal frequency division to same frequency, discriminator output error voltage is to loop filter, phase demodulation error voltage is mainly filtered into direct voltage by loop filter, control VCO exports the frequency signal of specifying, this signal exports single-pole double-throw switch (SPDT) to after isolation is amplified, finally select previously preset frequency output signal by single-pole double-throw switch (SPDT), this signal finally exports after isolation amplification, power amplification, harmonic process again.FPGA is mainly configured these two PLL phase-locked loop chips, and change frequency dividing ratio and realize PLL frequency hopping, preset output frequency selected by control switch simultaneously.
Before system hops, need the frequency of the preset next one point of 50us in advance, when switching frequency, response time only depends on the response speed of FPGA program and the switching time of switch, after the switch control program partial compilation of FPGA, almost all be made up of logical device, the response time is only depended on and the delay of clock frequency and gate can reach ns magnitude.When after frequency error factor, system needs to quick initialize next Frequency point, for next rate-adaptive pacemaker is prepared.Here frequency switching time refers to that a Frequency point saltus step is to switching time of next Frequency point, as shown in Figure 6 a, if use single PLL to carry out frequency hopping, when skipping to next Frequency point from a Frequency point, middle transition band has the loop search condition of frequency saltus step back and forth; As shown in Figure 6 b, adopt two PLL to carry out frequency hopping, the pre-postpone switching over of frequency hopping, the transition band of frequency hopping does not have the signal generation of other frequency, only have the vacancy time of one section of non-output signal, and this time is very short.
Further embodiment:
" table tennis " mode of employing carries out frequency error factor, frequency agility bounce time during conventional P LL frequency hopping can be converted to stand-by period during stable output frequency; When adopting many PLL to carry out preset, can shorten stand-by period during predetermined frequency further, shortening half when the stand-by period, required preset PLL quantity in advance will double, and the stand-by period is shorter, and cost will be higher.
Further embodiment:
In circuit theory diagrams of the present invention shown in Fig. 5 b, Fig. 5 c, Fig. 5 d, Fig. 5 e, A1 is single-chip microcomputer, is mainly 2 tunnel PLL frequency synthesizer chips and carries out initial configuration and frequency preset.A2, A3 are synthesizer chip, are integrated with digital frequency divider, phase discriminator, cyclelog and register in this chip.A4, A5 form 2 road PLL active loop filters, filter loop noise, control loop bandwidth.A6, A10 are linear stable device, are+12V by+15V voltage transitions, provide the VCO stabilized supply voltage of A21, A22 respectively.A11, A12, A13 form single-pole double-throw switch (SPDT), 2 grades of series connection main raising switch isolation degree.A17, A18, A19 are for A11, A12, A13 switch transition control logic and provide driving force.A8, A9 are 2 linear voltage regulators, voltage is down to+3.3V from+15V, provides burning voltage to switching circuit.A14 is for taking away amplifier, and A7 is that it provides+5V the voltage after being changed by+15V.A20 is non-level amplifier.A22, A23 form cascading filter, improve the harmonics restraint of output signal.
The technical indicator that in the present invention, high-purity frequency source reaches is as follows
A. frequency range C-band f
0=960MHz ~ 1160MHz, BW=200MHz;
B. frequency interval: Δ f=10MHz, totally 201 frequencies;
C. phase noise: ￡ (1kHz) <-105dBc/Hz;
D. Hopping time: τ < 10 μ s;
E. harmonics restraint: >=50dBc
F. spurious reduction: S
p> 70dBc;
G. power output: P
0=10dBm ± 1dB;
H. output VSWR :≤1.5;
I. working temperature: t=-40 DEG C ~+70 DEG C;
J. size restrictions: 60 × 60 × 35.
Although with reference to explanatory embodiment of the present invention, invention has been described here, above-described embodiment is only the present invention's preferably execution mode, embodiments of the present invention are not restricted to the described embodiments, should be appreciated that, those skilled in the art can design a lot of other amendment and execution mode, these amendments and execution mode will drop within spirit disclosed in the present application and spirit.
Claims (6)
1. a high-purity frequency source, it comprises reference source, single-chip microcomputer, phase-locked loop module, isolating amplifier circuit, described PLL phase-locked loop module is primarily of PLL phase-locked loop chip, LF loop considers ripple device, VCO voltage controlled oscillator forms, it is characterized in that: it is also provided with diverter switch, described phase-locked loop module comprises a PLL phase-locked loop module, 2nd PLL phase-locked loop module, a described PLL phase-locked loop module is identical with parameter with the composition of the 2nd PLL phase-locked loop module, a described PLL phase-locked loop module and the 2nd PLL phase-locked loop module are all by described Single-chip Controlling, input and the input of the 2nd PLL phase-locked loop module of the one PLL phase-locked loop module are connected the output of described reference source jointly, the output of the one PLL phase-locked loop module is connected described diverter switch jointly with the output of the 2nd PLL phase-locked loop module, its signal is after described diverter switch switches, finally export after postpositive disposal module again.
2. according to the high-purity frequency source described in claim 1, it is characterized in that: described postpositive disposal module comprises the isolating amplifier circuit, the large circuit of power, the harmonic wave worry wave circuit that connect successively.
3. according to the high-purity frequency source described in claim 1, it is characterized in that: described PLL phase-locked loop module is at least set to two groups.
4. according to the high-purity frequency source described in claim 1, it is characterized in that: described diverter switch is single-pole double-throw switch (SPDT).
5., according to the high-purity frequency source described in claim 1, it is characterized in that the output of the VCO voltage controlled oscillator in a described PLL phase-locked loop module or the 2nd PLL phase-locked loop module is also connected with single-pole single-throw switch (SPST).
6., according to the high-purity frequency source described in claim 1, it is characterized in that the VCO voltage controlled oscillator in a described PLL phase-locked loop module or the 2nd PLL phase-locked loop module is also connected with low-dropout regulator.
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| CN105356878A (en) * | 2015-12-04 | 2016-02-24 | 东南大学 | Realization method and apparatus of improved three-ring bandwidth frequency synthesizer |
| CN105406862A (en) * | 2015-12-07 | 2016-03-16 | 扬州海科电子科技有限公司 | Low stray broadband 10-20GHz phase lock loop device |
| CN105610439A (en) * | 2016-03-10 | 2016-05-25 | 成都西科微波通讯有限公司 | Frequency preset circuit |
| CN107911111A (en) * | 2017-11-16 | 2018-04-13 | 北京遥感设备研究所 | A kind of S-band fast frequency hopping rate source based on phaselocked loop and matrix switch |
| CN109104188A (en) * | 2018-10-12 | 2018-12-28 | 南京屹信航天科技有限公司 | It is a kind of for minimizing the local oscillation circuit of ODU receiving channel |
| CN109167572A (en) * | 2018-10-12 | 2019-01-08 | 南京屹信航天科技有限公司 | It is a kind of for minimizing the frequency synthesizer of ODU receiving channel |
| CN109656857A (en) * | 2018-12-19 | 2019-04-19 | 南京威翔科技有限公司 | A kind of multifrequency point based on FPGA is switched fast output control method |
| CN116203594A (en) * | 2023-05-06 | 2023-06-02 | 石家庄银河微波技术股份有限公司 | Device and system for generating radio navigation signal |
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| CN109167572A (en) * | 2018-10-12 | 2019-01-08 | 南京屹信航天科技有限公司 | It is a kind of for minimizing the frequency synthesizer of ODU receiving channel |
| CN109656857A (en) * | 2018-12-19 | 2019-04-19 | 南京威翔科技有限公司 | A kind of multifrequency point based on FPGA is switched fast output control method |
| CN116203594A (en) * | 2023-05-06 | 2023-06-02 | 石家庄银河微波技术股份有限公司 | Device and system for generating radio navigation signal |
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Application publication date: 20150128 |