CN104319248A - Method for forming semiconductor testing fixture - Google Patents
Method for forming semiconductor testing fixture Download PDFInfo
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- CN104319248A CN104319248A CN201410606075.4A CN201410606075A CN104319248A CN 104319248 A CN104319248 A CN 104319248A CN 201410606075 A CN201410606075 A CN 201410606075A CN 104319248 A CN104319248 A CN 104319248A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
- H01L22/30—Structural arrangements specially adapted for testing or measuring during manufacture or treatment, or specially adapted for reliability measurements
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Abstract
The invention provides a method for forming a semiconductor testing fixture. The method for forming the semiconductor testing fixture comprises the steps that a substrate is provided; a plurality of testing pins are formed on the base in a mutually separated mode; a fixing layer is formed on the substrate, wherein the space between every two adjacent testing pins is filled with the fixing layer, and the fixing layer covers the surface of a part of the side wall of each testing pin. According to the method for forming the semiconductor testing fixture, through forming of the fixing layer, the mechanical strength of the testing pins is improved through the fixing layer, and the fixing layer can disperse the stress borne by the testing pins when the testing pins are in contact with a tested terminal and prevent the testing pins from deforming or from disengaging from the surface of the substrate during tests.
Description
Technical field
The present invention relates to semiconductor test technical field, particularly a kind of formation method of semiconductor test tool.
Background technology
Test processing procedure is after IC encapsulation, the electrical functionality of the product that test package completes, to ensure IC integrality functionally of dispatching from the factory, and does to classify according to its electrical functionality to the product tested, as the Appreciation gist of IC different brackets product, last and visual inspection operation is done to product.
Electrical functionality test is carry out testing to determine the normal operation of product energy for the various electrical parameters of product.
On traditional same tested terminal, the test of two-point contact is as Kelvin's test etc., the mode adopting Double ejection pin or the distribution of two golden finger parallel side-by-side more, and it mainly has the following disadvantages:
1, the accuracy of manufacture is lower: along with constantly reducing of semiconductor product size, spacing between the size of tested terminal and different tested terminal is also constantly reducing, in order to comply with this trend, Conventional parallel the Double ejection pin of column distribution or two golden finger test mode bottleneck in the problem of its close spacing become increasingly conspicuous, required precision is more and more higher, and some cannot achieve even.
2, structural strength is more weak: in order to realize two-point contact test in space limited on tested terminal, thimble or golden finger corresponding more and more thinner, its Mechanical Structure Strength is also more and more weak.
3, useful life is shorter: the test contact head of traditional thimble or golden finger is more frayed, especially precision propose requirements at the higher level, mechanical strength relatively low time, the degree of wear is larger, and then reduces the useful life of measurement jig.
4, measuring accuracy is lower: for complying with the compact growth requirement of semiconductor, the resistance value that more and more thinner thimble or golden finger produce constantly increases, and simultaneously when carrying out high-current test, can produce larger pressure drop and affecting the judgement of test number; On the other hand, the Double ejection pin of parallel side-by-side distribution or the also easy deviation producing test number because of offset deviation between the two of two golden finger; In addition, the Double ejection pin of traditional also column distribution adopts two back to the way of contact on inclined-plane in order to the distance reduced between two pins, and contact head easily rotates tested terminal because of the torsion of telescopic spring in its overall structure and then affects measuring accuracy.
Summary of the invention
The problem that the present invention solves how to improve the precision and stability of existing electrical performance testing.
For solving the problem, the invention provides a kind of formation method of semiconductor test tool, comprising: substrate is provided; Form some some test syringe needles be separated from each other on the substrate; Fixed bed on the substrate, the space between adjacent test syringe needle filled by described fixed bed and the partial sidewall of coverage test syringe needle is surperficial.
Optionally, described test syringe needle is single metal needle.
Optionally, the formation method of described test syringe needle is: in substrate, form metal level; Etch described metal level and form some test syringe needles; Form the dielectric layer covering described substrate and test syringe needle, return the dielectric layer that etching removes segment thickness, in substrate, remaining dielectric layer is as fixed bed.
Optionally, form dielectric layer on the substrate, there are in described dielectric layer the some through holes exposing substrate surface; In described through hole, fill metal form some test syringe needles; Return the dielectric layer that etching removes segment thickness, in substrate, remaining dielectric layer is as fixed bed.
Optionally, described test syringe needle is for coaxially to test syringe needle, and described coaxial test syringe needle comprises the first testing needle, and described first testing needle comprises the first noumenon, is positioned at first test lead of the first noumenon one end and is positioned at the first link of the first noumenon other end; Cover the insulating barrier on the first noumenon surface of described first testing needle; Be positioned at second testing needle of surface of insulating layer around described first testing needle, second testing needle is coaxial with the first testing needle, second testing needle comprises the second body, is positioned at second test lead of second body one end and is positioned at the second link of the second body other end, and described second test lead surface flushes with the first test lead surface.
Optionally, the forming process of described first testing needle is: form the first metal layer on the substrate; Etch described the first metal layer and form some first testing needles.
Optionally, the forming process of described first testing needle is: form sacrifice layer on the substrate, has the some through holes exposing substrate surface in described sacrifice layer; In described through hole, fill full metal, form some first testing needles; Remove described sacrifice layer.
Optionally, the forming process of described insulating barrier and the second testing needle is: form the insulating thin layer covering each first testing needle sidewall and top surface; Etch described insulating thin layer without mask etching technique and form insulating barrier at the sidewall of the first testing needle; Form the second metal level covering described insulating barrier and the first testing needle top surface; Without the second metal level described in mask etching, form the second testing needle at surface of insulating layer.
Optionally, the forming process of described first probe, insulating barrier, the second probe and fixed bed is: form dielectric layer on the substrate, be formed with some first through holes and the annular through-hole around each first through hole in described dielectric layer, isolated by part dielectric layer between the first through hole and annular through-hole; In the first through hole, fill metal form the first testing needle, in annular through-hole, fill metal form the second testing needle; Remove the dielectric layer of the segment thickness outside the second testing needle, between the first testing needle and the second testing needle, remaining dielectric layer is as insulating barrier, and in the substrate between test syringe needle, remaining dielectric layer is as fixed bed.
Optionally, signal circuit is formed in described substrate, described signal circuit comprises first input end, the first output, the second input and the second output, described first output is electrically connected with the first link of the first testing needle, described second output is electrically connected with the second link of the second testing needle, and described first input end and the second input are electrically connected with the test circuit of outside respectively.
Compared with prior art, technical scheme of the present invention has the following advantages:
Semiconductor test tool formation method of the present invention, comprising: provide substrate; Form some some test syringe needles be separated from each other on the substrate; Fixed bed on the substrate, the space between adjacent test syringe needle filled by described fixed bed and the partial sidewall of coverage test syringe needle is surperficial.Described fixed bed improves the mechanical strength of test syringe needle, and fixed bed can disperse the stress be subject to when testing syringe needle and tested termination contact, prevents testing needle head from deforming when testing or departs from from substrate surface.
Further, described test syringe needle is for coaxially to test syringe needle, first testing needle and the second testing needle are integrated on a test syringe needle, second testing needle is around described first testing needle, with insulator separation between second testing needle and the first testing needle, thus while ensureing that the size of testing needle is less, promote the mechanical strength of testing needle; On the other hand, the first testing needle and the second testing needle are coaxial distributions, make the precision of spacing between the first testing needle and the second testing needle higher, improve the precision of test; Again on the one hand, need multiple testing needle (such as Double ejection pin or golden finger) just can carry out electrical performance testing compared to prior art, a test syringe needle of the present invention can carry out the test of electric property.
Accompanying drawing explanation
Fig. 1 ~ Fig. 4 is the structural representation of one embodiment of the invention semiconductor test tool;
Fig. 5 ~ Figure 10 is the structural representation of one embodiment of the invention semiconductor test tool forming process;
Figure 11 ~ Figure 14 is the structural representation of another embodiment of the present invention semiconductor test tool forming process;
Figure 15 is the structural representation of another embodiment of the present invention semiconductor test tool;
The structural representation of Figure 16 ~ Figure 17 further embodiment of this invention semiconductor test tool forming process;
The structural representation of Figure 18 ~ Figure 20 yet another embodiment of the invention semiconductor test tool forming process.
Embodiment
As background technology sayed, the performance of existing thimble or golden finger still has much room for improvement.
For this reason, the invention provides a kind of semiconductor test tool, comprising: substrate; Be positioned at some some test syringe needles be separated from each other in substrate; Be positioned at suprabasil fixed bed, described fixed bed fills space between adjacent test syringe needle and second test lead of second body one end, the partial sidewall of coverage test syringe needle surface.Described fixed bed is for improving the mechanical strength of test syringe needle, and fixed bed can disperse the stress be subject to when testing syringe needle and tested termination contact, prevents testing needle head from deforming when testing or departs from from substrate surface.
For enabling above-mentioned purpose of the present invention, feature and advantage more become apparent, and are described in detail specific embodiments of the invention below in conjunction with accompanying drawing.When describing the embodiment of the present invention in detail, for ease of illustrating, schematic diagram can be disobeyed general ratio and be made partial enlargement, and described schematic diagram is example, and it should not limit the scope of the invention at this.In addition, the three-dimensional space of length, width and the degree of depth should be comprised in actual fabrication.
Fig. 1 ~ Fig. 4 is the structural representation of one embodiment of the invention semiconductor test tool; Fig. 5 ~ Figure 10 is the structural representation of one embodiment of the invention semiconductor test tool forming process; Figure 11 ~ Figure 14 is the structural representation of another embodiment of the present invention semiconductor test tool forming process; Figure 15 is the structural representation of another embodiment of the present invention semiconductor test tool; The structural representation of Figure 16 ~ Figure 17 further embodiment of this invention semiconductor test tool forming process; The structural representation of Figure 18 ~ Figure 20 yet another embodiment of the invention semiconductor test tool forming process.
Please refer to Fig. 1, one embodiment of the invention provides a kind of semiconductor test tool, comprising:
Substrate 200;
Be positioned at some test syringe needles 20 be separated from each other in substrate 200;
Be positioned at the fixed bed 210 in substrate 200, the space between adjacent test syringe needle filled by described fixed bed 210 and the partial sidewall of coverage test syringe needle 20 is surperficial.
In the present embodiment, described test syringe needle 20, for coaxially to test syringe needle, please refer to Fig. 2, and Fig. 2 is the structure for amplifying schematic diagram of a test syringe needle in Fig. 1, and described test syringe needle 20 comprises:
First testing needle 201, described first testing needle 201 comprises the first noumenon, is positioned at first test lead 21 of the first noumenon one end and is positioned at the first link 22 of the first noumenon other end;
Cover the insulating barrier 202 on the first noumenon surface of described first testing needle 201;
Be positioned at second testing needle 203 of insulating barrier 202 surface around described first testing needle 201, second testing needle 203 is coaxial with the first testing needle 201, second testing needle 203 comprises the second body, is positioned at second test lead 23 of second body one end and is positioned at the second link 24 of the second body other end, and described second test lead 23 surface flushes with the first test lead 31 surface.
Incorporated by reference to referring to figs. 2 and 3, Fig. 3 is the cross-sectional view of Fig. 2 along hatching AB direction, the shape of described first testing needle 201 is cylinder, the section shape of corresponding first testing needle 201 is circular, the section shape of described insulating barrier 202 is annular, and the section shape of described second testing needle 203 is annular.It should be noted that, the section shape of described first testing needle can be other shape, and such as the section shape of described first testing needle can be regular polygon, such as equilateral triangle, square.
Test syringe needle of the present invention is formed by semiconductor integration making technology, and the diameter of the first testing needle 201 thus formed can be less, and in one embodiment, the diameter of described first testing needle 201 is 100 nanometer ~ 500 micron, can be 200 nanometer ~ 50 micron.
The width of corresponding described insulating barrier 202 and the width of the second testing needle 203 also can be very little, in one embodiment, the width of described insulating barrier 202 is 80 nanometer ~ 400 micron, can be 100 nanometer ~ 10 micron, the width of described second testing needle 203 is 60 nanometer ~ 300 micron, can be 90 nanometer ~ 25 micron.
It should be noted that, in other embodiments of the invention, according to the needs of test, the thickness of the described diameter of the first testing needle 201, the thickness of insulating barrier 202 and the 3rd testing needle 203 can be other suitable numerical value.
The material of described first testing needle 201 and the second testing needle 203 is copper, gold, tungsten or alloy material or other suitable metal material or metal compound material.
Described insulating barrier 202 is for the electric isolation between the first testing needle 201 and the second testing needle 203, in the present embodiment, the top surface of described insulating barrier 202 flushes with the top surface (the second test lead 23) of the top surface (the first test lead 21) of the first testing needle 201 and the second testing needle 203, namely make there is no space between the first test lead 21 of the first testing needle 201 and the second test lead 23 of the second testing needle 203, when testing, prevent the second test lead 23 of the first test lead 21 of the first testing needle 201 or the second testing needle 203 thus between there is gap and deform under the effect of stress of outside, and make the first test lead 21 of the first testing needle 201 and the second test lead 23 electrical contact of the second testing needle 203, thus the precision of impact test.
Described insulating barrier 202 can be single or multiple lift (>=2 layers) stacked structure.
The material of described insulating barrier 202 can be insulating dielectric materials, one or more in such as silica, silicon nitride, silicon oxynitride, fire sand, fire sand, the material of described insulating barrier can also be resin material, such as, epoxy resin, polyimide resin, polyvinyl resin, benzocyclobutane olefine resin or polybenzoxazoles resin.
From the direction pointing to the second test lead 23 away from the second test lead 23, the width of the part body of described second testing needle 203 reduces gradually.Specifically please refer to Fig. 1, the width of the part body of described second testing needle 203, less the closer to second its width of test lead 23, when by how being used for testing with testing needle 20, the distance between the test lead of adjacent test syringe needle 20 is increased.
Please continue to refer to Fig. 1, described substrate 200 also has fixed bed 210, the surface of described fixed bed 210 is lower than the top surface testing syringe needle 20, and described fixed bed 210 covers the partial sidewall surface of described test syringe needle 20, described fixed bed 210 is for improving the mechanical strength of test syringe needle 20, fixed bed 210 can disperse to test syringe needle 20 and the stress be subject to during tested termination contact, prevents test syringe needle 20 from deforming or depart from from substrate 200 surface when testing.
The material of described fixed bed 210 is silica, silicon nitride, silicon oxynitride, fire sand, fire sand or resin or other suitable materials.
The thickness of described fixed bed 210 can be 1/4 ~ 2/3 of testing needle 20 height.
Test syringe needle 20 of the present invention is applied in carry out electrical performance testing time, in one embodiment, test syringe needle of the present invention can be applied to resistance test or high-current test, by one end of test syringe needle 20 and tested termination contact, make the surface contact of the first test lead 21 of the first testing needle 201 and the second test lead 23 surface of the second testing needle 203 and tested terminal, and test voltage is applied between the first testing needle 201 and the second testing needle 202, measure by the first testing needle 201, second testing needle 203, and the electric current on tested terminal, and obtain test resistance by test voltage divided by electric current.
In one embodiment, apply test syringe needle 20 of the present invention when carrying out the test of resistance, because the first testing needle 201 and the second testing needle 203 are coaxial, thus measuring current is spread to surrounding uniformly by the first testing needle 201, flow to the second testing needle 203, namely the electric current making the upper different directions of the annular region (part contacted with insulating barrier 202) of the tested terminal between the first testing needle 201 and the second testing needle 203 flow through is average, improves the precision of test.
In other embodiments of the invention, test syringe needle of the present invention can be applied to other forms of electrical performance testing, such as can apply the test that multiple test syringe needle carries out electric property, such as measuring current can flow to the first testing needle or second testing needle of another test syringe needle from the first testing needle of a test syringe needle or the second testing needle, or test circuit can flow to the first testing needle and second testing needle of another test syringe needle from the second testing needle of a test syringe needle and the second testing needle.
The quantity of described test syringe needle 20 is more than or equal to two, in a specific embodiment, and the arrangement in ranks on a substrate 200 of described test syringe needle 20.
Signal circuit is formed in described substrate 200, described signal circuit comprises first input end, the first output, the second input and the second output, described first output is electrically connected with the first link of the first testing needle 201, described second output is electrically connected with the second link of the second testing needle 203, and described first input end and the second input are electrically connected with the test circuit of outside respectively.Described test circuit is used for providing test signal, the test signal that described signal circuit is used for test circuit produces transfers to the first testing needle 201 and the second testing needle 203, and by the electric signal transmission that obtains in test process to test circuit, test circuit processes the signal of telecommunication received, and obtains test parameter.
The material PCB resin etc. of described substrate 200, described first input end and the first output are by being positioned at intrabasement first metal wire electrical connection, and described second input and the second output are by being positioned at intrabasement second metal wire electrical connection.
In one embodiment, described substrate 200 comprises front and the back side with vis-a-vis, the back side of described substrate comprises interface area, some first outputs and the second output are positioned at the front of substrate 200, corresponding with the position of the first testing needle and the second testing needle, some first input ends and the second input can concentrate on the interface area at substrate 200 back side, some first input ends can be connected with the test circuit of outside by one or more interface with the second input, simplify the interface circuit between semiconductor test tool and the test circuit of outside.In a specific embodiment, described substrate 200 can be formed by the pressing of multi-layer PCB resin substrate, every one deck PCB resin substrate includes some interconnection structures, each interconnection structure comprises the through-hole interconnection structure that runs through this PCB resin substrate and is positioned at the metal level that PCB resin substrate is connected with through-hole interconnection structure on the surface, during the pressing of multi-layer PCB resin substrate, multiple interconnection structure is electrically connected to form the first metal wire or the second metal wire, thus makes some first input ends and the second input can concentrate on the interface area at substrate 200 back side.
In another embodiment, described substrate 200 comprises front and the back side with vis-a-vis, the back side of described substrate comprises interface area, some first outputs and the second output are positioned at the front of substrate 200, some first input ends and the second input are positioned at the back side of substrate 200, the the first through-hole interconnection structure and the second through-hole interconnection structure that run through substrate 200 can be formed in described substrate 200, described first input end and the first output are by being positioned at the first through-hole interconnection structure electrical connection of substrate 200, described second input and the second output are by being positioned at the second through-hole interconnection structure electrical connection of substrate 200, the back side of described substrate 200 also has the some first interconnection metal layer and second interconnection metal layer more again, one end of described first interconnection metal layer again is electrically connected with first input end, the other end of the first interconnection metal layer is again positioned at interface area, one end of described second interconnection metal layer again is electrically connected with the second input, the other end of the described second interconnection metal layer is again positioned at interface area, first in interface area again interconnection metal layer with second again interconnection metal layer be connected with the test circuit of outside by one or more interface.
In other embodiments, test circuit (not shown) can be formed with in described substrate 200, described test circuit comprises the first signal end and secondary signal end, first signal end is electrically connected with the first link of the first testing needle 201, and secondary signal end is electrically connected with the second link of the second testing needle 203.Described test circuit is when testing, test signal (such as voltage signal or current signal) is applied to the first testing needle 201 and the second testing needle 203, and process acquisition test parameter (such as resistance etc.) is carried out to the signal of telecommunication (such as current signal etc.) obtained.
With reference to figure 4, Fig. 4 be semiconductor test tool of the present invention for structural representation during electrical performance testing, first semiconductor test tool is placed in tester table; Then encapsulating structure 300 to be tested is placed on semiconductor test tool, described encapsulating structure to be tested 300 have some tested terminals 31, described tested terminal 31 can be pad or the pin of encapsulating structure 300 to be tested, and the part surface of described tested terminal 31 is electrically connected with the test lead (test lead is the first test lead of the first testing needle 201 and the second test lead of the second testing needle 203) of corresponding test syringe needle 20; Then between the first testing needle 201 and the second testing needle 203, apply test signal, carry out the test of electric property.
Electrical performance testing can be carried out to the multiple tested terminal of encapsulating structure 300 by semiconductor test tool of the present invention simultaneously, improve the efficiency of test and the accuracy of test.
It should be noted that, semiconductor test tool of the present invention can be applied to manual test (artificial loading encapsulating structure to be tested) also can be applied to automatic test (mechanical hand loads encapsulating structure to be tested automatically).
The embodiment of the present invention additionally provides a kind of method forming aforesaid semiconductor measurement jig, specifically please refer to Fig. 5 ~ Figure 10.
Please refer to Fig. 5, substrate 200 is provided; Described substrate 200 is formed some first testing needles 201.
Described first testing needle 201 is cylinder, the section shape that first testing needle 201 obtains along the direction being parallel to substrate 200 surface is for circular, the diameter of described first testing needle 201 is 500 nanometer ~ 500 micron, the quantity of the first testing needle 201 that described substrate 200 is formed is more than or equal to 2, in the present embodiment, to form 3 the first testing needles 201 on a substrate 200 exemplarily.
It should be noted that, the section shape of described first testing needle can be other shape, and such as the shape of described first testing needle is regular polygon, such as equilateral triangle, square.
In one embodiment, the forming process of described first testing needle 201 is: in described substrate 200, form the first metal layer (not shown); Form patterned mask layer on the first metal layer; With described patterned mask layer for mask, etch described the first metal layer and form some first testing needles 201; Remove described patterned mask layer.
In another embodiment, the forming process of described first testing needle 201 is: in described substrate 200, form sacrifice layer (not shown), has the some through holes exposing substrate 200 surface in described sacrifice layer; In described through hole, fill full the first metal layer, form some first testing needles; Remove described sacrifice layer.
The technique of filling the first metal layer in described through hole is electroplating technology, before filling the first metal layer in through-holes, also comprises: form conductive layer at the sidewall of described through hole and the surface of bottom and sacrifice layer, described conductive layer is as negative electrode during electroplating technology.
The material of described conductive layer is one or more in Ti, Ta, TiN, TaN etc., and conductive layer can be single or multiple lift (>=2 layers) stacked structure.
In one embodiment, described conductive layer can be double stacked structure, and the conductive layer of described double stacked structure comprises Ti layer and is positioned at the TiN layer on Ti layer, or comprises Ta layer and be positioned at TaN layer on Ta layer.
The thickness of described conductive layer is less than the radius of through hole, and in one embodiment, the thickness of described conductive layer is 50 ~ 200 nanometers, and the formation process of conductive layer is sputtering.
After formation conductive layer, carry out electroplating technology, form the first metal layer layer, described the first metal layer to be positioned on conductive layer and filling vias, after carrying out electroplating technology, also comprise: carry out chemical mechanical milling tech, remove the first metal layer and the conductive layer of sacrificial layer surface, form the first testing needle 201, first testing needle 201 comprises the first metal layer and surrounds the non-proliferation barrier layer of described the first metal layer, described non-proliferation barrier layer is made up of conductive layer remaining after cmp, spread in the insulating barrier of follow-up formation for preventing the metal in metal level.
The material of described the first metal layer is copper, gold, tungsten or alloy material or other suitable metal materials.
Described first testing needle 201 is the first link with the surface (lower surface) of substrate 200 surface contact, and the surface (top surface) relative with the first link of the first testing needle 201 is the first test lead.
Signal circuit is formed in described substrate 200, described signal circuit comprises first input end, the first output, the second input and the second output, described first output is electrically connected with the first link of the first testing needle 201, described second output is electrically connected with the second link of the second testing needle 203, and described first input end and the second input are electrically connected with the test circuit of outside respectively.Described test circuit is used for providing test signal, the test signal that described signal circuit is used for test circuit produces transfers to the first testing needle 201 and the second testing needle 203, and by the electric signal transmission that obtains in test process to test circuit, test circuit processes the signal of telecommunication received, and obtains test parameter.
The material PCB resin etc. of described substrate 200, described first input end and the first output are by being positioned at intrabasement first metal wire electrical connection, and described second input and the second output are by being positioned at intrabasement second metal wire electrical connection.
In one embodiment, described substrate 200 comprises front and the back side with vis-a-vis, the back side of described substrate comprises interface area, some first outputs and the second output are positioned at the front of substrate 200, corresponding with the position of the first testing needle and the second testing needle, some first input ends and the second input can concentrate on the interface area at substrate 200 back side, some first input ends can be connected with the test circuit of outside by one or more interface with the second input, simplify the interface circuit between semiconductor test tool and the test circuit of outside.In a specific embodiment, described substrate 200 can be formed by the pressing of multi-layer PCB resin substrate, every one deck PCB resin substrate includes some interconnection structures, each interconnection structure comprises the through-hole interconnection structure that runs through this PCB resin substrate and is positioned at the metal level that PCB resin substrate is connected with through-hole interconnection structure on the surface, during the pressing of multi-layer PCB resin substrate, multiple interconnection structure is electrically connected to form the first metal wire or the second metal wire, thus makes some first input ends and the second input can concentrate on the interface area at substrate 200 back side.
In another embodiment, described substrate 200 comprises front and the back side with vis-a-vis, the back side of described substrate comprises interface area, some first outputs and the second output are positioned at the front of substrate 200, some first input ends and the second input are positioned at the back side of substrate 200, the the first through-hole interconnection structure and the second through-hole interconnection structure that run through substrate 200 can be formed in described substrate 200, described first input end and the first output are by being positioned at the first through-hole interconnection structure electrical connection of substrate 200, described second input and the second output are by being positioned at the second through-hole interconnection structure electrical connection of substrate 200, the back side of described substrate 200 also has the some first interconnection metal layer and second interconnection metal layer more again, one end of described first interconnection metal layer again is electrically connected with first input end, the other end of the first interconnection metal layer is again positioned at interface area, one end of described second interconnection metal layer again is electrically connected with the second input, the other end of the described second interconnection metal layer is again positioned at interface area, first in interface area again interconnection metal layer with second again interconnection metal layer be connected with the test circuit of outside by one or more interface.
In other embodiments, test circuit (not shown) can be formed with in described substrate 200, described test circuit comprises the first signal end and secondary signal end, first signal end is electrically connected with the first link of the first testing needle 201, and secondary signal end is electrically connected with the second link of the second testing needle 203.Described test circuit is when testing, test signal (such as voltage signal or current signal) is applied to the first testing needle 201 and the second testing needle 203, and process acquisition test parameter (such as resistance etc.) is carried out to the signal of telecommunication (such as current signal etc.) obtained.In one embodiment, the dielectric layer that described substrate 200 comprises Semiconductor substrate (such as silicon substrate or substrate etc.) and is positioned in Semiconductor substrate, described Semiconductor substrate is formed with semiconductor device (such as transistor etc.), metal interconnecting wires and passive device (such as resistance, electric capacity etc.) is formed in described dielectric layer, semiconductor device and passive device are connected and composed test circuit by described metal interconnecting wires, and the first signal end and secondary signal end can by being arranged in the first metal wire that dielectric layer is electrically connected with test circuit and the second metal wire is drawn.
In conjunction with reference to figure 6 and Fig. 7, the sidewall of each first testing needle 201 forms insulating barrier 202.
The forming process of described insulating barrier 202 is: form the insulating thin layer 204 covering each first testing needle 201 sidewall and top surface; Etch described insulating thin layer 204 without mask etching technique and form insulating barrier 202 at the sidewall of the first testing needle 201.
The thickness of described insulating barrier 202 is 80 nanometer ~ 400 micron, and the material of described insulating barrier 202 can be insulating dielectric materials, one or more in such as silica, silicon nitride, silicon oxynitride, fire sand, fire sand.
Described insulating barrier 202 can be single or multiple lift (>=2 layers) stacked structure.
Described is anisotropic plasma etching industrial without mask etching technique, and in one embodiment, the etching gas that described plasma etching industrial adopts is fluorine-containing and gas that is carbon, is specifically as follows CF
4, C
2f
6, C
4f
8, CHF
3, CH
2f
2in one or more, source power is 500 ~ 1000W, and bias power is 0 ~ 100W, and etch chamber pressure is 2 ~ 500mtorr.
In the present embodiment, described insulating barrier 202 is the silicon oxide layer of individual layer,
In other embodiments of the invention, the material of described insulating barrier 202 can also be resin material, and described resin material can be epoxy resin, polyimide resin, polyvinyl resin, benzocyclobutane olefine resin or polybenzoxazoles resin.
The formation process of described insulating barrier 202 is screen printing technique etc.
In conjunction with reference to figure 8 and Fig. 9, form the second testing needle 203 on the surface of insulating barrier 202, described second testing needle 203 is around corresponding first testing needle 201.
The forming process of described second testing needle 203 is: form the second metal level 205 covering described insulating barrier 202 and the first testing needle 201 top surface; Without the second metal level 205 described in mask etching, form the second testing needle 203 on insulating barrier 202 surface.
The formation process of described second metal level 205 is sputtering, and the second metal level 205 material is copper, gold, tungsten or alloy material or other suitable metal materials, and the thickness of the second metal level 205 is 60 nanometer ~ 300 micron.
Be anisotropic plasma etching industrial without the technique of the second metal level 205 described in mask etching, in one embodiment, the etching gas that described plasma etching industrial adopts is SF
6, NF
3, Cl
2, one or more in HBr, source power is 500 ~ 1500W, and bias power is 0 ~ 100W, and etch chamber pressure is 10 ~ 500mtorr.
Each first testing needle 201 forms one with corresponding insulating barrier 202 and the second testing needle 203 and tests syringe needle 20.
Please refer to Figure 10, described substrate 200 forms fixed bed 210, the space between adjacent test syringe needle 20 filled by described fixed bed 210 and the partial sidewall of coverage test syringe needle 20 is surperficial.
The forming process of described fixed bed 210 is: form the fid bed of material covering described substrate 200 and test syringe needle 20 surface; Return the described fid bed of material of etching, form fixed bed 210.
Before returning the etching fid bed of material, also comprise step: flatening process is carried out to the described fid bed of material, such as chemical mechanical milling tech, expose the top surface of test syringe needle 20; Then return the fid bed of material after etching planarization, form fixed bed 210.
In one embodiment, before returning the described fid bed of material of etching, mask layer can be formed on the top surface of described test syringe needle 20, described mask layer is when returning the etching fid bed of material, prevent the damage that syringe needle is etched, after formation fixed bed 210, remove described mask layer.
In another embodiment, before the etching fid bed of material, if when not forming mask layer on test syringe needle 20, then the material of described fixed bed 210 is not identical with the material of insulating barrier 202, when making the etching fid bed of material, insulating barrier 202 can not be etched or etch rate very low, ensure the integrality of insulating barrier 202.
The material of described fixed bed 210 is silica, silicon nitride, silicon oxynitride, fire sand, fire sand or resin or other suitable materials.
The thickness of described fixed bed 210 can be 1/4 ~ 2/3 of testing needle 20 height.
Another embodiment of the present invention additionally provides a kind of method forming aforesaid semiconductor test tool, specifically please refer to Figure 11 ~ Figure 14.
Please refer to Figure 11, substrate 200 is provided; Described substrate 200 forms dielectric layer 207, states in dielectric layer 207 and be formed with some first through holes 208 and isolated by part dielectric layer around between annular through-hole 209, first through hole 208 of each first through hole 208 and annular through-hole 209.
Described first through hole 208 and annular through-hole 209 expose the surface of substrate 200, and in described first through hole 208, follow-up filling metal forms the first testing needle, and in described second through hole, follow-up filling metal forms the second testing needle.
Be formed with signal circuit or test circuit in described substrate 200, describe about signal circuit or test circuit and please refer to previous embodiment, do not repeat them here.
With reference to Figure 12, Figure 12 is the plan structure schematic diagram of part-structure in Figure 11, and described first through hole 208 is circular, and annular through-hole 209 is annular, annular through-hole 209 is isolated by part dielectric layer material around between described first through hole 208, first through hole 208 and annular through-hole 209.
In other embodiments of the invention, the shape of described first through hole can be other shape, can be such as regular polygon, be specifically as follows equilateral triangle, square etc.
In one embodiment, the material of described dielectric layer 207 is insulating dielectric materials, one or more in such as silica, silicon nitride, silicon oxynitride, fire sand, fire sand, dielectric layer 207 is formed on a substrate 200 by chemical gaseous phase deposition technique, then on described dielectric layer 207, patterned photoresist layer is formed, with described patterned photoresist layer for mask, etch described dielectric layer 207, in dielectric layer 207, form some first through holes 208 and the annular through-hole 209 around each first through hole 208; After forming the annular through-hole 209 of the first through hole 208, remove described patterned photoresist layer.
In another embodiment, the material of described dielectric layer 207 is resin glue, described resin glue is epoxide-resin glue, polyimide resin glue, polyvinyl adhesive, benzocyclobutene resin glue or polybenzoxazoles resin glue, forms dielectric layer 207 by dry film process, wet film technique, typography or plastic roll technique in described substrate 200; Then in described dielectric layer, some first through holes 208 and the annular through-hole 209 around each first through hole 208 is formed by exposure and developing process.
With reference to Figure 13, in the first through hole 208 (with reference to Figure 11), fill metal form the first testing needle 201, in annular through-hole 209 (with reference to Figure 11), fill metal form the second testing needle 203.
Described first testing needle 201 and the second testing needle 203 are formed by same processing step.
The technique of filling metal in the first through hole 208 and annular through-hole 209 is electroplating technology, fill metal in the first through hole 208 and annular through-hole 209 before, also comprise: form conductive layer at the sidewall of described first through hole 208 and annular through-hole 209 and the surface of bottom and sacrifice layer, described conductive layer is as negative electrode during electroplating technology.
The material of described conductive layer is one or more in Ti, Ta, TiN, TaN etc., and conductive layer can be single or multiple lift (>=2 layers) stacked structure.
In one embodiment, described conductive layer can be double stacked structure, and the conductive layer of described double stacked structure comprises Ti layer and is positioned at the TiN layer on Ti layer, or comprises Ta layer and be positioned at TaN layer on Ta layer.
The thickness of described conductive layer is less than the less radius value in the radius of the first through hole 208 and the radius of annular through-hole 209, and the formation process of conductive layer is sputtering.
After formation conductive layer, carry out electroplating technology, form metal level, described metal level to be positioned on conductive layer and to fill the first through hole 208 and annular through-hole 209, after carrying out electroplating technology, also comprise: carry out chemical mechanical milling tech, remove metal level and the conductive layer on dielectric layer 207 surface, form the first testing needle 201 and the second testing needle 203, first testing needle 201 and the second testing needle 203 include metal level and surround the non-proliferation barrier layer of described metal level, described non-proliferation barrier layer is that after cmp, remaining conductive layer is formed, spread in the insulating barrier of follow-up formation for preventing the metal in metal level.
The material of described metal level is copper, gold, tungsten or alloy material or other suitable metal materials.
Form by electroplating technology the damage that the first testing needle 201 and the second testing needle 203, first testing needle 201 and the second testing needle 203 can not be etched in the present embodiment simultaneously, make the surface topography of the first testing needle 201 and the second testing needle 203 better.
With reference to Figure 14, remove the segment thickness dielectric layer 207 (with reference to Figure 13) outside the second testing needle 203, between first testing needle 201 and the second testing needle 203, remaining dielectric layer is as insulating barrier 202, in substrate 200 between needle adjacent 20, remaining dielectric layer is as fixed bed 210, the top surface of described fixed bed 210 is lower than the surface testing syringe needle 20, and the partial sidewall of coverage test syringe needle.
Before certain media layer 207 outside removal second testing needle 203, described first testing needle 201 and the second testing needle 203 and the dielectric layer between the first testing needle 201 and the second testing needle 203 form photoresist mask layer; Then with described photoresist for mask, the dielectric layer 207 of the segment thickness outside etching removal second testing needle 203, remaining dielectric layer is as fixed bed 210.
The thickness of institute's fixed bed 210 is 1/4 ~ 2/3 of test syringe needle 20 height.
Dielectric layer 207 technique outside etching removal second testing needle 203 can be wet etching or dry etch process.
In a specific embodiment, when the material of described dielectric layer 207 is silica, the etching solution that wet-etching technology adopts is hydrofluoric acid solution, and the etching gas that dry etching adopts is fluorocarbon gas; When the material of described dielectric layer 207 is silicon nitride, the etching solution that wet-etching technology adopts is phosphoric acid solution, and the etching gas that dry etching adopts is carbon-fluorine-hydrogen compound gas; When the material of described dielectric layer 207 is resin glue, the etching solution that wet-etching technology adopts is sulfuric acid solution, and the etching gas that dry etching adopts is oxygen.
Additionally provide a kind of semiconductor test tool in another embodiment of the present invention, please refer to Figure 15, comprising:
Substrate 100;
Be positioned at some some test syringe needles 101 be separated from each other in substrate 100;
Be positioned at the fixed bed 102 in substrate 100, the space between adjacent test syringe needle 101 filled by described fixed bed 102 and the partial sidewall of coverage test syringe needle 101 is surperficial.
In the present embodiment, described test syringe needle 101 is single metal needle.
In the present embodiment, described test syringe needle 101 is along being parallel to the section shape of substrate 100 surface direction acquisition for circular, and the diameter of described test syringe needle is 100 nanometer ~ 300 micron.
In other embodiments of the invention, described test syringe needle 101 can be other shape along being parallel to the section shape that substrate 100 surface direction obtains, the section shape of such as described test syringe needle 101 can be regular polygon, such as equilateral triangle, square.
The material of described test syringe needle 101 is copper, gold, tungsten or alloy material or other suitable metal material or metal compound material.
The quantity of test syringe needle 101 is more than or equal to 2.
Described substrate 100 also has fixed bed 102, the surface of described fixed bed 102 is lower than the top surface testing syringe needle 101, and described fixed bed 102 covers the partial sidewall surface of described test syringe needle 101, described fixed bed 102 is for improving the mechanical strength of test syringe needle 101, fixed bed 102 can disperse to test syringe needle 101 and the stress be subject to during tested termination contact, prevents test syringe needle 101 from deforming or depart from from substrate 100 surface when testing.
The material of described fixed bed 102 is silica, silicon nitride, silicon oxynitride, fire sand, fire sand or resin or other suitable materials.
The thickness of described fixed bed 102 can be 1/4 ~ 2/3 of testing needle 101 height.
Be formed with signal circuit in described substrate 100, described signal circuit comprises some inputs and output, and described output is electrically connected with the lower surface of test syringe needle 101, and described input is electrically connected with outside test circuit.Described test circuit is used for providing test signal, described signal circuit is used for the test signal that test circuit produces to transfer to test syringe needle 101, and by the electric signal transmission that obtains in test process to test circuit, test circuit processes the signal of telecommunication received, and obtains test parameter.
The material PCB resin etc. of described substrate 100, described input and output are by being positioned at the electrical connection of intrabasement metal wire.
In one embodiment, described substrate 100 comprises front and the back side with vis-a-vis, the back side of described substrate comprises interface area, some outputs are positioned at the front of substrate 100, corresponding with the position of test syringe needle 101 lower surface, some described inputs concentrate on the interface area at substrate 100 back side, some inputs can be connected with the test circuit of outside by one or more interface, simplify the interface circuit between semiconductor test tool and the test circuit of outside.In a specific embodiment, described substrate 100 can be formed by the pressing of multi-layer PCB resin substrate, every one deck PCB resin substrate includes some interconnection structures, each interconnection structure comprises the through-hole interconnection structure that runs through this PCB resin substrate and is positioned at the metal level that PCB resin substrate is connected with through-hole interconnection structure on the surface, during the pressing of multi-layer PCB resin substrate, multiple interconnection structure is electrically connected to form metal wire, thus belong to line and can bend arrangement, make some outputs concentrate on the interface area at substrate 100 back side.
In another embodiment, described substrate 100 comprises front and the back side with vis-a-vis, the back side of described substrate comprises interface area, some first outputs and the second output are positioned at the front of substrate 100, some first input ends and the second input are positioned at the back side of substrate 100, the the first through-hole interconnection structure and the second through-hole interconnection structure that run through substrate 100 can be formed in described substrate 100, described first input end and the first output are by being positioned at the first through-hole interconnection structure electrical connection of substrate 100, described second input and the second output are by being positioned at the second through-hole interconnection structure electrical connection of substrate 100, the back side of described substrate 100 also has the some first interconnection metal layer and second interconnection metal layer more again, one end of described first interconnection metal layer again is electrically connected with first input end, the other end of the first interconnection metal layer is again positioned at interface area, one end of described second interconnection metal layer again is electrically connected with the second input, the other end of the described second interconnection metal layer is again positioned at interface area, first in interface area again interconnection metal layer with second again interconnection metal layer be connected with the test circuit of outside by one or more interface.
In other embodiments, can be formed with test circuit (not shown) in described substrate 100, described test circuit comprises signal end, and signal end is electrically connected with the lower surface of test syringe needle 101.Described test circuit is when testing, by signal end, test signal (such as voltage signal or current signal) is applied to test syringe needle 101, in test process, obtain the signal of telecommunication (such as current signal etc.), and process acquisition test parameter (such as resistance etc.) is carried out to the signal of telecommunication obtained.
Further embodiment of this invention additionally provides a kind of method forming above-mentioned semiconductor test tool, specifically please refer to Figure 16 ~ Figure 17.
Please refer to Figure 16, substrate 100 is provided; Described substrate 100 forms some test syringe needles 101.
The forming process of described test syringe needle 101 is: in described substrate 100, form metal level (not shown); Form patterned mask layer on the metal layer; With described patterned mask layer for mask, etch described metal level, form some test syringe needles on the substrate.
Signal circuit or test circuit is formed in described substrate 100.About the description of signal circuit or test circuit, please refer to previous embodiment, do not repeat them here.
The material of described metal level is copper, gold, tungsten or alloy material or other suitable metal material or metal compound material, etches described metal level and adopts anisotropic dry etch process.
Please refer to Figure 17, form the dielectric layer covering described substrate 100 and test syringe needle 101, return the dielectric layer that etching removes segment thickness, in substrate, remaining dielectric layer is as fixed bed 102.
The material of described dielectric layer is silica, silicon nitride, silicon oxynitride, fire sand, fire sand or resin or other suitable materials.
The technique of returning the dielectric layer of etching removal segment thickness can be wet-etching technology or dry etch process, and concrete etching technics please refer to the introduction of previous embodiment relevant portion, does not repeat them here.
Further embodiment of this invention additionally provides a kind of method forming above-mentioned semiconductor test tool, specifically please refer to Figure 18 ~ Figure 20.
Please refer to Figure 18, substrate 100 is provided; Described substrate 100 forms dielectric layer 104, there are in described dielectric layer 104 the some through holes 105 exposing substrate 100 surface.
Follow-uply in through hole 105, fill metal, form test syringe needle.
In one embodiment, the material of described dielectric layer 104 is insulating dielectric materials, one or more in such as silica, silicon nitride, silicon oxynitride, fire sand, fire sand, in substrate 100, dielectric layer 104 is formed by chemical gaseous phase deposition technique, then on described dielectric layer 104, patterned photoresist layer is formed, with described patterned photoresist layer for mask, etch described dielectric layer 104, in dielectric layer 104, form some through holes 105; After forming through hole 105, remove described patterned photoresist layer.
In another embodiment, the material of described dielectric layer 104 is resin glue, described resin glue is epoxide-resin glue, polyimide resin glue, polyvinyl adhesive, benzocyclobutene resin glue or polybenzoxazoles resin glue, forms dielectric layer 104 by dry film process, wet film technique, typography or plastic roll technique in described substrate 100; Then in described dielectric layer 104, some through holes 105 are formed by exposure and developing process.
Signal circuit or test circuit is formed in described substrate 100.About the description of signal circuit or test circuit, please refer to previous embodiment, do not repeat them here.
Please refer to Figure 19, in described through hole 105 (with reference to Figure 18), fill metal form test syringe needle 101.
The fill process of described metal is electroplating technology, specifically please refer to the introduction of previous embodiment relevant portion, does not repeat them here.
Please refer to Figure 20, return the dielectric layer 104 (with reference to Figure 19) that etching removes segment thickness, in substrate 100, remaining dielectric layer is as fixed bed 102.
Although the present invention discloses as above, the present invention is not defined in this.Any those skilled in the art, without departing from the spirit and scope of the present invention, all can make various changes or modifications, and therefore protection scope of the present invention should be as the criterion with claim limited range.
Claims (10)
1. a formation method for semiconductor test tool, is characterized in that, comprising:
Substrate is provided;
Form some some test syringe needles be separated from each other on the substrate;
Fixed bed on the substrate, the space between adjacent test syringe needle filled by described fixed bed and the partial sidewall of coverage test syringe needle is surperficial.
2. the formation method of semiconductor test tool as claimed in claim 1, it is characterized in that, described test syringe needle is single metal needle.
3. the formation method of semiconductor test tool as claimed in claim 2, it is characterized in that, the formation method of described test syringe needle is: in substrate, form metal level; Etch described metal level and form some test syringe needles; Form the dielectric layer covering described substrate and test syringe needle, return the dielectric layer that etching removes segment thickness, in substrate, remaining dielectric layer is as fixed bed.
4. the formation method of semiconductor test tool as claimed in claim 2, is characterized in that, form dielectric layer on the substrate to have the some through holes exposing substrate surface in described dielectric layer; In described through hole, fill metal form some test syringe needles; Return the dielectric layer that etching removes segment thickness, in substrate, remaining dielectric layer is as fixed bed.
5. the formation method of semiconductor test tool as claimed in claim 1, it is characterized in that, described test syringe needle is for coaxially to test syringe needle, described coaxial test syringe needle comprises the first testing needle, and described first testing needle comprises the first noumenon, is positioned at first test lead of the first noumenon one end and is positioned at the first link of the first noumenon other end; Cover the insulating barrier on the first noumenon surface of described first testing needle; Be positioned at second testing needle of surface of insulating layer around described first testing needle, second testing needle is coaxial with the first testing needle, second testing needle comprises the second body, is positioned at second test lead of second body one end and is positioned at the second link of the second body other end, and described second test lead surface flushes with the first test lead surface.
6. the formation method of semiconductor test tool as claimed in claim 5, it is characterized in that, the forming process of described first testing needle is: form the first metal layer on the substrate; Etch described the first metal layer and form some first testing needles.
7. the formation method of semiconductor test tool as claimed in claim 5, it is characterized in that, the forming process of described first testing needle is: form sacrifice layer on the substrate, has the some through holes exposing substrate surface in described sacrifice layer; In described through hole, fill full metal, form some first testing needles; Remove described sacrifice layer.
8. the formation method of semiconductor test tool as claimed in claims 6 or 7, it is characterized in that, the forming process of described insulating barrier and the second testing needle is: form the insulating thin layer covering each first testing needle sidewall and top surface; Etch described insulating thin layer without mask etching technique and form insulating barrier at the sidewall of the first testing needle; Form the second metal level covering described insulating barrier and the first testing needle top surface; Without the second metal level described in mask etching, form the second testing needle at surface of insulating layer.
9. the formation method of semiconductor test tool as claimed in claim 5, it is characterized in that, the forming process of described first probe, insulating barrier, the second probe and fixed bed is: form dielectric layer on the substrate, be formed with some first through holes and the annular through-hole around each first through hole in described dielectric layer, isolated by part dielectric layer between the first through hole and annular through-hole; In the first through hole, fill metal form the first testing needle, in annular through-hole, fill metal form the second testing needle; Remove the dielectric layer of the segment thickness outside the second testing needle, between the first testing needle and the second testing needle, remaining dielectric layer is as insulating barrier, and in the substrate between test syringe needle, remaining dielectric layer is as fixed bed.
10. the formation method of semiconductor test tool as claimed in claim 5, it is characterized in that, signal circuit is formed in described substrate, described signal circuit comprises first input end, the first output, the second input and the second output, described first output is electrically connected with the first link of the first testing needle, described second output is electrically connected with the second link of the second testing needle, and described first input end and the second input are electrically connected with the test circuit of outside respectively.
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| CN201410606075.4A CN104319248B (en) | 2014-10-30 | 2014-10-30 | The forming method of semiconductor test gauge |
| US14/927,749 US10006943B2 (en) | 2014-10-30 | 2015-10-30 | Semiconductor testing fixture and fabrication method thereof |
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| CN110726918A (en) * | 2019-09-25 | 2020-01-24 | 苏州韬盛电子科技有限公司 | Semiconductor chip test coaxial socket with impedance matching structure and preparation method thereof |
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| CN101713790A (en) * | 2008-09-29 | 2010-05-26 | 日本电产理德株式会社 | Inspection fixture, electrode of the fixture, method of making the electrode |
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| CN1886821A (en) * | 2003-11-26 | 2006-12-27 | 佛姆法克特股份有限公司 | Methods for making vertical electrical feed through structures |
| US20080074130A1 (en) * | 2006-09-27 | 2008-03-27 | Taiwan Semiconductor Manufacturing Co., Ltd. | Apparatus and method for testing conductive bumps |
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| CN110726918B (en) * | 2019-09-25 | 2022-04-05 | 苏州韬盛电子科技有限公司 | Semiconductor chip test coaxial socket with impedance matching structure and preparation method thereof |
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