CN104298936B - A kind of FPGA encryptions and parameter configuring system based on CPLD chips - Google Patents
A kind of FPGA encryptions and parameter configuring system based on CPLD chips Download PDFInfo
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- CN104298936B CN104298936B CN201410603250.4A CN201410603250A CN104298936B CN 104298936 B CN104298936 B CN 104298936B CN 201410603250 A CN201410603250 A CN 201410603250A CN 104298936 B CN104298936 B CN 104298936B
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- fpga
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F21/00—Security arrangements for protecting computers, components thereof, programs or data against unauthorised activity
- G06F21/70—Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer
- G06F21/71—Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer to assure secure computing or processing of information
- G06F21/72—Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer to assure secure computing or processing of information in cryptographic circuits
Abstract
The present invention relates to fpga logic design field, the encryption of more particularly to a kind of FPGA communication systems and parameter configuring system, refer specifically to a kind of FPGA encryptions based on CPLD chips and parameter configuring system, system is made up of CPU, FPGA and CPLD three parts, and wherein CPLD is responsible for system encryption and systematic parameter configuration；FPGA inside deciphering modules are responsible for system decryption, by enabling FPGA function module, complete FPGA system function start-up and shut-down control；And systemic-function debugging and system upgrade can also be completed by jtag interface or RJ45 interfaces.In the case that the invention realizes that system encryption is safe and reliable, it is few can to take fpga logic resource to client's open F PGA logical codes；And it can complete renewal of the equipment and maintenance management by local upgrade or remote upgrade method, solve the intellectual property protection of CES circuit simulation series of products and parameter configuration problem very well.
Description
Technical field
The present invention relates to fpga logic design field, the encryption of more particularly to a kind of FPGA communication systems and parameter configuration system
System.
Background technology
TDMoIP is the access device that TDM business is carried by IP network, is widely used in 3G/4G transmission networks and accesses
2G business, realize compatibility and the transition of 2G business.CES circuit simulations are TDMoIP device core technologies, because technical difficulty is non-
Chang Gao, the company of the CES core technologies of whole world grasp at present are only several.Research and development company forms TDMoIP in the CES schemes of research and development
During series of products, how to protect core technology very crucial.System core technology is encrypted and is also just particularly important, is led to
Comparative analysis conventional encryption scheme is crossed, the FPGA system encryption for finding to use and method for parameter configuration are protection System core technologies
One of maximally efficient mode.
FPGA (Field Programmable Gate Array) field programmable gate array is the most frequently used complex communication
Circuit system development scheme, CES circuit simulation systems are generally comprised by CPU (Central Processing Unit）Centre
Manage device, SWITCH exchange, FPGA field programmable gate arrays, wherein CPU mainly be responsible for data processing, SWITCH mainly be responsible on
Downlink data exchanges, FPGA is mainly responsible for system logic processing.During system electrification, CPU is read from external memory storage FLASH
FPGA logical code, FPGA is loaded, after FPGA normal loads, system enters normal operating conditions.
And prior art is easy to capture logical code to FPGA loading procedures in CPU, is analyzed and replicated；The opposing party
Face, because CES circuit simulation product line models are more, by E1（A kind of time division multiple frame, speed 2.048Mbit/s）Interface
Point have 6 kinds of E1,2E1,4E1,8E1,16E1,32E1 etc., every kind of E1 divides convergence/do not converge 2 kinds of patterns again, also have system/loopback/
Difference/adaptive 4 kinds of clock types, the maintenance upgrade process for thus causing user encryption in model management and later stage become
It is extremely complex.
At present, FPGA encryption methods mainly have two categories below：
A. the FPGA of carrying encryption function is selected, such as Xilinx Virtex 2-5 series, is calculated using des encryption
Method；Altera Stratix II-III series, using 128 AES advanced encryption algorithms.Both AESs add
Close principle is：Logical code is encrypted when being loaded into Flash, is reduced when being loaded back into FPGA internal SRAMs, third party from
The data of Flash copies are encryption datas, can not be used.This method is simple and convenient, but it is higher to encrypt cost, in general, low
Shelves FPGA does not possess this encryption function.
B.FPGA external special encryption chips, such as U.S. letter DS28E01, after system electrification, DS28E01 can produce one by
The MAC of HASH operation results, i.e., 160 including key, random number, device whole world unique identifier and additional data（Message
Identifying code）, meanwhile, also it can equally carry out comprising key, random number, device recognition number and add with safe storage inside FPGA
HASH including data is calculated, and produces a desired MAC, and then the two MAC are compared in FPGA, if one
Sample, then FPGA think circuit " legal ", now FPGA enters normal operating conditions, and the institute run in FPGA configuration data is active
Energy；If two MAC are inconsistent, FPGA enters abnormal condition, only carries out partial function.This special encryption chip uses state
Border general-purpose algorithm, realize simply, be widely used at present.
But DS28E01 is not suitable for the parameter configuration control of CES circuit simulation series of products, and many times user
Wish control is encrypted to FPGA system work, without checking is encrypted to all runnings, to reduce FPGA
Logic takes, and improves resource utilization ratio, and now existing FPGA cipher modes cannot meet above-mentioned requirements well.
And CPLD (Complex Programmable Logic Device) CPLD, be from PAL and
The large scale integrated circuit that GAL device developments come out, user can construct its logic function as needed, be adapted to complete various
Algorithm and combinational logic circuit.CPLD has E2PROM or FAST FLASH, is not also lost even if programming information during system cut-off
Lose, without external memory chip, using simple.In addition CPLD good confidentialities, cost is low, is suitable for system encryption and parameter
Configuration.
The content of the invention
It is an object of the invention to provide a kind of encryption of FPGA communication systems and parameter configuring system, the present invention to pass through CPLD
Privately owned algorithm for encryption and parameter configuration processing is realized, in the case where system encryption is safe and reliable, can be patrolled to client's open F PGA
Code is collected, client can pass through local upgrade or remote upgrade, updating maintenance equipment control, solve CES circuit simulation series of products
Intellectual property protection and parameter flexible configuration problem.
In order to realize foregoing invention purpose, there is provided following technical scheme：
It is a kind of based on CPLD chips FPGA encryption and parameter configuring system, including external memory modules, CPU module,
FPGA module and CPLD modules, wherein the external memory modules are connected with CPU module, the CPU module is total by address
Line and data/address bus are connected with FPGA module, and the FPGA module is connected by CLK and DATA data/address bus with CPLD modules.
The logical code of the system is stored in external memory modules, and the CPU module will be stored in outer during work
Logical code in portion's memory module is loaded into FPGA module.External memory modules are joined directly together with CPU module, and are led to
Cross CPU the logical code of system is loaded into FPGA, this connected mode can be by CPU in external memory modules
Storage information is updated and upgraded, and facilitates the later maintenance and upgrading of system.
Further, the inside of the FPGA includes deciphering module, and the decryption work of system is completed by deciphering module,
Only need to take seldom logical resource.
Further, enciphering algorithm module and system configuration module are included inside the CPLD；Adding inside the CPLD
Close algoritic module produces deciphering scrambler, the configuration data of system configuration module storage system.
Further, during work, the mutual control planning of intermodule is that the CPU module will be stored in external memory storage
Logical code in module is loaded into FPGA；FPGA inside deciphering module, deciphering scrambler is read from CPLD modules, and
Contrast is decrypted；
If decryption contrast is correct, deciphering module reads the configuration data of system from CPLD, and carries out parameter configuration
With checking；
If matching checking is correct, enabled information is sent by deciphering module, triggering starts each function mould inside FPGA
Block, FPGA enter normal operating conditions.
It is worth noting that, the system logical code is divided into two parts, i.e. FPGA open logical code parts and CPLD
Encryption logic code section, only two part logical codes coordinate, and system could normal work；Seem safety cabinet have key and
As two parts of password, key is changeless, and password can be changed, and key and password all can not individually open guarantor
Dangerous cabinet, only key and password coordinate correctly, and ability opening safety cabinet is the same；FPGA open logical code parts are can to change liter
Level, CPLD encryption logic code sections are not revisable, and only two parts coordinate, system ability normal work, so
Just both solved the flexibility problem of system, and also ensure that the safety issue of system.
Further, the CPU module is also connected with joint test working group jtag interface.
Further, system can be updated external memory modules, be realized and FPGA system is locally risen by JTAG mouths
Level, during upgrading, it is not necessary to CPLD encryption chips are upgraded, such upgrading mode can in order to user model management and
Update, solve the problems, such as the intellectual property protection of CES circuit simulation series of products and parameter flexible configuration.
Preferably, the CPU module is also connected with RJ45 interfaces.
Further, the system can also read upgrade information by IP address, CPU from RJ45, and renewal write-in is outside to deposit
Memory modules, realize to FPGA system remote upgrade, during upgrading, it is not necessary to which CPLD encryption chips are upgraded.
Preferably, cpu chip selects the 88E6218 of MARVELL companies.
Preferably, fpga chip selects Xilinx XC6SLX16-2FT256.
Preferably, CPLD chips select the A3PN015 of ACTEL companies.
Compared with prior art, beneficial effects of the present invention：It is an object of the invention to provide a kind of based on CPLD chips
FPGA is encrypted and parameter configuring system, system are made up of CPU, FPGA, CPLD three parts, and CPLD is responsible for system encryption and system
Parameter configuration；FPGA inside deciphering modules are responsible for system decryption, and the decryption work of system is completed by deciphering module, it is only necessary to
Take seldom logical resource.By enabling the functional module inside FPGA, complete to FPGA system function start-up and shut-down control；CPU
Reading external memory（FLASH）, complete to load FPGA logical code configuration, CPU can also pass through jtag interface and complete system
The local upgrade for function debugging and the system of uniting, CPU also can realize remote upgrade of system etc. by RJ45 interfaces.The present invention is logical
Cross CPLD and realize the privately owned algorithm for encryption of FPGA and parameter configuration processing, can be to client in the case where system encryption is safe and reliable
Open F PGA logical codes, client can solve CES circuits and imitate by local upgrade or remote upgrade, updating maintenance equipment control
True series of products intellectual property protection and parameter flexible configuration problem.
Brief description of the drawings：
Fig. 1 is a kind of FPGA encryptions based on CPLD chips and parameter configuring system structure chart.
Embodiment
With reference to test example and embodiment, the present invention is described in further detail.But this should not be understood
Following embodiment is only limitted to for the scope of the above-mentioned theme of the present invention, it is all that this is belonged to based on the technology that present invention is realized
The scope of invention.
A kind of FPGA encryptions and parameter configuring system based on CPLD chips, as shown in figure 1, including external memory storage mould
Block, CPU module, FPGA module and CPLD modules, wherein the external memory modules are connected with CPU module, the CPU module
It is connected by address bus and data/address bus with FPGA module, the FPGA module passes through CLK and DATA data/address bus and CPLD
Module is connected.
The logical code of the system is stored in external memory modules, and the CPU module will be stored in outer during work
Logical code in portion's memory module is loaded into FPGA module.External memory modules and CPU module be joined directly together without
It is to be connected to be advantageous in that with FPGA, the system data that very easily can be stored by CPU progress external memory modules
Renewal and upgrading, and the logical code of system is loaded into by CPU FPGA this connected mode, CPU pairs can be passed through
Storage information is updated and upgraded in external memory modules, facilitates the later maintenance and upgrading of system.
Further, the inside of the FPGA includes deciphering module, and the decryption work of system is completed by deciphering module,
Only need to take seldom logical resource.
Further, include inside the CPLD, enciphering algorithm module and system configuration module；Adding inside the CPLD
Close algoritic module produces deciphering scrambler, the configuration data of system configuration module storage system.
Further, during work, the mutual control planning of intermodule is that the CPU module will be stored in external memory storage
Logical code in module is loaded into FPGA module；
FPGA inside deciphering module, deciphering scrambler is read from CPLD modules, and contrast is decrypted；
If decryption contrast is correct, deciphering module reads the configuration data of system from CPLD, and carries out parameter configuration
With checking；
If matching checking is correct, enabled information is sent by deciphering module, triggering starts each function mould inside FPGA
Block, FPGA enter normal operating conditions.
Specifically, FPGA inside deciphering module, according to the logical code control command loaded from CPLD modules
Encryption information is read in enciphering algorithm module, and contrast is decrypted.CPLD AES is privately owned algorithm, private using CPLD
After thering is key, CPLD logical code burnings to fix, it is impossible to replicate, confidentiality is high；Can be by each model parameter configuration of CES products
CPLD is write direct, is easy to the differentiation of product type, also allows for product maintenance upgrading, it should be noted that FPGA logical code is not
It can work independently, it must work together with CPLD, it is possible to open F PGA logical codes, without influenceing system safety.
Specifically, the system logical code is divided into two parts, i.e. FPGA open logical code parts and CPLD encryption logic code portions
Point, only two part logical codes coordinate, and system could normal work；Seem that safety cabinet there are two parts one of key and password
Sample, key are changeless, and password can be changed, and key and password all can not individually opening safety cabinets, only key
Coordinate correctly with password, ability opening safety cabinet is the same；FPGA open logical code parts can change upgrading, CPLD encryptions
Logical code part is not revisable, and only two parts coordinate, and system ability normal work, thus both solves system
Flexibility problem, also ensure that the safety issue of system.
If FPGA deciphering module, decryption is correct, then reads system configuration data from CPLD system configuration module,
And carry out the matching checking of configuration data.FPGA configuration data is stored in the system configuration module of CPLD chips, during operation
FPGA parameter configuration and checking procedure is equivalent to secondary decrypting process.
After the completion of FPGA parameter configurations, whether institute's configuration data is correctly verified, configuration passes through if correct
FPGA deciphering module sends enabled information, and triggering starts each functional modules of FPGA, FPGA is entered normal operating conditions.
The system is simply encrypted and configuration verification in start-up course, is no longer demonstrated during normal work, run
Mode is simpler, and it is few to take fpga logic resource.FPGA logical code is loaded by CPU, is easy to system upgrade.
Further, the CPU module is also connected with joint test working group jtag interface.
Further, system can be updated external memory modules, be realized and FPGA system is locally risen by JTAG mouths
Level, during upgrading, it is not necessary to CPLD encryption chips are upgraded, such upgrading mode can in order to user model management and
Update, solve the problems, such as the intellectual property protection of CES circuit simulation series of products and parameter flexible configuration.
Preferably, the CPU module is also connected with RJ45 interfaces.
Further, the system can also read upgrade information by IP address, CPU from RJ45, and renewal write-in is outside to deposit
Memory modules, realize to FPGA system remote upgrade, during upgrading, it is not necessary to which CPLD encryption chips are upgraded.
Preferably, cpu chip selects the 88E6218 of MARVELL companies.
Preferably, fpga chip selects Xilinx XC6SLX16-2FT256.
Preferably, CPLD chips select the A3PN015 of ACTEL companies.
It is an object of the invention to provide a kind of encryption of FPGA communication systems and parameter configuring system, system by CPU,
FPGA, CPLD three parts form, and CPLD is responsible for system encryption and systematic parameter configuration；FPGA inside deciphering modules are responsible for system
Decryption, by enabling FPGA function module, complete FPGA system function start-up and shut-down control；CPU reading external memories FLASH, it is complete
Paired FPGA logical code loading configuration, CPU can also can complete systemic-function debugging and system upgrade by jtag interface,
CPU also can realize remote upgrade of system etc. by RJ45 interfaces.The present invention by CPLD realize the privately owned algorithm for encryption of FPGA and
Parameter configuration processing, can be to client's open F PGA logical codes in the case where system encryption is safe and reliable, and client can pass through this
Ground upgrades or remote upgrade, updating maintenance equipment control, solves the intellectual property protection of CES circuit simulation series of products and parameter spirit
Allocation problem living.
Claims (4)
1. it is a kind of based on CPLD chips FPGA encryption and parameter configuring system, including external memory modules, CPU module,
FPGA module and CPLD modules, it is characterized in that, wherein the external memory modules are connected with CPU module, the CPU module is led to
Cross address bus and data/address bus is connected with FPGA module, the FPGA module passes through CLK and DATA data/address bus and CPLD moulds
Block is connected；
Include enciphering algorithm module and system configuration module inside the CPLD；
Enciphering algorithm module inside the CPLD produces deciphering scrambler, the configuration data of system configuration module storage system；
Wherein, the logical code of the system is stored in external memory modules, and the logical code is disclosed including FPGA and patrolled
Collect code section and CPLD encryption logic code sections；FPGA configuration data is stored in the system configuration module of CPLD chips
In；
The inside of the FPGA includes deciphering module, for according to the logical code control command loaded from CPLD modules
Encryption information is read in enciphering algorithm module, and contrast is decrypted；If decryption contrast is correct, deciphering module is read from CPLD
The configuration data of system is taken, and carries out parameter configuration matching checking；FPGA parameter configurations send enabled information if correct, touch
Hair starts each functional modules of FPGA, FPGA is entered normal operating conditions.
2. a kind of FPGA encryptions and parameter configuring system based on CPLD chips as claimed in claim 1, it is characterized in that, it is described
CPU module is also connected with jtag interface.
3. a kind of FPGA encryptions and parameter configuring system based on CPLD chips as claimed in claim 1, it is characterized in that, it is described
CPU module is also connected with RJ45 interfaces.
4. a kind of FPGA encryptions and parameter configuring system based on CPLD chips as claimed in claim 3, it is characterized in that, CPU
Chip selects the 88E6218 of MARVELL companies；Fpga chip selects Xilinx XC6SLX16-2FT256；CPLD is selected
The A3PN015 of ACTEL companies.
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| TWI579768B (en) * | 2016-01-12 | 2017-04-21 | 英業達股份有限公司 | Updating system of firmware of complex programmable logic device and updating method thereof |
| CN106547716B (en) * | 2016-11-01 | 2019-06-14 | 中国人民解放军国防科学技术大学 | A kind of expansion bus configuration system and method towards low pin number |
| CN108874714A (en) * | 2018-06-06 | 2018-11-23 | 山东超越数控电子股份有限公司 | A kind of secure communication device based on chip |
| CN109284638B (en) * | 2018-09-11 | 2020-08-04 | 网御安全技术（深圳）有限公司 | Protection method and system for operating environment of security chip |
| CN111181917A (en) * | 2019-11-20 | 2020-05-19 | 中国电子科技集团公司第三十研究所 | FPGA safety protection method |
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| CN101673101B (en) * | 2009-09-27 | 2011-06-22 | 电子科技大学 | On-line programming FPGA reconfigurable device |
| CN103593622A (en) * | 2013-11-05 | 2014-02-19 | 浪潮集团有限公司 | FPGA-based design method of safe and trusted computer |
| CN204066120U (en) * | 2014-10-31 | 2014-12-31 | 成都朗锐芯科技发展有限公司 | A kind of FPGA based on CPLD chip encrypts and parameter configuring system |
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| CN101211266A (en) * | 2006-12-30 | 2008-07-02 | 北京天融信网络安全技术有限公司 | FPGA automatic downloading and on-line upgrading process |
| CN101854243A (en) * | 2010-04-30 | 2010-10-06 | 株洲南车时代电气股份有限公司 | Circuit system design encryption circuit and encryption method thereof |
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Denomination of invention: FPGA encryption and parameter configuration system based on CPLD Effective date of registration: 20201222 Granted publication date: 20171208 Pledgee: Bank of Chengdu science and technology branch of Limited by Share Ltd. Pledgor: CHENGDU LONGRAISE TECHNOLOGY DEVELOPMENT Co.,Ltd. Registration number: Y2020980009706 |