CN104298616B - Data block initial method, cache memory and terminal - Google Patents
Data block initial method, cache memory and terminal Download PDFInfo
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- CN104298616B CN104298616B CN201310296274.5A CN201310296274A CN104298616B CN 104298616 B CN104298616 B CN 104298616B CN 201310296274 A CN201310296274 A CN 201310296274A CN 104298616 B CN104298616 B CN 104298616B
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Abstract
The present invention provides a kind of data block initial method, cache memory and terminal.Wherein method includes：The initialization directive that cache memory reception processing device is sent, initialization directive includes the identification information of data block in cache memory to be initiated；Cache memory is initialized according to initialization directive, the data block corresponding to the identification information of data block.So that processor only needs to send an initialization directive to cache memory, it is possible to which realization is initialized to all in data block, so as to improve the performance of processor.
Description
Technical field
The present invention relates to field of computer technology, more particularly to a kind of data block initial method, cache memory
And terminal.
Background technology
In the prior art, it is right when operating system is course allocation internal memory, it is necessary first to determine physics page frame to be allocated
Physics page frame to be allocated is initialized, and the physics page frame after initialization is distributed into process.Processor is according to operating system
Instruction when being initialized to physics page frame to be allocated, it is first that the initial data write-in of physics page frame to be allocated is slow at a high speed
Rush memory（cache）Data block in, data block is initialized, then the data in the data block after initialization are write
Enter in physics page frame to be allocated.
In the prior art, processor uses the store that the value of register is write into internal memory to instruct, and realizes cache number
1 or 0 is initialized to according to all positions in block.But in the prior art, processor needs to send a plurality of store instructions to internal memory,
All positions in cache data block could be initialized to 1 or 0, reduce the performance of processor.
The content of the invention
The present invention provides a kind of data block initial method, cache memory and terminal, for solving prior art
The problem of performance of middle processor is not high.
The first aspect of the invention is to provide a kind of data block initial method, including：
The initialization directive that cache memory reception processing device is sent, the initialization directive includes to be initiated
The identification information of data block in the cache memory；
The cache memory is according to the initialization directive, the data corresponding to the identification information of the data block
Block is initialized.
With reference in a first aspect, in the first feasible embodiment of first aspect, also being wrapped in the initialization directive
Include：The virtual address of first physics page frame to be initiated in internal memory；
Methods described also includes：
The cache memory is according to the virtual address of the first physics page frame in bypass conversion buffered TLB tables
Search the physical address of corresponding first physics page frame；
The physical address of the first physics page frame is write the cache memory by the cache memory
Described in label segment corresponding to identification information.
With reference to the first feasible embodiment of first aspect, in second of feasible embodiment of first aspect
In, the cache memory writes the physical address of the first physics page frame described in the cache memory
After in label segment corresponding to identification information, in addition to：
The cache memory obtains the physical address of the first physics page frame from the label segment；
Data in data block by initialization are write the first physics page frame by the cache memory
In the corresponding internal memory of physical address.
With reference to the feasible embodiment of the first feasible embodiment of first aspect and second, in first aspect
In the third feasible embodiment, the cache memory writes the physical address of the first physics page frame described
Before in label segment corresponding to identification information described in cache memory, if being wrapped in label segment corresponding to the identification information
The physical address of the second physics page frame is included, then methods described also includes：
The cache memory judges the physical address and the second physics page frame of the first physics page frame
Whether physical address is consistent；
If inconsistent, the cache memory is by the corresponding data block of label segment corresponding to the identification information
Data are write in the corresponding internal memory of physical address of the second physics page frame.
With reference in a first aspect, in the 4th kind of feasible embodiment of first aspect, the initialization directive also includes：
Data to be written, all positions of the data to be written are 0 or are 1, and the digit of the data to be written is k, and k is whole more than 0
Number；
Data block corresponding to the identification information to the data block is initialized, including：
Write during the cache memory is every k into data block corresponding to the identification information of the data block described
Data to be written.
With reference in a first aspect, in the 5th kind of feasible embodiment of first aspect, the mark to the data block
Know the corresponding data block of information to be initialized, including：
The cache memory is initialized to the block caching in the cache memory；
Data in block caching after initialization are write number corresponding to the identification information by the cache memory
According to block.
The second aspect of the invention provides a kind of cache memory, including：Processing unit, control logic unit and
Multiple data blocks；
The processing unit, the initialization directive sent for reception processing device, the initialization directive includes treating initial
The identification information of data block in the cache memory changed；
The processing unit, is additionally operable to according to the initialization directive, controls the control logic unit to the data
The data block that the identification information of block is corresponding is initialized.
With reference to second aspect, in the first feasible embodiment of second aspect, the cache memory is also
Including：The identification information of data block corresponding label segment and bypass conversion buffered TLB tables；
Also include in the initialization directive：The virtual address of first physics page frame to be initiated in internal memory；
The processing unit, is additionally operable to be searched in the TLB tables according to the virtual address of the first physics page frame pair
The physical address for the first physics page frame answered；
The processing unit, is additionally operable to the physical address of the first physics page frame writing the cache memory
Described in label segment corresponding to identification information.
With reference to the first feasible embodiment of second aspect, in second of feasible embodiment of second aspect
In, the processing unit is marked the physical address of the first physics page frame is write described in the cache memory
After knowing in the corresponding label segment of information, it is additionally operable to obtain the physical address of the first physics page frame from the label segment；
The processing unit, is additionally operable to, by the data in the data block by initialization, write the first physics page frame
The corresponding internal memory of physical address in.
With reference to the feasible embodiment of the first feasible embodiment of second aspect and second, in second aspect
In the third feasible embodiment, the physical address of the first physics page frame is write the high speed and delayed by the processing unit
Before rushing in label segment corresponding to identification information described in memory, if label segment corresponding to the identification information includes second
The physical address of physics page frame, the processing unit is additionally operable to, and judges the physical address of the first physics page frame and described the
Whether the physical address of two physics page frames is consistent；
If inconsistent, the processing unit is additionally operable to, by the corresponding data block of label segment corresponding to the identification information
Data write in the corresponding internal memory of physical address of the second physics page frame.
With reference to second aspect, in the 4th kind of feasible embodiment of second aspect, the initialization directive also includes：
Data to be written, all positions of the data to be written are 0 or are 1, and the digit of the data to be written is k, and k is whole more than 0
Number；
The processing unit is according to the initialization directive, mark of the control control logic unit to the data block
During the corresponding data block of information is initialized, the processing unit specifically for,
Institute is write in controlling the control logic unit into data block corresponding to the identification information of the data block per k
State data to be written.
With reference to second aspect, in the 5th kind of feasible embodiment of second aspect, the cache memory is also
Including：Block is cached；
The control logic unit to described piece of caching specifically for initializing；
The processing unit is additionally operable to, and the data in the block caching after initialization are write into number corresponding to the identification information
According to block.
The third aspect of the invention provides a kind of terminal, including：Processor and such as in terms of second and second side
Cache memory in five kinds of feasible embodiments in face.
In the present invention, cache memory includes the mark of data block to be initiated by what reception processing device was sent
The initialization directive of information, is initialized according to the data block that initialization directive is corresponding to the identification information of data block so that
Processor is only needed to send an initialization directive to cache memory, it is possible to which realization is entered to all positions in data block
Row initialization, saves the instruction overhead in initialization procedure, improves the performance of processor.
Brief description of the drawings
The flow chart of data block initial method one embodiment that Fig. 1 provides for the present invention；
The flow chart of internal memory initialization method one embodiment based on data initialization block that Fig. 2 provides for the present invention；
The flow for internal memory initialization method another embodiment based on data initialization block that Fig. 3 provides for the present invention
Figure；
The flow for internal memory initialization method another embodiment based on data initialization block that Fig. 4 provides for the present invention
Figure；
Fig. 5 is a kind of circuit diagram of cache memory suitable for the embodiment shown in Fig. 1-4；
Fig. 6 is the form schematic diagram that dcbo is instructed；
The structural representation of cache memory one embodiment that Fig. 7 provides for the present invention；
The structural representation for cache memory another embodiment that Fig. 8 provides for the present invention；
The structural representation of terminal one embodiment that Fig. 9 provides for the present invention.
Embodiment
To make the purpose, technical scheme and advantage of the embodiment of the present invention clearer, below in conjunction with the embodiment of the present invention
In accompanying drawing, the technical scheme in the embodiment of the present invention is clearly and completely described, it is clear that described embodiment is
A part of embodiment of the present invention, rather than whole embodiments.Based on the embodiment in the present invention, those of ordinary skill in the art
The every other embodiment obtained under the premise of creative work is not made, belongs to the scope of protection of the invention.
The flow chart of data block initial method one embodiment that Fig. 1 provides for the present invention, the execution master of following steps
Body can be computer, mobile phone, the cache memory in various types of terminal devices such as PAD.As shown in figure 1, including：
101st, the initialization directive that cache memory reception processing device is sent, initialization directive includes to be initiated
The identification information of data block in cache memory.
Wherein, cache memory（Cache）In have multiple data blocks（DATA）, each data block also correspond to one
Label (TAG).The data that can be stored with corresponding data block in label in internal memory the physical address of physics page frame and
The identification information of data block is specifically as follows the title of the corresponding label of data block, i.e. Cache indexes in other information, the present invention
Number.
102nd, cache memory is according to initialization directive, and the data block corresponding to the identification information of data block is carried out just
Beginningization.
As a kind of feasible embodiment, cache memory can delay to the block in cache memory first
Deposit（block buffer）Initialized, specifically, all positions all sets during can block be cached, or, can also be by
All positions all resets in block caching；Further, cache memory again writes the data in the block caching after initialization
The corresponding data block of inlet identity information.
Optionally, it can further include in initialization directive：Data to be written, all positions of data to be written be 0 or
It is 1, the digit of data to be written is k, and k is the integer more than 0.Then under the implement scene, a kind of feasible embodiment party is used as
Formula, cache memory can write data to be written into every k of data block corresponding to the identification information of data block, due to
All positions of data to be written are 0 or are 1, therefore can realize that the data block corresponding to the identification information of data block is carried out just
Beginningization.
Under the implement scene that initialization directive includes data to be written, another feasible embodiment, high speed are used as
Buffer storage can also be cached to block in every k in write data to be written, data during then block is cached again write-in mark
Know the corresponding data block of information.
It should be further stated that, initialization directive instructs or put 1 instruction to set to 0.And by cache memory
All of data block set to 0 or put 1 instruction, can be applied not only to realize the initialization operation to data block, also
It can apply to other application scene.For example, programmer is during programming, if desired to an array or other data
All positions in structure are all entered as 0 or are entered as 1, and programmer, which can use, sets to 0 or put 1 instruction.In another example, if programmer
Need all positions being all 0 or be all 1 value of page and be assigned to another page, programmer, which can also use, sets to 0 or put 1 finger
Order.
Those skilled in the art can also will set to 0 instruction or put 1 application of instruction in other needs using setting to 0 instruction or put 1
The application scenarios of instruction, are no longer repeated herein.
In the present embodiment, cache memory includes the mark of data block to be initiated by what reception processing device was sent
Know the initialization directive of information, initialized, made according to the data block that initialization directive is corresponding to the identification information of data block
Obtain processor to only need to send an initialization directive to cache memory, it is possible to realize to all positions in data block
Initialized, save the instruction overhead in initialization procedure, improve the performance of processor.
On the basis of embodiment illustrated in fig. 1, in ensureing that the data in the data block after initialization can be written to
In depositing, so as to realize the initialization to internal memory, optionally, it can further include in initialization directive：Treat initial in internal memory
The virtual address for the first physics page frame changed.The internal memory initialization method based on data initialization block that Fig. 2 provides for the present invention
The flow chart of one embodiment, as shown in Fig. 2 can further include after the data block initial method shown in Fig. 1
Following steps：
103rd, cache memory according to the virtual address of the first physics page frame bypass conversion buffered
（Translation look aside buffer, TLB）The physical address of corresponding first physics page frame is searched in table.
Wherein, the virtual address of physics page frame is preserved in TLB tables to the transformational relation of physical address, it is therefore, slow at a high speed
Corresponding first physics can be found according to the virtual address of the first physics page frame carried in initialization directive by rushing memory
The physical address of page frame.
104th, the physical address of the first physics page frame is write to identify in cache memory and believed by cache memory
Cease in corresponding label segment.
Wherein, multiple label segments can be included in the corresponding label of each data block, label segment corresponding to identification information refers to
Be the label segment for being used in multiple label segments preserve the physical address of physics page frame.
It should be noted that cache memory can both perform step 103 and step 104 before step 102；
Step 103 and step 104 can be performed after step 102；Can also perform step 102 while perform step 103 and
Step 104.
Wherein, step 103 is that the first physics page frame is prestored in label segment corresponding to identification information with 104 effect
Physical address, so as to which corresponding internal memory can be searched according to the physical address of the first physics page frame below, by identification information pair
Data in the data block answered are write in the corresponding internal memory of physical address of the first physics page frame, internally deposit into capable initialization.
Further, in order to realize the initialization to internal memory, as shown in figure 3, on the basis of embodiment illustrated in fig. 2, step
After rapid 104, it can also include：
105th, cache memory obtains the physical address of the first physics page frame from label segment.
106th, the data in the data block by initialization are write the physics of the first physics page frame by cache memory
In the corresponding internal memory in address.
In the present embodiment, cache memory includes the mark of data block to be initiated by what reception processing device was sent
Know the initialization directive of information, initialized according to the data block that initialization directive is corresponding to the identification information of data block, and
The virtual address of the first physics page frame to be initiated obtains the first physics page frame in the internal memory included according to initialization directive
Physical address, the physical address of the first physics page frame is write into the corresponding label segment of cache memory identification information
In so that processor only needs to send an initialization directive to cache memory, it is possible to realize in data block
All are initialized, so as to realize the initialization to internal memory, are saved the instruction overhead in initialization procedure, are improved place
Manage the performance of device.
The flow chart for the internal memory initialization method of data initialization block another embodiment that Fig. 4 provides for the present invention, such as
Shown in Fig. 4, on the basis of Fig. 2 or embodiment illustrated in fig. 3, the physical address of the first physics page frame is write at step 104
Before in the corresponding label segment of cache memory identification information, it may be preserved in label segment corresponding to identification information
The physical address of the physical address of other physics page frames, i.e. the second physics page frame, it is necessary to by data block under the implement scene
In data corresponding with the physical address of the second physics page frame write-in internal memory preserved, step 104 is then performed again.Therefore,
It can also include：
107th, cache memory judges the physical address of the first physics page frame and the physical address of the second physics page frame
It is whether consistent.
If the 108, inconsistent, cache memory is by the data in the corresponding data block of label segment corresponding to identification information
Write in the corresponding internal memory of physical address of the second physics page frame.
Fig. 5 provides a kind of circuit diagram for the cache memory for being applied to the embodiment shown in Fig. 1-4, such as schemes
Shown in 5, multiple data blocks can be included in the cache memory（DATA）, one label of each data block correspondence（TAG）,
These data blocks and its corresponding label constitute the caching of cache memory（Cache）.Cache memory is received
The initialization directive sent to processor can be dcbo instructions, and the form schematic diagram of dcbo instructions is as shown in fig. 6, including deposit
Device RA fields and register RB fields.High speed to be initiated can be preserved under the first implement scene, in register RA to delay
The void of the first physics page frame to be initiated in internal memory can be preserved by rushing in the identification information of data block in memory, register RB
Intend address.Under the implement scene that initialization directive includes data to be written, height to be initiated can be preserved in register RA
The virtual address of first physics page frame to be initiated in the identification information and internal memory of data block, register in fast buffer storage
Data to be written can be preserved in RB.Cache memory can pass through control logic unit（SET Control Logic）Come
Perform initialization operation.
In addition, when the digit of the virtual address of the first physics page frame to be initiated in internal memory is more, more than register RB
Maximum number of digits when, the identification information of data block in cache memory to be initiated can be preserved in register RA, with
And in internal memory the virtual address of the first physics page frame to be initiated low portion, can preserve in internal memory in register RB and treat
The high-order portion of the virtual address of first physics page frame of initialization.Cache memory is received after initialization directive, can
So that register RA to be added with the content in register RB, effective address is obtained（Effective Address）, will post
Internal memory in storage RB in the high-order portion and register RA of the virtual address of the first physics page frame to be initiated in internal memory
In the low portion position of virtual address of the first physics page frame to be initiated be placed on the high position of effective address, by register RA
In cache memory to be initiated in the identification information of data block be placed on the low level of effective address, speed buffering is deposited
Reservoir the virtual address of the first physics page frame to be initiated and high speed to be initiated can delay from internal memory is obtained respectively
Rush the identification information of data block in memory.
Under the first implement scene, cache memory can be according to the height to be initiated preserved in register RA
The identification information of data block in fast buffer storage, determines data block corresponding to identification information（DATA）；According in register RB
The virtual frame number of the virtual address, i.e. the first physics page frame of first physics page frame to be initiated in the internal memory of preservation
（Virtual Page Number, VPN）, bypass conversion buffered TLB tables are searched, the physical address of the first physics page frame are obtained, i.e.,
The physics frame number of first physics page frame（Page Frame Number, PFN）, judge to protect in label segment corresponding to identification information
Whether the physical address for the second physics page frame deposited is consistent with the physical address of the first physics page frame, i.e. the thing of the second physics page frame
Whether reason address and the physical address of the first physics page frame hit（Hit）, in the physical address and the first thing of the second physics page frame
In the case that the physical address of reason page frame is consistent, the data in data block corresponding to identification information can be written to block caching
（block buffer）In, after cache memory is initialized to the data in block caching, during can block be cached
Data write in data block corresponding to identification information；In the physical address and the physics of the first physics page frame of the second physics page frame
In the case that address is inconsistent, the data in data block corresponding to identification information can be written to second by cache memory
In the corresponding internal memory of physical address of physics page frame, the physical address of the first physics page frame is then written to identification information correspondence
Label segment in, by after initialization block caching in data be written in data block corresponding to identification information.
When cache memory writes missing, under using cache memory writing allocation policy, processor is not required to
First by data from internal memory reads the data block of cache memory internal memory is write back to after being initialized to data block
In, directly data block can be initialized, and the data of the data block after initialization are written in internal memory, so as to reduce
Processor internally deposits into accessing operation during row initialization, further increasing the performance of processor.
In the present embodiment, cache memory includes the mark of data block to be initiated by what reception processing device was sent
Know the initialization directive of information, initialized according to the data block that initialization directive is corresponding to the identification information of data block, and
The virtual address of the first physics page frame to be initiated obtains the first physics page frame in the internal memory included according to initialization directive
Physical address, judge the second Physical Page preserved in the physical address of the first physics page frame label segment corresponding with identification information
Whether the physical address of frame is consistent, in the case of inconsistencies, by the corresponding data block of label segment corresponding to identification information
Data are write in the corresponding internal memory of physical address of the second physics page frame, then the physical address of the first physics page frame is write at a high speed
In the corresponding label segment of buffer storage identification information so that processor only needs to send at the beginning of one to cache memory
Beginningization is instructed, it is possible to which realization is initialized to all in data block, so as to realize the initialization to internal memory, is saved
Instruction overhead in initialization procedure, improves the performance of processor.
One of ordinary skill in the art will appreciate that：Realizing all or part of step of above-mentioned each method embodiment can lead to
The related hardware of programmed instruction is crossed to complete.Foregoing program can be stored in a computer read/write memory medium.The journey
Sequence upon execution, performs the step of including above-mentioned each method embodiment；And foregoing storage medium includes：ROM, RAM, magnetic disc or
Person's CD etc. is various can be with the medium of store program codes.
The structural representation of cache memory one embodiment that Fig. 7 provides for the present invention, as shown in fig. 7, comprises：
Processing unit 71, control logic unit 72 and multiple data blocks 73；
Processing unit 71, the initialization directive sent for reception processing device, initialization directive includes height to be initiated
The identification information of data block in fast buffer storage；
Processing unit 71, is additionally operable to according to initialization directive, identification information of the control control logic unit 72 to data block
Corresponding data block 73 is initialized.
Further, initialization directive also includes：Data to be written, all positions of data to be written are 0 or are 1, to be written
The digit of data is k, and k is the integer more than 0；
Processing unit 71 is according to initialization directive, and control control logic unit 72 is corresponding to the identification information of data block 73
During data block is initialized, processing unit 71 specifically for,
Number to be written is write during control control logic unit 72 is every k into data block corresponding to the identification information of data block 73
According to.
Yet further, cache memory can also include：Block is cached；
Control logic unit 72 to block caching specifically for initializing；
Processing unit 71 is additionally operable to, and the data in the block caching after initialization are write into data block corresponding to identification information
73。
In the present embodiment, cache memory includes the mark of data block to be initiated by what reception processing device was sent
Know the initialization directive of information, initialized, made according to the data block that initialization directive is corresponding to the identification information of data block
Obtain processor to only need to send an initialization directive to cache memory, it is possible to realize to all positions in data block
Initialized, save the instruction overhead in initialization procedure, improve the performance of processor.
The structural representation for cache memory another embodiment that Fig. 8 provides for the present invention, as shown in figure 8,
On the basis of embodiment illustrated in fig. 7, in addition to：
The identification information of data block corresponding label segment 74 and bypass conversion buffered TLB tables 75；
It can also include in initialization directive：The virtual address of first physics page frame to be initiated in internal memory；
Processing unit 71, is additionally operable to search corresponding first in TLB tables 75 according to the virtual address of the first physics page frame
The physical address of physics page frame；
Processing unit 71, is additionally operable to the physical address of the first physics page frame writing cache memory identification information
In corresponding label segment 74.
Further, processing unit 71, get the bid by the physical address write-in cache memory of the first physics page frame
After knowing in the corresponding label segment of information, it is additionally operable to obtain the physical address of the first physics page frame from label segment 74；
Processing unit 71, is additionally operable to write the data in the data block by initialization the physics of the first physics page frame
In the corresponding internal memory in address.
Further, the physical address of the first physics page frame is write in cache memory and identified by processing unit 71
Before in the corresponding label segment 74 of information, if label segment 74 corresponding to identification information includes the second physics page frame physically
Location, processing unit 71 is additionally operable to, judge the first physics page frame physical address and the second physics page frame physical address whether one
Cause；If inconsistent, processing unit 71 is additionally operable to, and the data in the corresponding data block of label segment 74 corresponding to identification information are write
In the corresponding internal memory of physical address of second physics page frame.
In the present embodiment, cache memory includes the mark of data block to be initiated by what reception processing device was sent
Know the initialization directive of information, initialized according to the data block that initialization directive is corresponding to the identification information of data block, and
The virtual address of the first physics page frame to be initiated obtains the first physics page frame in the internal memory included according to initialization directive
Physical address, the physical address of the first physics page frame is write into the corresponding label segment of cache memory identification information
In so that processor only needs to send an initialization directive to cache memory, it is possible to realize in data block
All are initialized, so as to realize the initialization to internal memory, are saved the instruction overhead in initialization procedure, are improved place
Manage the performance of device.
The structural representation of terminal one embodiment that Fig. 9 provides for the present invention, as shown in figure 9, including：Processor 91 with
And cache memory 92.
The 26S Proteasome Structure and Function of wherein cache memory 92 can be found in the speed buffering in Fig. 7 or embodiment illustrated in fig. 8
The 26S Proteasome Structure and Function of memory, will not be repeated here.
In the present invention, cache memory includes the mark of data block to be initiated by what reception processing device was sent
The initialization directive of information, is initialized according to the data block that initialization directive is corresponding to the identification information of data block so that
Processor is only needed to send an initialization directive to cache memory, it is possible to which realization is entered to all positions in data block
Row initialization, saves the instruction overhead in initialization procedure, improves the performance of processor.
Finally it should be noted that：Various embodiments above is merely illustrative of the technical solution of the present invention, rather than its limitations；To the greatest extent
The present invention is described in detail with reference to foregoing embodiments for pipe, it will be understood by those within the art that：Its according to
The technical scheme described in foregoing embodiments can so be modified, or which part or all technical characteristic are entered
Row equivalent substitution；And these modifications or replacement, the essence of appropriate technical solution is departed from various embodiments of the present invention technology
The scope of scheme.
Claims (9)
1. a kind of data block initial method, it is characterised in that including：
The initialization directive that cache memory reception processing device is sent, the initialization directive includes to be initiated described
The identification information of data block in cache memory；
The cache memory enters according to the initialization directive, the data block corresponding to the identification information of the data block
Row initialization；
Also include in the initialization directive：The virtual address of first physics page frame to be initiated in internal memory；
The cache memory is searched according to the virtual address of the first physics page frame in bypass conversion buffered TLB tables
The physical address of corresponding first physics page frame；
The physical address of the first physics page frame is write institute in the cache memory by the cache memory
State in label segment corresponding to identification information；
The physical address of the first physics page frame is write institute in the cache memory by the cache memory
Before stating in label segment corresponding to identification information, if label segment corresponding to the identification information includes the thing of the second physics page frame
Address is managed, then methods described also includes：
The cache memory judges the physical address of the first physics page frame and the physics of the second physics page frame
Whether address is consistent；
If inconsistent, the cache memory is by the data in the corresponding data block of label segment corresponding to the identification information
Write in the corresponding internal memory of physical address of the second physics page frame.
2. according to the method described in claim 1, it is characterised in that the cache memory is by the first physics page frame
Physical address write in label segment corresponding to identification information described in the cache memory after, in addition to：
The cache memory obtains the physical address of the first physics page frame from the label segment；
Data in data block by initialization are write the physics of the first physics page frame by the cache memory
In the corresponding internal memory in address.
3. according to the method described in claim 1, it is characterised in that the initialization directive also includes：Data to be written, it is described to treat
All positions for writing data are 0 or are 1, and the digit of the data to be written is k, and k is the integer more than 0；
Data block corresponding to the identification information to the data block is initialized, including：
Write during the cache memory is every k into data block corresponding to the identification information of the data block described to be written
Data.
4. according to the method described in claim 1, it is characterised in that data corresponding to the identification information to the data block
Block is initialized, including：
The cache memory is initialized to the block caching in the cache memory；
Data in block caching after initialization are write data block corresponding to the identification information by the cache memory.
5. a kind of cache memory, it is characterised in that including：Processing unit, control logic unit and multiple data blocks；
The processing unit, the initialization directive sent for reception processing device, the initialization directive includes to be initiated
The identification information of data block in the cache memory；
The processing unit, is additionally operable to according to the initialization directive, controls the control logic unit to the data block
Data block corresponding to identification information is initialized；
The identification information of data block corresponding label segment and bypass conversion buffered TLB tables；
Also include in the initialization directive：The virtual address of first physics page frame to be initiated in internal memory；
The processing unit, is additionally operable to be searched in the TLB tables according to the virtual address of the first physics page frame corresponding
The physical address of first physics page frame；
The processing unit, is additionally operable to the physical address of the first physics page frame writing institute in the cache memory
State in label segment corresponding to identification information；
The physical address of the first physics page frame is write and identified described in the cache memory by the processing unit
Before in the corresponding label segment of information, if label segment corresponding to the identification information includes the second physics page frame physically
Location, the processing unit is additionally operable to, and judges the physical address of the first physics page frame and the physics of the second physics page frame
Whether address is consistent；
If inconsistent, the processing unit is additionally operable to, by the number in the corresponding data block of label segment corresponding to the identification information
In the corresponding internal memory of physical address according to write-in the second physics page frame.
6. cache memory according to claim 5, it is characterised in that the processing unit, by described first
After the physical address of physics page frame is write in label segment corresponding to identification information described in the cache memory, also use
In the physical address that the first physics page frame is obtained from the label segment；
The processing unit, is additionally operable to write the data in the data block by initialization the thing of the first physics page frame
Manage in the corresponding internal memory in address.
7. cache memory according to claim 5, it is characterised in that the initialization directive also includes：It is to be written
Data, all positions of the data to be written are 0 or are 1, and the digit of the data to be written is k, and k is the integer more than 0；
The processing unit is according to the initialization directive, identification information of the control control logic unit to the data block
During corresponding data block is initialized, the processing unit specifically for,
Treated in controlling the control logic unit into data block corresponding to the identification information of the data block per k described in write-in
Write data.
8. cache memory according to claim 5, it is characterised in that also include：Block is cached；
The control logic unit to described piece of caching specifically for initializing；
The processing unit is additionally operable to, and the data in the block caching after initialization are write into data corresponding to the identification information
Block.
9. a kind of terminal, it is characterised in that including：Processor and the speed buffering as described in claim any one of 5-8 are deposited
Reservoir.
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| CN1617113A (en) * | 2003-11-13 | 2005-05-18 | 国际商业机器公司 | Method of assigning virtual memory to physical memory, storage controller and computer system |
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