CN104281545B - A kind of method for reading data and equipment - Google Patents
A kind of method for reading data and equipment Download PDFInfo
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- CN104281545B CN104281545B CN201310291218.2A CN201310291218A CN104281545B CN 104281545 B CN104281545 B CN 104281545B CN 201310291218 A CN201310291218 A CN 201310291218A CN 104281545 B CN104281545 B CN 104281545B
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/14—Handling requests for interconnection or transfer
- G06F13/16—Handling requests for interconnection or transfer for access to memory bus
- G06F13/1668—Details of memory controller
- G06F13/1673—Details of memory controller using buffers
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/14—Handling requests for interconnection or transfer
- G06F13/20—Handling requests for interconnection or transfer for access to input/output bus
- G06F13/28—Handling requests for interconnection or transfer for access to input/output bus using burst mode transfer, e.g. direct memory access DMA, cycle steal
- G06F13/282—Cycle stealing DMA
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F2213/00—Indexing scheme relating to interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F2213/28—DMA
- G06F2213/2806—Space or buffer allocation for DMA transfers
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
- Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management
Abstract
The embodiment of the invention discloses a kind of method for reading data and equipment, it is related to computer realm, reduces operation complexity and power consumption in the continuous reading process of mass data.Concrete scheme is：MC will need the row address of the data that read in memory to send to memory, so as to memory by the data storage of row corresponding with row address in memory in the buffering area of memory；MC sends the first order to memory, sends the data for needing to read to MC so that memory travels through all column address according to the first order；, wherein it is desired to which the data read are all data of the row corresponding with row address stored in buffering area, first orders for activating the direct memory access logic in memory；MC receives the data that the needs that memory is sent are read.During the present invention is used for digital independent.
Description
Technical field
The present invention relates to computer realm, more particularly to a kind of method for reading data and equipment.
Background technology
It is well known that computer system is typically by processor, internal memory, input equipment, output equipment and the part group of bus five
Into wherein internal memory is for preserving data and instruction needed for processor operation, dynamic random access memory（Dynamic
Random Access Memory, DRAM）It is the main flow realization of the internal memory of current computer system.
Reading to data in DRAM is typically all to be realized by way of row plus row, specifically, working as Memory Controller Hub
（Memory Controller, MC）Receive central processing unit（Center Processing Unit, CPU）The data of transmission
During access instruction, data access instruction is parsed to obtain row address and row ground of the data for needing to access in DRAM first
Location, row address then is sent to DRAM, to cause DRAM that the row address is corresponded into the data storage of row in row buffer（row
buffer）In, finally column address is sent to DRAM again, such DRAM can be with from row according to the column address received
The data block for choosing needs to read in buffer, and sent by the data wire between DRAM and MC into MC caching, then by
MC sends the data block for needing to read to CPU.It can thus be seen that traditional method for reading data can functionally meet
Requirements for access, but in the case where such as reading the scenes such as big file or playing video file, CPU needs to get from DRAM continuously
Substantial amounts of data, traditional method are that CPU sends multiple data access instructions to MC, so that MC is constantly multiple to DRAM transmissions
Column address, so to guarantee to read a large amount of continuous data, but such complex operation and power consumption is high.
For the continuous scene for reading mass data of this needs, prior art provides a solution, in the third generation
Double data rate Synchronous Dynamic Random Access Memory（Double-Data-Rate Three Synchronous Dynamic
Random Access Memory, DDR3SDRAM）Specification in, propose that a kind of burst is read（burst read）Operation, specifically
Be by burst read orders, MC only needs to send a row address and a column address to DRAM, and DRAM cans will
Continuous N since the column address（N<9）Individual data block, which is read, to be sent to MC.
At least there are the following problems in the prior art：It is well known that the size of data line is generally 4KB- in DRAM
64KB, and in DDR3SDRAM specification, it is the reading that data are carried out with maximum 8 times data bit width from the perspective of MC,
That is the disposable maximum size for reading data is 512bit, and granularity is bigger than traditional 64bit or 128bit, but still
The size of data line in DRAM is so much smaller than, the data line to read the DRAM cached in whole row buffer, still
Need repeatedly to send burst read orders, that is to say, that the problems such as complex operation and high power consumption still occurs.Therefore, needing
Continuously to read in the scene of mass data, how reduce operation complexity, and reduce power consumption height to turn into art technology
The important topic of personnel's research.
The content of the invention
Embodiments of the invention provide a kind of method for reading data and equipment, reduce in the continuous reading process of mass data
Operation complexity and power consumption.
To reach above-mentioned purpose, embodiments of the invention adopt the following technical scheme that：
The first aspect of the present invention, there is provided a kind of method for reading data, including：
Memory Controller Hub MC sends the row address of the data for needing to read in memory to the memory, with toilet
Memory is stated by the data storage of row corresponding with the row address in the memory in the buffering area of the memory；
The MC sends the first order to the memory, so that the memory is all according to the described first order traversal
Column address sends the data for needing to read to the MC；Wherein, the data for needing to read are in the buffering area
All data of the row corresponding with the row address of storage, described first orders for activating the direct storage in the memory
Device accesses dma logic；
The MC receives the data that the needs that the memory is sent are read.
With reference in a first aspect, in a kind of possible implementation, the number that reads will be needed in the Memory Controller Hub MC
According to row address send to before memory, in addition to：
The MC receives the data access instruction that central processor CPU is sent；Wherein, the data access instruction includes
The row address of the data for needing to read in the memory；
The MC parses the data access instruction and obtains the row address.
With reference to first aspect and above-mentioned possible implementation, in alternatively possible implementation, the data are visited
Ask that instruction includes sign, the sign is used to indicate that the data for needing to read correspond to row for the row address
All data；
The MC parses the data access instruction and obtains the row address, including：
The MC parses the data access instruction and obtains the row address and the sign；
The MC sends the first order to the memory, including：
The MC sends first order according to the sign to the memory.
With reference to first aspect and above-mentioned possible implementation, in alternatively possible implementation, methods described is also
Including：
The data of row corresponding with the row address described in stored in the buffering area need not write back the memory
In in row corresponding with the row address when, the MC sends the second order to the memory, so that the memory is closed
Row corresponding with the row address, and by the bit line in the memory（bitline）It is arranged to predeterminated voltage；Wherein, it is described
Second order for indicate the memory need not will be stored in the buffering area described in row corresponding with the row address
Data are write back in the memory in row corresponding with the row address.
With reference to first aspect and above-mentioned possible implementation, in alternatively possible implementation, connect in the MC
After receiving the data that the needs that the memory is sent are read, in addition to：
When row corresponding with the row address need to carry out zeros data in the memory, the MC is sent out to the memory
Send the 3rd order, so as to the memory according to the described 3rd order will be stored in the buffering area described in the row address
The data of corresponding row are all reset, and the data of row corresponding with the row address described in after clearing are write back into the memory
In in row corresponding with the row address；Wherein, the described 3rd order for indicating the memory by the described and row
Location corresponds to the zeros data of row.
The second aspect of the present invention, there is provided a kind of method for reading data, including：
Memory receives the row address that Memory Controller Hub MC is sent；Wherein, the row address exists for the data that needs are read
Row address in the memory；
The memory is by the data storage of row corresponding with the row address in the memory in the slow of the memory
Rush in area；
The memory receives the first order that the MC is sent；Wherein, described first order for activating the storage
Direct memory access logic in device；
The memory travels through all column address according to the described first order and sends the data for needing to read to institute
State MC；Wherein, the data for needing to read are all data of the row corresponding with the row address stored in the buffering area.
With reference to second aspect, in a kind of possible implementation, in addition to：
The memory receives the second order that the MC is sent；Wherein, described second order for indicating the storage
Device will need not be stored in the buffering area described in row corresponding with the row address data write back in the memory with
The row address is corresponded in row；
The memory closes row corresponding with the row address, and by the bit line in the memory（bitline）If
It is set to predeterminated voltage.
With reference to second aspect and above-mentioned possible implementation, in alternatively possible implementation, in the storage
Device travels through all column address according to the described first order and sends the data for needing to read to the MC, in addition to：
The memory receives the 3rd order that the MC is sent；Wherein, the described 3rd order for indicating the storage
Device is by the zeros data of the row corresponding with the row address；
Memory row corresponding with the row address according to the described 3rd order will store in the buffering area
Data all reset；
The memory by the data of row corresponding with the row address described in after clearing write back in the memory with
In row corresponding to the row address.
The third aspect of the present invention, there is provided a kind of Memory Controller Hub, including：
First transmitting element, for the row address of the data for needing to read in memory to be sent to the memory,
So as to the memory by the data storage of row corresponding with the row address in the memory the memory buffering area
In；
Second transmitting element, for sending the first order to the memory, so that the memory is according to described first
Order travels through all column address and sends the data for needing to read to the Memory Controller Hub MC；Wherein, it is described to need to read
The data taken are all data of the row corresponding with the row address stored in the buffering area, and described first orders for activating
Direct memory access logic in the memory；
First receiving unit, the data read for receiving the needs that the memory is sent.
With reference to the third aspect, in a kind of possible implementation, in addition to：
Second receiving unit, for sending the row address for the data for needing to read to storage in first transmitting element
Before device, the data access instruction that central processor CPU is sent is received；Wherein, the data access instruction includes the need
The row address of the data to be read in the memory；
Resolution unit, for parsing the data access instruction that second receiving unit obtains with obtaining the row
Location.
With reference to the third aspect and above-mentioned possible implementation, in alternatively possible implementation, the data are visited
Ask that instruction includes sign, the sign is used to indicate that the data for needing to read correspond to row for the row address
All data；
The resolution unit, the data access instruction obtained specifically for parsing second receiving unit obtain institute
State row address and the sign；
Second transmitting element, specifically for according to the sign that the resolution unit obtains to the storage
Device sends first order.
With reference to the third aspect and above-mentioned possible implementation, in alternatively possible implementation, in addition to：
4th transmitting element, it is not required to for the data of row corresponding with the row address described in stored in the buffering area
When writing back in the memory in row corresponding with the row address, the second order is sent to the memory, so as to described
Memory closes row corresponding with the row address, and will be bit line in the memory（bitline）It is arranged to predeterminated voltage；
Wherein, described second order for indicate the memory will need not be stored in the buffering area described in and institute
State row address and correspond to the data of row and write back in the memory in row corresponding with the row address.
With reference to the third aspect and above-mentioned possible implementation, in alternatively possible implementation, in addition to：
5th transmitting element, what the needs for receiving the memory transmission in first receiving unit were read
After data, when row corresponding with the row address need to carry out zeros data in the memory, the is sent to the memory
Three order, so as to the memory according to the described 3rd order will be stored in the buffering area described in it is corresponding with the row address
Capable data are all reset, and the data of row corresponding with the row address described in after clearing are write back in the memory and
In row corresponding to the row address；Wherein, the described 3rd order for indicating that the memory will the described and row address pair
The zeros data that should be gone.
The fourth aspect of the present invention.A kind of memory is provided, including：
First receiving unit, for receiving the row address of Memory Controller Hub MC transmissions；Wherein, the row address is to need to read
Row address of the data taken in the memory；
Memory cell, for by row corresponding with the row address that first receiving unit obtains in the memory
Data storage is in the buffering area of the memory；
Second receiving unit, the first order sent for receiving the MC；Wherein, described first order for activating institute
State the direct memory access logic in memory；
Transmitting element, first order for being obtained according to second receiving unit travel through all column address by institute
The data that stating needs to read are sent to the MC；Wherein, it is described to need the data that read to be stored in the buffering area and institute
State all data that row address corresponds to row.
With reference to fourth aspect, in a kind of possible implementation, in addition to：
3rd receiving unit, the second order sent for receiving the MC；Wherein, described second order for indicating institute
State memory will need not be stored in the buffering area described in the data of row corresponding with the row address write back to the storage
In device in row corresponding with the row address；
Processing unit, for closing corresponding with row address row, and by the bit line in the memory（bitline）
It is arranged to predeterminated voltage.
With reference to fourth aspect and above-mentioned possible implementation, in alternatively possible implementation, in addition to：
4th receiving unit, for traveling through all column address by the need according to the described first order in the transmitting element
The data to be read are sent to the MC, receive the 3rd order that the MC is sent；Wherein, the described 3rd order for referring to
Show the memory by the zeros data of the row corresponding with the row address；
Unit is reset, the 3rd order for being obtained according to the 4th receiving unit will store in the buffering area
The row corresponding with the row address data all reset；
Writeback unit, for the data of row corresponding with the row address described in described reset after unit is reset to be write back to
In the memory in row corresponding with the row address.
Method for reading data provided in an embodiment of the present invention and equipment, the row of the data that MC reads needs in memory
Address is sent to memory, so as to memory by the data storage of row corresponding with row address in memory memory buffering area
In, then MC sends the first order to memory, to cause memory travels through all column address according to the first order will to need to read
The data taken send the data read to MC, the needs that now MC can be sent to receive memory, the data that the needs are read
For all data of the row corresponding with row address stored in buffering area, DRAM is activated in memory by the first order received
Dma logic, all data of the row corresponding with row address stored in buffering area are sent out with ensuring to travel through all column address
MC is delivered to, can so be reduced mass data to read all data in buffering area and continuously read by single command
Operation complexity and power consumption in journey.
Brief description of the drawings
In order to illustrate more clearly about the embodiment of the present invention or technical scheme of the prior art, below will be to embodiment or existing
There is the required accompanying drawing used in technology description to be briefly described, it should be apparent that, drawings in the following description are only this
Some embodiments of invention, for those of ordinary skill in the art, without having to pay creative labor, may be used also
To obtain other accompanying drawings according to these accompanying drawings.
Fig. 1 is a kind of method for reading data flow chart that one embodiment of the invention provides；
Fig. 2 is a kind of method for reading data flow chart that another embodiment of the present invention provides；
Fig. 3 is another method for reading data flow chart that another embodiment of the present invention provides；
Fig. 4 is a kind of simplified state machine diagram of data read operation provided by the invention；
Fig. 5 is a kind of Memory Controller Hub composition schematic diagram that another embodiment of the present invention provides；
Fig. 6 is another Memory Controller Hub composition schematic diagram that another embodiment of the present invention provides；
Fig. 7 is a kind of memory composition schematic diagram that another embodiment of the present invention provides；
Fig. 8 is another memory composition schematic diagram that another embodiment of the present invention provides；
Fig. 9 is another Memory Controller Hub composition schematic diagram that another embodiment of the present invention provides；
Figure 10 is another memory composition schematic diagram that another embodiment of the present invention provides.
Embodiment
Below in conjunction with the accompanying drawing in the embodiment of the present invention, the technical scheme in the embodiment of the present invention is carried out clear, complete
Site preparation describes, it is clear that described embodiment is only part of the embodiment of the present invention, rather than whole embodiments.It is based on
Embodiment in the present invention, those of ordinary skill in the art are obtained every other under the premise of creative work is not made
Embodiment, belong to the scope of protection of the invention.
One embodiment of the invention provides a kind of method for reading data, as shown in figure 1, this method can include：
101st, MC sends the row address of the data for needing to read in memory to memory, so that memory will store
The data storage of row corresponding with row address is in the buffering area of memory in device.
Wherein, MC can send the row address of the data for needing to read in memory to memory, so as to memory
By the data storage of the row corresponding with the row address stored in memory in the buffering area of memory.
Optionally, the row address of the data for needing to read in memory can be sent in MC to before memory, MC
The data access instruction of CPU transmissions can be received, wherein, the data access instruction is that CPU needs to read data from memory
When send, and the data access instruction includes the row address of data that needs are read in memory, when MC receives number
, can be to be parsed to the data access instruction received after access instruction, the data that obtaining CPU needs to read are being deposited
Row address in reservoir.
It is further alternative, sign can also be included in data access instruction, the sign is used to indicate to need
The data of reading are all data that row address corresponds to row, then MC can parse data access instruction and obtain row address and instruction
Mark.
102nd, MC sends the first order to memory, so that memory travels through all column address by needs according to the first order
The data of reading are sent to MC., wherein it is desired to the data read are all numbers of the row corresponding with row address stored in buffering area
According to.
Wherein, read in the application scenarios for reading big file or playing video file, it is necessary to from memory a large amount of
Continuous data, the data for now needing to read are all data of the row corresponding with row address stored in buffering area, then MC
, so that memory can travel through all column address according to the first order, it be able to will be buffered with sending the first order to memory
All data of the row corresponding with row address stored in area are sent into MC caching by the data wire between memory and MC,
So in such as reading the needs such as big file or playing video file and continuously reading the scene of mass data, by MC to storage
The single command that device is sent, realizes the reading of continuous mass data.Wherein this first order it is straight in memory for activating
Connect memory access（Direct Memory Access, DMA）Logic.
Optionally, when data access instruction includes sign, and MC parsing data access instructions obtain the sign
When, then MC can be able to be specifically in data access instruction to send the first order to memory according to the sign
It is middle to indicate that CPU needs to read a large amount of continuous data with a bit, then now MC can just send the first order to memory,
So that memory can come out all digital independents of the row corresponding with row address stored in buffering area.It is understood that
If not including sign in data access instruction, or contain the column address for needing to read data, then can be according to existing
There is technology directly to send column address to memory, so that memory comes out digital independent corresponding with column address.
103rd, MC receives the data that the needs that memory is sent are read.
Wherein, the first order is sent to memory in MC, memory travels through all column address according to the first order and will buffered
The data of the row corresponding with row address stored in area are sent to MC, what MC can be read with receiving the needs of memory transmission
Data, and by the data storage received in MC caching, so as to which the data for needing to read are sent to CPU, and then cause
CPU obtains the data for needing to read.
It should be noted that the memory in the embodiment of the present invention can be DRAM, the embodiment of the present invention is at this to storage
Device is not particularly limited.
Method for reading data provided in an embodiment of the present invention, MC send out the row address of the data for needing to read in memory
Deliver to memory, so as to memory by the data storage of row corresponding with row address in memory in the buffering area of memory, so
MC sends the first order to memory afterwards, to cause memory to order the number for traveling through all column address and reading needs according to first
According to sending to MC, now MC can be to receive the data that the needs of memory transmission are read, and the data that the needs are read are buffering
All data of the row corresponding with row address stored in area, DRAM activate the DMA in memory by the first order received
Logic, with ensure to travel through all column address by all data of the row corresponding with row address stored in buffering area send to
MC, it can so be reduced by single command with reading all data in buffering area in the continuous reading process of mass data
Operation complexity and power consumption.
Another embodiment of the present invention provides a kind of method for reading data, as shown in Fig. 2 this method can include：
201st, memory receives the row address that MC is sent.Wherein, the row address is to need the data read in memory
Row address.
Wherein, when CPU needs to carry out the reading of data, data read command can be sent to MC, MC is to receiving
Data read command is parsed, and obtaining CPU needs the row address of the data that read in memory, then will parse what is obtained
Row address is sent to memory, and now memory can be to receive the row address of MC transmissions.
202nd, memory by the data storage of row corresponding with row address in memory in the buffering area of memory.
Wherein, can be with according to the row address that receive, by memory after MC receives the row address of MC transmissions
The data storage of row corresponding with the row address is in the buffering area of memory.
203rd, memory receives the first order that MC is sent.
Wherein, read in the application scenarios for reading big file or playing video file, it is necessary to from memory a large amount of
Continuous data, MC can send the first order to memory, and then memory can be ordered with receiving the first of MC transmissions.Its
In this first order for activating the dma logic in memory.
204th, memory travels through all column address according to the first order and sends the data for needing to read to MC.Wherein, should
The data for needing to read are all data of the row corresponding with row address stored in buffering area
Wherein, when memory receive MC transmission first order after, can to activate the dma logic in memory,
Now dma logic can be to send cumulative column address since 0 according to sequential, and such memory can be to travel through all row
The reading of all data orders of the row corresponding with row address stored in buffering area is obtained needing the data read by address, and
The data for needing to read are sent into MC caching by the data wire between memory and MC, the need that will be received so as to MC
The data to be read are sent to CPU, and then cause CPU to obtain the data for needing to read.
It should be noted that the memory in the embodiment of the present invention can be DRAM, the embodiment of the present invention is at this to storage
Device is not particularly limited.
Method for reading data provided in an embodiment of the present invention, the row address that memory is sent according to the MC received, will be deposited
The data storage of row corresponding with the row address is in the buffering area of memory in reservoir, the then sent according to the MC received
One order, the dma logic in memory is activated so that memory can travel through all column address and send out the data for needing to read
MC is delivered to, so that MC sends the data that the needs received are read to CPU, the data that the needs are read are to be stored in buffering area
Row corresponding with row address all data, memory by receive first order activation memory in dma logic, with
All column address can be traveled through by, which ensuring, sends all data of the row corresponding with row address stored in buffering area to MC, so logical
The complex operation in the continuous reading process of mass data can be reduced to read all data in buffering area by crossing single command
Degree and power consumption.
Another embodiment of the present invention provides a kind of method for reading data, as shown in figure 3, this method can include：
It is well known that such as reading the continuous application scenarios for reading mass data such as big file or playing video file
In, first data can be read in internal memory from hard disk, then so that CPU can continuously read substantial amounts of data, but it is existing
The scheme of continuous mass data is read in technology the defects of complex operation, power consumption is big, and data provided in an embodiment of the present invention are read
The method taken, by adding new order so that in continuously the application scenarios of mass data are read, can effectively reduce big
Operation complexity and power consumption, specific implementation process in the amount continuous reading process of data may be referred to following steps.
301st, MC receives the data access instruction that CPU is sent.
Wherein, when CPU needs to carry out the reading of data, data access instruction can be sent to MC, now MC can be with
Receive the data access instruction that CPU is sent.Wherein, the data that can include needing to read in the data access instruction are in memory
In row address, sign can also be included, the data that the sign is used to indicate to need to read correspond to row for row address
All data.
302nd, MC parses data access instruction and obtains row address and sign.
Wherein, can be with to the data access instruction received after MC receives the data access instruction of CPU transmissions
Parsed, obtain the row address included in data access instruction, and the sign included in data access instruction.
303rd, MC sends row address to memory.
Wherein, after MC parsing data access instructions obtain row address, the row address, the row can be sent to memory
Address can be sent to memory by ACTIVE orders.
304th, memory by the data storage of row corresponding with row address in memory in the buffering area of memory.
Wherein, can be with by row corresponding with row address in memory after memory receives the row address of MC transmissions
Data storage in the buffering area of memory.
305th, MC sends the first order according to sign to memory.
Wherein, from step 301, the sign that MC parses to obtain is indicated for needing the data read for row
Location corresponds to all data of row, then in embodiments of the present invention, MC does not send read command to memory（The wherein READ is ordered
The column address for the data for needing to access is included in order）, but the newer command of addition of the embodiment of the present invention, i.e. MC are sent to memory
The first order is sent to memory, this first is ordered for activating the dma logic in memory.
It should be noted that the first order newly added in the embodiment of the present invention can be multiplexed existing control in the prior art
System orders the pin used to represent, for example, multiplexing sends the pin used during read command；If existing control be present certainly
The untapped pin of signal, the pin that can also be used without using existing control command, but using untapped pin or not
The combination of the pin used represents, such as DDR3 Read orders can be first by A0-A15 selected lines, then using A0-
A9, A11 choose row, and the A12-A15 not used when can use transmission column address in the embodiment of the present invention is encoded, for example is adopted
It is 0001 with A12-A15 pins, to activate the dma logic for reading full line, to reach the purpose for reading full line, also just says and work as A12-
When A15 pins are 0001, represent that MC have sent RAS_READ orders to memory.
306th, memory travels through all column address according to the first order and sends the Data Data for needing to read to MC.Its
In, it is necessary to which the data read are all data of row corresponding with row address stored in buffering area
Wherein, in embodiments of the present invention, when the data for needing to read are the corresponding with row address of the storage in buffering area
During capable all data, in order to realize that single command reads all numbers of the row corresponding with row address of the storage in buffering area
According to the embodiment of the present invention increases a simple dma logic in memory, and the dma logic is receiving the first of MC transmissions
After order, cumulative column address since 0 can be sent according to SECO, so when memory receives the of MC transmissions
After one order, the dma logic in memory is activated, now memory can to travel through all column address, and then according to when
All data of the row corresponding with row address stored in the reading buffering area of sequence order, and by the data read out by with MC
Between data wire send into MC caching.For example, the size of buffering area is 4KB, and stored in buffering area with row ground
The size that location corresponds to the data of row is also 4KB, and the data bit width between memory and MC is 64bit, that is, 8 bytes, according to
The size of data bit width and buffering area between memory and MC, column address can be obtained as 9, then now in memory
The dma logic of addition needs it can be according to the column address signal of sequential export 9（0-511）, so that memory can order
Reading buffering area in all data of row corresponding with row address for storing, and all data of reading are sent to MC caching
In.Wherein, in order to ensure that memory can accurately read out the data of the storage of buffering area according to sequential, dma logic needs
Column address can be produced in strict accordance with the reading sequential of memory.
Optionally, when MC receive memory transmission needs read data when, following steps 307 can be performed：
307th, MC sends the data for needing to read to CPU.
Wherein, can be will receive after MC receives the data of corresponding with the row address row of memory transmission
The data of row corresponding with row address are sent to CPU, so that CPU obtains the data for needing to read.
Optionally, it is well known that during data are read every time, it is also necessary to visit the last time stored in buffering area
The data asked are write back in row corresponding to the memory cell in memory, and the bitline of buffering area is arranged into predeterminated voltage,
But in many application scenarios, it may appear that with regard to useless data after running through, then the process that writes back just becomes nonsensical, and
And it can also bring corresponding power consumption.For example, in memory source anxiety, exchange（Swap）Technology can will be current no interior
Deposit data exchanges to disk to reach recovery internal memory, and the data read at this moment just need not write-back again.Therefore the present invention is real
Apply step 308- steps 309 in example realized by the order newly added read after the data that are not required to no longer write back, and be
Work is ready in the reading of data next time.
308th, when the data of the row corresponding with row address stored in buffering area need not write back in memory with row address pair
When in the row answered, MC sends the second order to memory.
Wherein, when the data of the row corresponding with row address stored in buffering area need not write back in memory with row address pair
When in the row answered, MC can send the second order to memory.For example, the second order is PRECHARGE_WITHOUT_
RESTORE orders, and with reference to the description of step 305, can represent to send PRECHARGE_ when A12-A15 pins are 0010
WITHOUT_RESTORE orders.Wherein, this second order for indicate memory will need not be stored in buffering area and row ground
The data that location corresponds to row are write back in memory in row corresponding with row address.
309th, memory closes corresponding with row address row, and by the bit line in memory（bitline）It is arranged to default
Voltage.
Wherein, after memory receives the second order of MC transmissions, memory, which does not perform, to be stored in buffering area
The data of row corresponding with row address write back in memory with the operation in the corresponding row of row address, but directly close and row address
Corresponding row, and the bitline in memory is arranged to predeterminated voltage, now memory will enter idle condition, etc.
When receiving the row address of MC transmissions again, state of activation is entered back into, carries out the read operation of data next time.That is add
Add and new be used to indicate that the data of the row corresponding with row address stored in buffering area need not be write back to memory by memory
In after order in row corresponding with row address, memory carries out the simplification state machine of read operation as shown in figure 4, in wherein Fig. 4
BA be BankActive abbreviation, activated for memory block, be a block of the storage particle for forming memory, PRE is
Precharge abbreviation, refer to precharging.It should be noted that need what is read in simplification state machine shown in Fig. 4
Data are the data of certain row in certain row, therefore read the data needed after the storage region activation of block according to column address.
It should be noted that step 308- steps 309 can perform after step 307 in the embodiment of the present invention, Ke Yi
Perform again before digital independent next time, the embodiment of the present invention is at this during specific execution to step 308- steps 309
Between be not limited.
Optionally, " zero page is distributed in the kernel of such as operating system（Data are all 0 page）" used etc. to kernel thread should
With in scene, operating system and application developer often have for routine data safety and carry out the bulk memory of distribution clearly
Zero operation, prior art ceaselessly write zero to realize by normal write operation to internal memory, and such operating efficiency is very low.This
Step 310- steps 311 realize the full line clearing of memory by the 3rd order newly added in inventive embodiments, improve
The efficiency of clear operation.
310th, when row corresponding with row address need to carry out zeros data in memory, MC sends the 3rd order to memory.
Wherein, when row corresponding with row address need to carry out zeros data in memory, MC sends the 3rd order to memory,
For example, the 3rd order is BUF_RESET orders, and reference table 1, can be when A12-A15 pins be 0011, expression sends BUF_
RESET orders, wherein, the 3rd orders for indicating memory by the zeros data of row corresponding with row address.
311st, memory all resets the data of the row corresponding with row address stored in buffering area according to the 3rd order, and
The data of row corresponding with row address after clearing are write back in memory in row corresponding with row address.
Wherein, when memory receive MC transmission the 3rd order when, can gate buffering area itself reset logic or
Person is gated for buffering area addition and resets logic, and the data of the row corresponding with row address stored in buffering area are disposable all clear
Zero, then the data of the row corresponding with row address after clearing are write back in memory in row corresponding with row address.
Method for reading data provided in an embodiment of the present invention, MC send out the row address of the data for needing to read in memory
Deliver to memory, so as to memory by the data storage of row corresponding with row address in memory in the buffering area of memory, so
MC sends the first order to memory afterwards, to cause memory to order the number for traveling through all column address and reading needs according to first
According to sending to MC, now MC can be to receive the data that the needs of memory transmission are read, and the data that the needs are read are buffering
All data of the row corresponding with row address stored in area, DRAM activate the DMA in memory by the first order received
Logic, with ensure to travel through all column address by all data of the row corresponding with row address stored in buffering area send to
MC, it can so be reduced by single command with reading all data in buffering area in the continuous reading process of mass data
Operation complexity and power consumption.
Also, for the data not used after reading, memory no longer carries out written-back operation, reduce further work(
Consumption, and memory is by by buffering area high-efficient cleaning zero, realizing the clearing to bulk contiguous memory in memory, improving clearing
The efficiency of operation and the control burden for reducing CPU and MC.
Another embodiment of the present invention provides a kind of Memory Controller Hub, as shown in figure 5, including：First transmitting element 41, second
Transmitting element 42, the first receiving unit 43.
First transmitting element 41, for the row address of the data for needing to read in memory to be sent to the storage
Device, so as to the memory by the data storage of row corresponding with the row address in the memory the memory buffering
Qu Zhong.
Second transmitting element 42, for sending the first order to the memory, so that the memory is according to described the
One order travels through all column address and sends the data for needing to read to the Memory Controller Hub MC；Wherein, the needs
The data of reading are all data of the row corresponding with the row address stored in the buffering area, and described first orders for swashing
Direct memory access logic in the memory living.
First receiving unit 43, the data read for receiving the needs that the memory is sent.
Further, the Memory Controller Hub can also include：Second receiving unit 44, resolution unit 45.
Second receiving unit 44, for first transmitting element 41 by the row address of data for needing to read send to
Before memory, the data access instruction that central processor CPU is sent is received；Wherein, the data access instruction includes institute
State the row address of the data for needing to read in the memory.
Resolution unit 45, the row is obtained for parsing the data access instruction that second receiving unit 44 obtains
Address.
Further, the data access instruction includes sign, and the sign is used to indicate the needs
The data of reading are all data that the row address corresponds to row.
The resolution unit 45, the data access instruction obtained specifically for parsing second receiving unit 44 obtain
To the row address and the sign；
Second transmitting element 42, specifically for according to the sign that the resolution unit 45 obtains to described
Memory sends first order.
Further, as shown in fig. 6, the Memory Controller Hub can also include：4th transmitting element 46.
4th transmitting element 46, the data for the row corresponding with the row address described in stored in the buffering area are not
When needing to write back in the memory in row corresponding with the row address, the second order is sent to the memory, with toilet
State memory and close row corresponding with the row address, and will be bit line in the memory（bitline）It is arranged to default electricity
Pressure.
Wherein, described second order for indicate the memory will need not be stored in the buffering area described in and institute
State row address and correspond to the data of row and write back in the memory in row corresponding with the row address.
Further, the Memory Controller Hub can also include：5th transmitting element 47.
5th transmitting element 47, need to read for receiving the described of memory transmission in first receiving unit 43
After the data taken, when row corresponding with the row address need to carry out zeros data in the memory, sent out to the memory
Send the 3rd order, so as to the memory according to the described 3rd order will be stored in the buffering area described in the row address
The data of corresponding row are all reset, and the data of row corresponding with the row address described in after clearing are write back into the memory
In in row corresponding with the row address；Wherein, the described 3rd order for indicating the memory by the described and row
Location corresponds to the zeros data of row.
Memory Controller Hub provided in an embodiment of the present invention, it would be desirable to the row address of the data of reading in memory send to
Memory, so as to memory by the data storage of row corresponding with row address in memory in the buffering area of memory, then MC
The first order is sent to memory, is sent out with the data for causing memory to be read needs according to first all column address of order traversal
MC is delivered to, now MC can be to receive the data that the needs of memory transmission are read, and the data that the needs are read are in buffering area
All data of the row corresponding with row address of storage, DRAM activate the dma logic in memory by the first order received,
All data of the row corresponding with row address stored in buffering area are sent to MC with ensuring to travel through all column address, so
Can be to read all data in buffering area by single command, the operation reduced in the continuous reading process of mass data is answered
Miscellaneous degree and power consumption.
Also, for the data not used after reading, memory no longer carries out written-back operation, reduce further work(
Consumption, and memory is by by buffering area high-efficient cleaning zero, realizing the clearing to bulk contiguous memory in memory, improving clearing
The efficiency of operation and the control burden for reducing CPU and MC.
Another embodiment of the present invention provides a kind of memory, as shown in fig. 7, comprises：First receiving unit 51, memory cell
52nd, the second receiving unit 53, transmitting element 54.
First receiving unit 51, for receiving the row address of Memory Controller Hub MC transmissions；Wherein, the row address is needs
Row address of the data of reading in the memory.
Memory cell 52, for will be corresponding with the row address that first receiving unit 51 obtains in the memory
Capable data storage is in the buffering area of the memory.
Second receiving unit 53, the first order sent for receiving the MC；Wherein, described first order for activating
Direct memory access logic in the memory.
Transmitting element 54, first order for being obtained according to second receiving unit 53 travel through all column address
The data for needing to read are sent to the MC；Wherein, stored in the data buffering area for needing to read
All data of row corresponding with the row address.
Further, as shown in figure 8, the memory can also include：3rd receiving unit 55, processing unit 56.
3rd receiving unit 55, the second order sent for receiving the MC；Wherein, described second order for indicating
The memory will need not be stored in the buffering area described in the data of row corresponding with the row address write back to described deposit
In reservoir in row corresponding with the row address.
Processing unit 56, for closing corresponding with row address row, and by the bit line in the memory
（bitline）It is arranged to predeterminated voltage.
Further, the memory can also include：4th receiving unit 57, reset unit 58, writeback unit 59.
4th receiving unit 57, for traveling through all column address by institute according to the described first order in the transmitting element 54
The data that stating needs to read are sent to the MC, receive the 3rd order that the MC is sent；Wherein, the 3rd order is used
In indicating the memory by the zeros data of the row corresponding with the row address.
Unit 58 is reset, the described 3rd for being obtained according to the 4th receiving unit 57 is ordered in the buffering area
The data of the row corresponding with the row address of storage are all reset.
Writeback unit 59, for the data of row corresponding with the row address described in described reset after unit 58 is reset to be write
Return in the memory in row corresponding with the row address.
Memory provided in an embodiment of the present invention, the row address sent according to the MC that receives, by memory with the row
Address corresponds to the data storage of row in the buffering area of memory, the first order then sent according to the MC received, will deposit
Dma logic activation in reservoir so that memory can travel through all column address and send the data for needing to read to MC, so as to
MC sends the data that the needs received are read to CPU, and the data that the needs are read are stored in buffering area and row address
All data of corresponding row, memory is by the dma logic in the first order activation memory for receiving, so that ensure can be all over
Go through all column address to send all data of the row corresponding with row address stored in buffering area to MC, so pass through single command
Operation complexity and power consumption in the continuous reading process of mass data can be reduced to read all data in buffering area.
Also, for the data not used after reading, memory no longer carries out written-back operation, reduce further work(
Consumption, and memory is by by buffering area high-efficient cleaning zero, realizing the clearing to bulk contiguous memory in memory, improving clearing
The efficiency of operation and the control burden for reducing CPU and MC.
Another embodiment of the present invention provides a kind of Memory Controller Hub, as shown in figure 9, including：Transmitter 61, receiver 62.
Transmitter 61, for the row address of the data for needing to read in memory to be sent to the memory, so as to
The memory is by the data storage of row corresponding with the row address in the memory in the buffering area of the memory；
The transmitter 61, it is additionally operable to send the first order to the memory, so that the memory is according to described the
One order travels through all column address and sends the data for needing to read to the Memory Controller Hub MC；Wherein, the needs
The data of reading are all data of the row corresponding with the row address stored in the buffering area, and described first orders for swashing
Direct memory access logic in the memory living.
The receiver 62, the data read for receiving the needs that the memory is sent.
Further, the receiver 62, it is additionally operable to send out the row address for the data for needing to read in the transmitter 61
Deliver to before memory, receive the data access instruction that central processor CPU is sent；Wherein, wrapped in the data access instruction
Include the row address of the data for needing to read in the memory.
The Memory Controller Hub can also include：Processor 63.
The processor 63, for parsing the data access instruction that shown receiver 62 obtains with obtaining the row
Location.
Further, the data access instruction includes sign, and the sign is used to indicate the needs
The data of reading are all data that the row address corresponds to row.
The processor 63, the data access instruction obtained specifically for parsing the receiver 62 obtain the row
Address and the sign.
The transmitter 61, sent out specifically for the sign obtained according to the processor 63 to the memory
Send first order.
Further, the transmitter 61, be additionally operable to work as the buffering area in store it is described corresponding with the row address
When capable data need not be write back in the memory in row corresponding with the row address, the second life is sent to the memory
Order, so that the memory closes row corresponding with the row address, and will be bit line in the memory（bitline）Set
For predeterminated voltage.
Wherein, described second order for indicate the memory will need not be stored in the buffering area described in and institute
State row address and correspond to the data of row and write back in the memory in row corresponding with the row address.
Further, the transmitter 61, it is additionally operable to receive the need of the memory transmission in the receiver 62
After the data to be read, when row corresponding with the row address need to carry out zeros data in the memory, to the storage
Device send the 3rd order, so as to the memory according to the described 3rd order will be stored in the buffering area described in the row
The data that address corresponds to row are all reset, and by the data of row corresponding with the row address described in after clearing write back to described in deposit
In reservoir in row corresponding with the row address；Wherein, the described 3rd order for indicate the memory will it is described with it is described
Row address corresponds to the zeros data of row.
Memory Controller Hub provided in an embodiment of the present invention, it would be desirable to the row address of the data of reading in memory send to
Memory, so as to memory by the data storage of row corresponding with row address in memory in the buffering area of memory, then MC
The first order is sent to memory, is sent out with the data for causing memory to be read needs according to first all column address of order traversal
MC is delivered to, now MC can be to receive the data that the needs of memory transmission are read, and the data that the needs are read are in buffering area
All data of the row corresponding with row address of storage, DRAM activate the dma logic in memory by the first order received,
All data of the row corresponding with row address stored in buffering area are sent to MC with ensuring to travel through all column address, so
Can be to read all data in buffering area by single command, the operation reduced in the continuous reading process of mass data is answered
Miscellaneous degree and power consumption.
Also, for the data not used after reading, memory no longer carries out written-back operation, reduce further work(
Consumption, and memory is by by buffering area high-efficient cleaning zero, realizing the clearing to bulk contiguous memory in memory, improving clearing
The efficiency of operation and the control burden for reducing CPU and MC.
Another embodiment of the present invention provides a kind of memory, as shown in Figure 10, including：EBI 71, processor 72, its
In, the EBI 71 is used to be communicated with external equipment.
EBI 71, for receiving the row address of Memory Controller Hub MC transmissions；Wherein, the row address is to need to read
Row address of the data in the memory.
Processor 72, for by the number of row corresponding with the row address that the EBI 71 obtains in the memory
According to being stored in the buffering area of the memory.
The EBI 71, it is additionally operable to receive the first order that the MC is sent；Wherein, described first order for swashing
Direct memory access logic in the memory living.
The EBI 71, for traveling through all column address by the data for needing to read according to the described first order
Send to the MC；Wherein, the data for needing to read are the row corresponding with the row address stored in the buffering area
All data.
Further, the EBI 71, it is additionally operable to receive the second order that the MC is sent；Wherein, described second
Order for indicate the memory will need not be stored in the buffering area described in row corresponding with the row address data
Write back in the memory in row corresponding with the row address.
The processor 72, is additionally operable to close corresponding with row address row, and by the bit line in the memory
（bitline）It is arranged to predeterminated voltage.
Further, the EBI 71, it is additionally operable to order all column address of traversal will according to described first described
The data for needing to read are sent to the MC, receive the 3rd order that the MC is sent；Wherein, the 3rd order
For indicating the memory by the zeros data of the row corresponding with the row address.
The processor 72, the 3rd order for being additionally operable to be obtained according to the EBI 71 is by the buffering area
The data of the row corresponding with the row address of storage are all reset；And by row corresponding with the row address described in after clearing
Data write back in the memory in row corresponding with the row address.
Memory provided in an embodiment of the present invention, the row address sent according to the MC that receives, by memory with the row
Address corresponds to the data storage of row in the buffering area of memory, the first order then sent according to the MC received, will deposit
Dma logic activation in reservoir so that memory can travel through all column address and send the data for needing to read to MC, so as to
MC sends the data that the needs received are read to CPU, and the data that the needs are read are stored in buffering area and row address
All data of corresponding row, memory is by the dma logic in the first order activation memory for receiving, so that ensure can be all over
Go through all column address to send all data of the row corresponding with row address stored in buffering area to MC, so pass through single command
Operation complexity and power consumption in the continuous reading process of mass data can be reduced to read all data in buffering area.
Also, for the data not used after reading, memory no longer carries out written-back operation, reduce further work(
Consumption, and memory is by by buffering area high-efficient cleaning zero, realizing the clearing to bulk contiguous memory in memory, improving clearing
The efficiency of operation and the control burden for reducing CPU and MC.
Through the above description of the embodiments, it is apparent to those skilled in the art that the present invention can borrow
Software is helped to add the mode of required common hardware to realize, naturally it is also possible to which by hardware, but the former is more preferably in many cases
Embodiment.Based on such understanding, portion that technical scheme substantially contributes to prior art in other words
Dividing can be embodied in the form of software product, and the computer software product is stored in the storage medium that can be read, and such as be counted
The floppy disk of calculation machine, hard disk or CD etc., including some instructions are causing a computer equipment（Can be personal computer,
Server, or network equipment etc.）Perform the method described in each embodiment of the present invention.
The foregoing is only a specific embodiment of the invention, but protection scope of the present invention is not limited thereto, any
Those familiar with the art the invention discloses technical scope in, the change or replacement that can readily occur in, all should
It is included within the scope of the present invention.Therefore, protection scope of the present invention should using the scope of the claims as
It is accurate.
Claims (16)
- A kind of 1. method for reading data, it is characterised in that including：Memory Controller Hub MC sends the row address of the data for needing to read in memory to the memory, the row address For indicating the memory by the data storage of row corresponding with the row address in the memory in the slow of the memory Rush in area；The MC sends the first order to the memory, and described first orders for activating the direct storage in the memory Device accesses dma logic, needs what is read by described to indicate that the memory travels through all column address according to the described first order Data are sent to the MC；Wherein, the data for needing to read are corresponding with the row address to be stored in the buffering area Capable all data；The MC receives the data that the needs that the memory is sent are read.
- 2. method for reading data according to claim 1, it is characterised in that will need to read in the Memory Controller Hub MC The row addresses of data send to before memory, in addition to：The MC receives the data access instruction that central processor CPU is sent；Wherein, the data access instruction includes described The row address of the data for needing to read in the memory；The MC parses the data access instruction and obtains the row address.
- 3. method for reading data according to claim 2, it is characterised in that the data access instruction includes indicateing arm Know, the sign is used for all data for indicating that the data for needing to read correspond to row for the row address；The MC parses the data access instruction and obtains the row address, including：The MC parses the data access instruction and obtains the row address and the sign；The MC sends the first order to the memory, including：The MC sends first order according to the sign to the memory.
- 4. according to the method for reading data any one of claim 1-3, it is characterised in that methods described also includes：The data of row corresponding with the row address described in stored in the buffering area need not write back in the memory with When in row corresponding to the row address, the MC sends the second order to the memory；Wherein, described second order for referring to Show the memory will need not be stored in the buffering area described in row corresponding with the row address data write back to it is described In memory in row corresponding with the row address, to indicate that the memory closes row corresponding with the row address, and by institute The bit line (bitline) stated in memory is arranged to predeterminated voltage.
- 5. according to the method for reading data any one of claim 1-3, it is characterised in that deposited described in being received in the MC After the data that the needs that reservoir is sent are read, in addition to：When row corresponding with the row address need to carry out zeros data in the memory, the MC sends the to the memory Three orders；Wherein, the described 3rd order for indicating the memory by the zeros data of the row corresponding with the row address, And indicate the memory by the data of row corresponding with the row address described in after clearing write back in the memory with institute State in row corresponding to row address.
- A kind of 6. method for reading data, it is characterised in that including：Memory receives the row address that Memory Controller Hub MC is sent；Wherein, the row address is the data for needing to read described Row address in memory；The memory by the data storage of row corresponding with the row address in the memory the memory buffering area In；The memory receives the first order that the MC is sent；Wherein, described first order for activating in the memory Direct memory access logic；The memory travels through all column address according to the described first order and sends the data for needing to read to the MC； Wherein, the data for needing to read are all data of the row corresponding with the row address stored in the buffering area.
- 7. method for reading data according to claim 6, it is characterised in that also include：The memory receives the second order that the MC is sent；Wherein, described second order for indicating the memory not The data of row corresponding with the row address described in needing will to store in the buffering area write back in the memory with it is described Row address is corresponded in row；The memory closes row corresponding with the row address, and the bit line (bitline) in the memory is arranged to Predeterminated voltage.
- 8. method for reading data according to claim 6, it is characterised in that in the memory according to the described first order All column address are traveled through to send the data for needing to read to the MC, in addition to：The memory receives the 3rd order that the MC is sent；Wherein, the described 3rd order for indicating that the memory will The zeros data of the row corresponding with the row address；The number of memory row corresponding with the row address according to the described 3rd order will store in the buffering area According to whole clearings；The memory by the data of row corresponding with the row address described in after clearing write back in the memory with it is described In row corresponding to row address.
- A kind of 9. Memory Controller Hub, it is characterised in that including：First transmitting element, for the row address of the data for needing to read in memory to be sent to the memory, so as to The memory is by the data storage of row corresponding with the row address in the memory in the buffering area of the memory；Second transmitting element, for sending the first order to the memory, so that the memory is according to the described first order All column address are traveled through to send the data for needing to read to the Memory Controller Hub MC；Wherein, it is described to need what is read Data are all data of row corresponding with the row address stored in the buffering area, and described first orders for described in activating Direct memory access logic in memory；First receiving unit, the data read for receiving the needs that the memory is sent.
- 10. Memory Controller Hub according to claim 9, it is characterised in that also include：Second receiving unit, for first transmitting element by the row address of data for needing to read send to memory it Before, receive the data access instruction that central processor CPU is sent；Wherein, the data access instruction includes described needing to read The row address of the data taken in the memory；Resolution unit, the row address is obtained for parsing the data access instruction that second receiving unit obtains.
- 11. Memory Controller Hub according to claim 10, it is characterised in that the data access instruction includes indicateing arm Know, the sign is used for all data for indicating that the data for needing to read correspond to row for the row address；The resolution unit, the data access instruction obtained specifically for parsing second receiving unit obtain the row Address and the sign；Second transmitting element, sent out specifically for the sign obtained according to the resolution unit to the memory Send first order.
- 12. according to the Memory Controller Hub any one of claim 9-11, it is characterised in that also include：4th transmitting element, it need not be write for the data of row corresponding with the row address described in stored in the buffering area When returning in the memory in row corresponding with the row address, the second order is sent to the memory, so as to the storage Device closes row corresponding with the row address, and will be that bit line (bitline) is arranged to predeterminated voltage in the memory；Wherein, described second order for indicate the memory will need not be stored in the buffering area described in the row The data that address corresponds to row are write back in the memory in row corresponding with the row address.
- 13. according to the Memory Controller Hub any one of claim 9-11, it is characterised in that also include：5th transmitting element, for receiving the data for the needs reading that the memory is sent in first receiving unit Afterwards, when row corresponding with the row address need to carry out zeros data in the memory, the 3rd life is sent to the memory Order, so as to the memory according to the described 3rd order will store in the buffering area row corresponding with the row address Data are all reset, and by the data of row corresponding with the row address described in after clearing write back in the memory with it is described In row corresponding to row address；Wherein, the described 3rd order for indicating that the memory will the row corresponding with the row address Zeros data.
- A kind of 14. memory, it is characterised in that including：First receiving unit, for receiving the row address of Memory Controller Hub MC transmissions；Wherein, the row address needs to read Row address of the data in the memory；Memory cell, for by the data of row corresponding with the row address that first receiving unit obtains in the memory It is stored in the buffering area of the memory；Second receiving unit, the first order sent for receiving the MC；Wherein, described first order for activating described deposit Direct memory access logic in reservoir；Transmitting element, first order for being obtained according to second receiving unit travel through all column address by the need The data to be read are sent to the MC；It is wherein, described that to need the data that read be storing with the row in the buffering area Address corresponds to all data of row.
- 15. memory according to claim 14, it is characterised in that also include：3rd receiving unit, the second order sent for receiving the MC；Wherein, described second order for indicating described deposit Reservoir will need not be stored in the buffering area described in the data of row corresponding with the row address write back in the memory In row corresponding with the row address；Processing unit, set for closing row corresponding with the row address, and by the bit line (bitline) in the memory For predeterminated voltage.
- 16. memory according to claim 14, it is characterised in that also include：4th receiving unit, need to read by described for traveling through all column address according to the described first order in the transmitting element The data taken are sent to the MC, receive the 3rd order that the MC is sent；Wherein, the described 3rd order for indicating institute Memory is stated by the zeros data of the row corresponding with the row address；Unit is reset, the institute that the 3rd order for being obtained according to the 4th receiving unit will store in the buffering area The data for stating row corresponding with the row address are all reset；Writeback unit, it is described for the data of row corresponding with the row address described in described reset after unit is reset to be write back to In memory in row corresponding with the row address.
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| CN201310291218.2A CN104281545B (en) | 2013-07-11 | 2013-07-11 | A kind of method for reading data and equipment |
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| CN201310291218.2A CN104281545B (en) | 2013-07-11 | 2013-07-11 | A kind of method for reading data and equipment |
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| KR20180114417A (en) * | 2017-04-10 | 2018-10-18 | 에스케이하이닉스 주식회사 | Controller and operating method thereof |
| US10658046B2 (en) * | 2017-05-26 | 2020-05-19 | Macronix International Co., Ltd. | Memory device and method for operating the same |
| CN112331253B (en) * | 2020-10-30 | 2023-12-08 | 深圳市宏旺微电子有限公司 | Chip testing method, terminal and storage medium |
| CN116719755B (en) * | 2023-08-10 | 2023-11-07 | 浪潮电子信息产业股份有限公司 | Method, device and equipment for multi-application memory access |
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