CN104252333B - Band masked bits search circuit, translation lookaside buffer, memorizer and microprocessor - Google Patents
Band masked bits search circuit, translation lookaside buffer, memorizer and microprocessor Download PDFInfo
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- CN104252333B CN104252333B CN201310259758.2A CN201310259758A CN104252333B CN 104252333 B CN104252333 B CN 104252333B CN 201310259758 A CN201310259758 A CN 201310259758A CN 104252333 B CN104252333 B CN 104252333B
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Abstract
The present invention provides a kind of band masked bits and searches circuit, translation lookaside buffer, memorizer and microprocessor, wherein band masked bits search circuit includes first memory element, second memory element, position searching unit and masked bits data input cell；Masked bits data input cell is used to receive data to be stored and masked bits, when masked bits are invalid, exports four groups of data；When masked bits are effective, output is searched invalid code and is not performed search operation with control bit searching unit；First memory element is used to store the first data storage, and second memory element is used to store the second data storage；First memory element sends the first data storage to searching unit for comparing, and second memory element sends the second data storage to searching unit for comparing.The band masked bits that the present invention is provided search circuit and translation lookaside buffer, it is possible to increase microprocessor carries out the speed of data search.
Description
Technical field
The present invention relates to circuit engineering, more particularly to a kind of band masked bits lookup circuit, translation lookaside buffer, memorizer
And microprocessor.
Background technology
First piece of microprocessor was developed from 1971 so far, microprocessor technology has obtained fast development, it is raw in industry
The fields such as product, space flight and aviation and electronic product have a wide range of applications.Microprocessor generally includes controller, arithmetical unit and storage
Device, wherein controller are used for the work for controlling each device in microprocessor, play a part of to coordinate, and are used for arithmetical unit carrying out various patrolling
Collect computing.Program of the microprocessor in running, initial data, ephemeral data and operation result are used in all writing memorizer
In storage, and controller can continually from memorizer, reading program be used to perform, or receive data controls to carry out according to this arithmetical unit
Then the data of renewal are write memorizer by computing again.The speed of microprocessor access memorizer largely have impact on micro-
The speed of service of processor.Translation lookaside buffer in memorizer（Translation lookaside buffer, TLB）It is
The key component of memorizer, for storing virtual address to the conversion table of physical address, realizes immediate addressing.Addressable is deposited
Reservoir（Content Addressable Memory, CAM）As Primary Component in TLB, for realizing data look-up functions.
CAM generally includes multigroup lookup circuit, and per group of position searches circuit includes that a position memory element and a position are looked into
Look for unit, wherein, position memory element be used for store a bit 0 or 1, position searching unit by controller send it is to be found
The data stored in binary number and position memory element are compared, if unanimously, are considered as and match with the data search of storage, if
It is inconsistent, then it is considered as lookup and mismatches, lookup result is passed to into next stage circuit.Each time visit of the microprocessor to memorizer
Ask that will perform position many times searches, therefore, improve CAM circuit structure, improve the speed that position is searched, visit to improving microprocessor
Ask that the speed of memorizer has positive impetus.For the CAM with masked bits, in searching unit generally in place, one is arranged
Specific field effect transistor, its control end receives masked bits signal, and when masked bits are effective, the field effect transistor is ended, so that position is looked into
Look for the outfan of circuit to remain high level, do not perform search operation, be considered as lookup matching；When masked bits are invalid, the effect
Should pipe conducting, the outfan for a searching unit provides discharge path so that position searching unit will can be deposited in the memory element of position
The data of storage are compared with data to be found, judge whether to search matching.But the conducting resistance that the field effect transistor has itself
The time of outfan electric discharge can be increased, reducing the speed of position lookup, and then reduce microprocessor carries out the speed of data search
Degree.
The content of the invention
The present invention provides a kind of band masked bits and searches circuit, translation lookaside buffer, memorizer and microprocessor, for carrying
High microprocessor carries out the speed of data search.
The embodiment of the present invention provides a kind of band masked bits and searches circuit, including first memory element, second store single
Unit, position searching unit and masked bits data input cell；
The masked bits data input cell is used to be input into data to be stored and masked bits, when the masked bits are invalid,
The masked bits data input cell exports the first data, the second data, the 3rd data and the 4th data, wherein, the first data
With the second value data conversely, the 3rd data with the 4th value data conversely, the first data are contrary with the 3rd value data；Work as institute
State masked bits it is effective when, invalid code is searched in masked bits data input cell output, and the lookup invalid code is used to control institute
Rheme searching unit does not perform search operation；
The input of first memory element is connected with the masked bits data input cell, for being input into described
One data and the second data, and the first data storage is stored as, input and the masked bits of the second memory element
Data input cell is connected, and for being input into the 3rd data and the 4th data, and is stored as the second data storage；
The outfan of first memory element is connected with a control end of institute's rheme searching unit, by described
One data storage sends institute's rheme searching unit to be used to compare, outfan and institute's rheme lookup of the second memory element
Another control end of unit is connected, and sending second data storage to institute rheme searching unit is used to compare.
The embodiment of the present invention provides a kind of translation lookaside buffer, including addressable memory array, static storage array
And write signal generative circuit, the addressable memory array includes multiple above-mentioned with masked bits lookup circuits.
The embodiment of the present invention provides a kind of memorizer, including translation lookaside buffer, cache memory, memorizer ground
Location maker and multiple storages unit, wherein, the translation lookaside buffer receives the void that the storage address maker sends
Intend a high position for address, and the virtual address is converted into into physical address, the translation lookaside buffer is using as above
Translation lookaside buffer.
The embodiment of the present invention provides a kind of microprocessor, including controller, arithmetical unit and memorizer, and the memorizer is adopted
Above-mentioned memorizer.
Band masked bits provided in an embodiment of the present invention search circuit, by arranging masked bits data input cell, are first
Position memory element provides the first data and the second data, and provides the 3rd data and the 4th data for second memory element,
First data and the second data are set to numerical value when masked bits are invalid to negate, the 3rd data and the 4th data are set to numerical value and take
Instead, and by the first data and the 3rd data it is set to numerical value and negates, and lookup invalid code is directly set to when masked bits are effective, should
Search invalid code and search operation is not performed for control bit searching unit, be directly considered as data to be stored with data to be found
Match somebody with somebody.And position searching unit can directly export lookup result according to the binary number stored in every memory element, reduce
In the searching unit of position, the quantity of metal-oxide-semiconductor, shortens discharge path, improves the speed of binary number lookup, and then improves micro- place
Reason device carries out the speed of data search.
Description of the drawings
Fig. 1 is the structural representation that circuit is searched with masked bits provided in an embodiment of the present invention；
Fig. 2 is that the structure of the masked bits data input cell searched with masked bits in circuit provided in an embodiment of the present invention is shown
It is intended to；
Fig. 3 is the work schedule schematic diagram that circuit is searched with masked bits provided in an embodiment of the present invention；
Fig. 4 is another structural representation that circuit is searched with masked bits provided in an embodiment of the present invention；
Fig. 5 is another schematic diagram that circuit work schedule is searched with masked bits provided in an embodiment of the present invention.
Specific embodiment
Fig. 1 is the structural representation that circuit is searched with masked bits provided in an embodiment of the present invention, and Fig. 2 is the embodiment of the present invention
What is provided searches the structural representation of the masked bits data input cell in circuit with masked bits.As depicted in figs. 1 and 2, band is covered
It is the element in CAM that code bit searches circuit, and CAM may include that multiple band masked bits search circuit, for searching simultaneously
Multiple binary numbers.
Each band masked bits searches circuit includes a memory element and position searching unit 2, wherein, the output of position memory element
End be connected with the control end of position searching unit 2, by the data storage in the memory element of position send a searching unit 2 to for than
Compared with.Data input pin in the memory element of position receives the binary number of controller transmission and realizes storage, in position searching unit 2
Data input pin receives the binary number to be found that controller sends, and will deposit in the binary number to be found and position memory element
The binary number of storage is compared, if unanimously, is considered as lookup matching, if inconsistent, be considered as lookup and mismatch, output correspondence
Lookup result.Search in circuit in each band masked bits, the quantity of position memory element is two, and specially first storage is single
Unit 11 and second memory element 12.Band masked bits search circuit also includes masked bits data input cell, the masked bits data
Input block includes data input pin 301 and masked bits input 302, is respectively used to be input into data to be stored and masked bits.When
When masked bits are invalid, the masked bits data input cell exports the first data, the second data, the 3rd data and the 4th data, and
It is sent to first memory element 11 and second memory element 12 is stored, to be compared with data to be found, wherein, first
Data are negated with the second value data, and the 3rd data are negated with the 4th value data, and the first data and the 3rd value data are negated.
When masked bits are effective, invalid code is searched in the masked bits data input cell output, and the lookup invalid code is searched for control bit
Unit 2 does not perform search operation, is directly considered as data to be stored with Data Matching to be found.The input of first memory element 11
End is connected with masked bits data input cell, for being input into the first data and the second data, and is stored as the first data storage, the
The input of two memory element 12 is connected with masked bits data input cell, for being input into the 3rd data and the 4th data, and
It is stored as the second data storage.The outfan of first memory element 11 is connected with a control end of position searching unit 2, will
First data storage sends a searching unit 2 to for comparing, outfan and the position searching unit 2 of second memory element 12
Another control end connects, and sends the second data storage to a searching unit 2 for comparing.The number to be stored of above-mentioned input
According to for the controller data to be stored for giving first memory element 11 or second memory element 12 to be entered.Masked bits are then controls
Device processed input, make a look up when masked bits are invalid for control, when masked bits are effective directly by data to be stored with it is to be checked
Data are looked for be set to lookup matching, to control the command signal of searching data digit.
The function of masked bits data input cell provided in an embodiment of the present invention be can according to the state of masked bits and
The data to be stored of input produce four groups of data.When masked bits are effective, no matter the numerical value of data to be stored is how many, by covering
The four groups of data for exporting directly are set to lookup invalid code by code bit data input cell, and the lookup invalid code is searched for control bit
Unit 2 does not perform search operation, is directly considered as data to be stored with Data Matching to be found.When masked bits are invalid, then mask
First data and the 3rd data of position data input cell output are anti-phase each other, to be stored data number of its concrete numerical value with input
The change of value and change.For masked bits data input cell, those skilled in the art can the various circuit structures of designed, designed, with
Realize searching circuit 2 execution position search operation come control bit according to the disarmed state of masked bits, or according to effective shape of masked bits
State is carried out control bit searching unit 2 and is not performed search operation.The present embodiment provides a kind of attainable scheme, as shown in Fig. 2 this is covered
Code bit data input cell can include the first nor gate 31, the second nor gate 32, the first not gate 33, the second not gate 34 and the 3rd
Not gate 35.Wherein, the first input end of the first nor gate 31 is used for input mask position, and the second input is used to be input into number to be stored
According to the outfan of the first nor gate 31 is connected with the input of the first not gate 33, and the outfan of the first nor gate 31 is used to export
Above-mentioned 3rd data, the outfan of the first not gate 33 are used to export the 4th data.The first input end of the second nor gate 32 is used for
Input mask position, the second input are connected with the outfan of the 3rd not gate 35, and the input of the 3rd not gate 35 is waited to deposit for being input into
Storage data, the outfan of the second nor gate 32 are connected with the input of the second not gate 34, and the outfan of the second nor gate 32 is used for
Above-mentioned first data are exported, the outfan of the second not gate 34 is used to export the second data.
The course of work of masked bits data input cell is：When masked bits are that high level is effective, 31 He of the first nor gate
The output of the second nor gate 32 is low level, and the output of the first not gate 33 and the second not gate 34 is high level, i.e., the first number
According to being 0 with the 3rd data, the second data and the 4th data are 1, that is, it is 0 to search invalid code, so that position searching unit 2 is not performed and looked into
Operation is looked for, is directly considered as data to be stored with Data Matching to be found.When masked bits are that low level is invalid, the first nor gate 31
The data to be stored that output with the second nor gate 32 is sent depending on controller, for example, when data to be stored are 1, first
3rd data of the output of nor gate 31 are 0, and the 4th data of the output of the first not gate 33 are 1, and anti-phase due to the 3rd not gate 35
Effect so that the first data of the output of the second nor gate 32 are 1, the second data of the output of the second not gate 34 are 0；When number to be stored
According to for 0 when, the first nor gate 31 output the 3rd data be 1, the first not gate 33 output the 4th data be 0, the second nor gate
First data of 32 outputs are 0, and the second data of the output of the second not gate 34 are 1.It follows that when masked bits are that low level is invalid
When, the first data and the 3rd value data it is anti-phase each other, and the first data and the second value data are anti-phase each other, the 3rd data and
4th value data is anti-phase each other.
For first memory element 11 and second memory element 12, those skilled in the art can be using in prior art
Conventional position storage unit circuit structure, it is also possible to which designed, designed has the circuit structure of storage binary number function.Described
Two memory element 12 and the structure of first memory element 11 can be with identical, and the present embodiment is with first memory element 11
As a example by a kind of concrete implementation scheme is provided：First memory element 11 includes the first field effect（Metal Oxid
Semiconductor, MOS）Pipe, the second field effect transistor and the cross coupling inverter with storage binary number function, this reality
Apply example and the first field effect transistor is referred to simply as into a MOS101, the second field effect transistor is referred to simply as into the 2nd MOS102, this first
MOS101 and the 2nd MOS102 is first kind field effect transistor, and the first kind field effect transistor can be n-channel field effect transistor.This enforcement
, using source electrode and symmetrical, the interchangeable metal-oxide-semiconductor of drain electrode, used as control end, source electrode and drain electrode are used as data for the grid of each metal-oxide-semiconductor for example
End.The control end of the first MOS101 is connected to write word line, and first data terminal of a MOS101 is used to receive the first data, should
First data terminal is referred to as the first data storage input 41, and second data terminal of a MOS101 is connected to cross coupling inverter
Normal phase input end, the control end of the 2nd MOS102 is connected to write word line, and first data terminal of the 2nd MOS102 is used to receiving the
First data terminal is referred to as the second data storage input 42, the second data terminal connection best friend of the 2nd MOS102 by two data
The inverting input of fork coupled inverters.When controller is effective by the write enable signal that write word line sends, above-mentioned write word line
For high level, conversely, when write enable signal is invalid, write word line is low level.First is allowed when write word line is high level
MOS101 and the 2nd MOS102 receiving datas.First data storage input 41 is input into for the positive of first memory element 11
End, inverting input of the second data storage input 42 for first memory element 11, both are anti-phase each other for being input into
Data.
The function of above-mentioned cross coupling inverter is storage binary number, and its particular circuit configurations can also be by technical staff
Designed, designed, the present embodiment provide a kind of implementation：Cross coupling inverter includes the 3rd field effect transistor（Referred to as：3rd
MOS103）, the 4th field effect transistor（Referred to as：4th MOS104）, the 5th field effect transistor（Referred to as：5th MOS105）Imitate with the 6th
Ying Guan（Referred to as：6th MOS106）, wherein, the 3rd MOS103 and the 4th MOS104 be first kind metal-oxide-semiconductor, the first kind metal-oxide-semiconductor
Can be n-channel metal-oxide-semiconductor, the 5th MOS105 and the 6th MOS106 is Equations of The Second Kind metal-oxide-semiconductor, and the Equations of The Second Kind metal-oxide-semiconductor can be p-channel
Metal-oxide-semiconductor.3rd MOS103, the 4th MOS104, each data terminal of the 6th MOS106 and the 5th MOS105 are sequentially connected with and circularize.The
The control end of three MOS103 is connected with the control end of the 5th MOS105, and with the number being connected with the 6th MOS106 in the 4th MOS104
According to end connection, also it is connected with second data terminal of the 2nd MOS102 as the inverting input of cross coupling inverter.4th
The control end of MOS104 is connected with the control end of the 6th MOS106, and with the data being connected with the 5th MOS105 in the 3rd MOS103
End connects, and the normal phase input end as cross coupling inverter is connected with second data terminal of a MOS101, in addition, also
As the control end connection corresponding with position searching unit 2 of first 11 outfan of memory element.
The circuit structure of second memory element 12 is identical with first memory element 11, with first memory element 11 pairs
Answer, first data terminal of the MOS101 in second memory element 12 is used to receive the 3rd data, and the data terminal is claimed
For the 3rd data storage input 43, for receiving the 4th data, the referred to as the 4th stores number to first data terminal of the 2nd MOS102
According to input 44, normal phase input end of the 3rd data storage input 43 for second memory element 12, the 4th data storage are defeated
Enter inverting input of the end 44 for second memory element 12, both are used to be input into mutually anti-phase data.Second storage is single
The control end of the 4th MOS104 in unit 12 is also corresponding with position searching unit 2 as the outfan of second memory element 12
One control end connection.
Position searching unit 2 can include the 7th field effect transistor（Referred to as：7th MOS107）, the 8th field effect transistor（Referred to as：The
Eight MOS108）With the 9th field effect transistor（Referred to as：9th MOS109）, three metal-oxide-semiconductors are first kind metal-oxide-semiconductor, first kind MOS
Pipe can be n-channel metal-oxide-semiconductor.Wherein, the control end of the 7th MOS107 is connected with the outfan of second memory element 12, specifically
It is connected with the control end of the 4th MOS104 in second memory element 12, first data terminal of the 7th MOS107 is searched as position
The normal phase input end of unit 2, receives the binary number to be found that controller sends, second data terminal and the 8th of the 7th MOS107
The first data terminal connection of MOS108.Inverting input of second data terminal of the 8th MOS108 as position searching unit 2, receives
The binary number anti-phase with binary number to be found, can be referred to as anti-phase binary number to be found, the control of the 8th MOS108
End be connected with the outfan of first memory element 11, specifically with first memory element 11 in the 4th MOS104 control end
Connection.In addition, second data terminal of the 7th MOS107 is also connected with the control end of the 9th MOS109, first number of the 9th MOS109
According to the outfan held as position searching unit 2, for exporting lookup result, the outfan generally arrives in binary number to be found
First preliminary filling is high level before, and second data terminal of the 9th MOS109 is grounded.
Position memory element the course of work be：By taking first memory element 11 as an example, when write word line is that high level is effective,
First MOS101 and the 2nd MOS102 conductings, a MOS101 receive the first data, and the 2nd MOS102 receives the second data.Its
In, the principle of the first data storage is set according to position memory element particular circuit configurations, for first of the present embodiment offer
For memory element 11, when masked bits are that low level is invalid, it is assumed that the first data are 1, as shown in the above the second data
Anti-phase each other with the first data, then the second data are 0, the 4th MOS104 and the 5th MOS105 conductings, due to the 5th MOS105 and
The line of the 6th MOS106 data terminals is set to high level always, and the line of the 3rd MOS103 and the 4th MOS104 data terminals is always
It is set to low level, therefore first memory element 11 can keeps the control end of the 4th MOS104, namely first memory element
11 outfan always remains as 1 within this cycle, is considered as the first data storage in first memory element 11.First
Memory element 11 by store the first data output to the 8th MOS108 in position searching unit 2 control end.Likewise, second
Position memory element 12 by store the 3rd data output to the 7th MOS107 in position searching unit 2 control end.
Position searching unit 2 the course of work be：When controller send look into enable signal it is effective when, position searching unit 2
Normal phase input end receives the binary number to be found that controller is sent, and what inverting input received that controller sends anti-phase treats
Search binary number.Before data to be found arrive, the outfan preliminary filling of position searching unit 2 is high level.Below according to position
The difference of memory element output binary number is specifically described：
When the binary number that first memory element 11 and second memory element 12 are exported is 0（I.e. masked bits are effective
State）When, all in cut-off state, the control end of the 9th MOS109 is low level to the 7th MOS107 and the 8th MOS108, because
This 9th MOS109 is also at cut-off state, therefore the outfan of position searching unit 2 still keeps high level, and lookup result is 1, directly
It is considered as lookup matching.
When first output of memory element 11 1, and second memory element 12 exports 0（Data i.e. to be stored are 1）When, the
Seven MOS107 end, the 8th MOS108 conductings.If position searching unit 2 receives binary number to be found for 1, anti-phase to be found two
System number is 0, then the control end of the 9th MOS109 is also 0, and the 9th MOS109 cut-offs, the outfan of position searching unit 2 are remained
High level, represents that data to be found are consistent with data storage, is considered as lookup matching.If position searching unit 2 receives to be found two
System number is 0, and anti-phase binary number to be found is 1, then the control end of the 9th MOS109 is also 1, the 9th MOS109 conductings, and position is looked into
After looking for the outfan of unit 2 to be discharged by the conducting resistance of the 9th MOS109, it is changed into low level, lookup result is 0, table
Show that data to be found are inconsistent with data storage, be considered as lookup and mismatch.
When first output of memory element 11 0, and second memory element 12 exports 1（Data i.e. to be stored are 0）When, the
Seven MOS107 are turned on, the 8th MOS108 cut-offs.If position searching unit 2 receives binary number to be found for 1, anti-phase to be found two
System number is 0, then the control end of the 9th MOS109 is also 1, the 9th MOS109 conductings, and the outfan of position searching unit 2 is by the
After the conducting resistance of nine MOS109 is discharged, it is changed into low level, represents that data to be found are inconsistent with data storage, be considered as
Search and mismatch.If position searching unit 2 receives binary number to be found for 0, anti-phase binary number to be found is 1, then the 9th
The control end of MOS109 is also 0, and the 9th MOS109 cut-offs, the outfan of position searching unit 2 remain high level, and lookup result is
1, represent that data to be found are consistent with data storage, be considered as lookup matching.
Fig. 3 is the work schedule schematic diagram that circuit is searched with masked bits provided in an embodiment of the present invention.With reference to Fig. 3 and on
The course of work of each unit is stated, and is illustrated to the course of work of the circuit when masked bits are invalid being searched with masked bits below：
In the period 1, data to be stored are set as 1, then at the t1 moment, write word line is high level, first memory element
11 the first data for receiving are 1, and the second data are 0（Indicate not in the drawings）, second memory element 12 receive
Three data are 0, and the 4th data are 1（Indicate not in the drawings）, binary number 1 is stored in into first memory element 11, binary system
Number 0 is stored in second memory element 12.At the t2 moment, the first data and the 3rd data are 0, and the second data and the 4th data are 1,
Due to write word line be low level, the change of each data store in not affecting data storage, therefore first memory element 11 two
System number keeps constant, is still 1.And first output of memory element 11 1, the output of second memory element 12 0.At the t3 moment,
Look into enable signal it is effective when, it is assumed that binary number to be found is 0, then the binary number to be found that position searching unit 2 is received is
0, anti-phase binary number to be found is 1, then the outfan output 0 of position searching unit 2, as lookup result, represents to be found two
System number is inconsistent with the binary number of storage, is considered as lookup and mismatches.
In second round, data to be stored are set as 0, then at the t4 moment, write word line is high level, first memory element
11 the first data for receiving are 0, and the second data are 1, and the 3rd data that second memory element 12 is received are 1, the 4th number
According to for 0, binary number 0 is stored in into first memory element 11, binary number 1 is stored in second memory element 12.At the t5 moment,
First data and the 3rd data are 0, and the second data and the 4th data are 1, and as write word line is low level, the change of each data is not
The binary number stored in affecting data storage, therefore first memory element 11 keeps constant, is still 0.And first storage
The output of unit 11 0, the output of second memory element 12 1.At the t6 moment, look into enable signal it is effective when, it is assumed that binary system to be found
Number is 0, and the binary number to be found that position searching unit 2 is received is 0, and anti-phase binary number to be found is 1, then position searching unit
2 outfan output 1, as lookup result, represents that binary number to be found is consistent with the binary number of storage, is considered as lookup
Match somebody with somebody.
In the period 3, data to be stored are set as 1, then at the t7 moment, write word line is high level, first memory element
11 the first data for receiving are 1, and the second data are 0, and the 3rd data that second memory element 12 is received are 0, the 4th number
According to for 1, binary number 1 is stored in into first memory element 11, binary number 0 is stored in second memory element 12.At the t8 moment,
First data and the 3rd data are 0, and the second data and the 4th data are 1, and as write word line is low level, the change of each data is not
The binary number stored in affecting data storage, therefore first memory element 11 keeps constant, is still 1.And first storage
The output of unit 11 1, the output of second memory element 12 0.At the t9 moment, look into enable signal it is effective when, it is assumed that binary system to be found
Number is 1, and the binary number to be found that position searching unit 2 is received is 1, and anti-phase binary number to be found is 0, then position searching unit
2 outfan output 1, as lookup result, represents that binary number to be found is consistent with the binary number of storage, is considered as lookup
Match somebody with somebody.
In the period 4, data to be stored are set as 0, then at the t10 moment, write word line is high level, and first stores single
The first data that unit 11 receives are 0, and the second data are 1, and the 3rd data that second memory element 12 is received are the 1, the 4th
Data are 0, and binary number 0 is stored in first memory element 11, and binary number 1 is stored in second memory element 12.In t11
Carve, the first data and the 3rd data are 0, the second data and the 4th data are 1, as write word line is low level, the change of each data
The binary number that change is stored in not affecting data storage, therefore first memory element 11 keeps constant, is still 0.And first
The output of memory element 11 0, the output of second memory element 12 1.At the t12 moment, look into enable signal it is effective when, it is assumed that to be found two
System number is 1, and the binary number to be found that position searching unit 2 is received is 1, and anti-phase binary number to be found is 0, then position is searched
The outfan output 0 of unit 2, as lookup result, represents that binary number to be found is inconsistent with the binary number of storage, is considered as
Search and mismatch.
Above-described embodiment provides first data and for first memory element by arranging masked bits data input cell
Two data, and provide the 3rd data and the 4th data for second memory element, when masked bits are invalid by the first data and
Second data are set to numerical value and negate, and the first data and the 3rd data are set to numerical value and negate, and the 3rd data and the 4th data are set to number
Value is negated, so that position searching unit performs search operation, and lookup invalid code is directly set to when masked bits are effective, and control bit is looked into
Look for unit not perform search operation, be directly considered as data to be stored with Data Matching to be found.And position searching unit can be with root
Lookup result is exported directly according to the binary number stored in every memory element, it is no longer necessary to masked bits signal is received in prior art
The metal-oxide-semiconductor of control, reduces the quantity of the metal-oxide-semiconductor connected on outfan discharge path in a searching unit, reduces electric conduction
Resistance, shortens a discharge path for searching unit outfan, improves the speed of binary number lookup, and then improves microprocessor
Device carries out the speed of data search.
On the basis of above-mentioned technical proposal, the quantity of position searching unit 2 can be at least two, every searching unit 2
In control end and corresponding position memory element outfan connection, can refer to Fig. 4 and Fig. 5, Fig. 4 provided for the embodiment of the present invention
With masked bits search circuit another structural representation, Fig. 5 be it is provided in an embodiment of the present invention with masked bits search circuit
Another schematic diagram of work schedule.It is specifically described by taking two position searching units 2 as an example below：
Position searching unit 2 includes first searching unit 21 and second searching unit 22, and first searching unit 21 is used
In the first binary number to be found and anti-phase first binary number to be found that controller sends is received, which is constituted and connected mode
The implementation of the position searching unit 2 of above-described embodiment offer is can refer to, here is omitted.Second searching unit 22 can be with
Including the tenth field effect transistor（Referred to as：Tenth MOS110）, the 11st field effect transistor（Referred to as：11st MOS111）With the 12nd
Effect pipe（Referred to as：12nd MOS112）, three metal-oxide-semiconductors are first kind metal-oxide-semiconductor, and the first kind metal-oxide-semiconductor can be n-channel
Metal-oxide-semiconductor.Wherein, the control end of the tenth MOS110 is connected with the outfan of second memory element 12, receives second storage single
The binary number of 12 output of unit, first data terminal of the tenth MOS110 are connect as the normal phase input end of second searching unit 22
The second binary number to be found that admission controller sends, the first number of second data terminal and the 11st MOS111 of the tenth MOS110
According to end connection.Inverting input of second data terminal of the 11st MOS111 as position searching unit 22, receives to be checked with second
The binary number that binary number is anti-phase is looked for, the anti-phase second binary number to be found, the control of the 11st MOS111 can be referred to as
End is connected with the outfan of first memory element 11, receives the binary number of first output of memory element 11.In addition, the tenth
The second data terminal in MOS110 is also connected with the control end of the 12nd MOS112, the first data terminal conduct of the 12nd MOS112
The outfan of position searching unit 22, for exporting lookup result, the outfan generally arrives it in the second binary number to be found
Front first preliminary filling is high level, and second data terminal of the 12nd MOS112 is grounded.
On the basis of above-mentioned technical proposal, with reference to Fig. 5, when masked bits are invalid, including first 21 He of searching unit
Second searching unit 22 with masked bits search circuit the course of work be：
In the period 1, data to be stored are set as 1.At the t3 moment, look into enable signal it is effective when, first searching unit
21 the first binary numbers to be found for receiving are 0, and anti-phase first binary number to be found is 1, and second searching unit 22 connects
The second binary number to be found for receiving is 0, and anti-phase second binary number to be found is 1, then first searching unit 21 is exported
0, as the first lookup result, represent that the first binary number to be found is inconsistent with the binary number of storage, be considered as and do not search not
Match somebody with somebody, and second searching unit 22 also exports 0, as the second lookup result, represent the second binary number to be found with storage
Binary number is inconsistent, is considered as lookup and mismatches.
In second round, data to be stored are set as 0.At the t6 moment, look into enable signal it is effective when, first searching unit
21 the first binary numbers to be found for receiving are 0, and anti-phase first binary number to be found is 1, and second searching unit 22 connects
The second binary number to be found for receiving is 0, and anti-phase second binary number to be found is 1, then first searching unit 21 is exported
1, as the first lookup result, represent that the first binary number to be found is consistent with the binary number of storage, be considered as lookup matching, and
Second searching unit 22 also exports 1, as the second lookup result, represents the binary system of the second binary number to be found and storage
Number is consistent, is considered as lookup matching.
In the period 3, data to be stored are set as 1.At the t9 moment, look into enable signal it is effective when, first searching unit
21 the first binary numbers to be found for receiving are 1, and anti-phase first binary number to be found is 0, and second searching unit 22 connects
The second binary number to be found for receiving is 0, and anti-phase second binary number to be found is 1, then first searching unit 21 is exported
1, as the first lookup result, represent that the first binary number to be found is consistent with the binary number of storage, be considered as lookup matching, the
Two outputs of searching unit 22 0, as the second lookup result, represent the second binary number to be found with the binary number for storing not
Unanimously, it is considered as lookup to mismatch.
In the period 4, data to be stored are set as 0.At the t12 moment, look into enable signal it is effective when, first search it is single
The first binary number to be found that unit 21 receives is 1, and anti-phase first binary number to be found is 0, second searching unit 22
The second binary number to be found for receiving is 0, and anti-phase second binary number to be found is 1, then first searching unit 21 is defeated
Go out 0, as the first lookup result, represent that the first binary number to be found is inconsistent with the binary number of storage, is considered as lookup not
Matching, the output of second searching unit 22 1, as the second lookup result, represent the two of the second binary number to be found and storage
System number is consistent, is considered as lookup matching.
Can be drawn by the above, band masked bits search circuit can be real in a cycle using two position searching units
Existing two-way parallel search, improve the lookup speed of binary number, and then improve microprocessor carries out the speed of data search.
Realize in a cycle, can not only search but also physical address can have been read by virtual address, or find out two groups of things
Reason address, and discharge path is shortened by, improve and search speed, and then improve addressing speed.
Upper rheme memory element and position searching unit are not limited to the concrete structure of the present embodiment offer, and existing skill may also be employed
The circuit structure commonly used in art, masked bits data input cell can also be suitably modified on the basis of the present embodiment, obtain
To other circuit structures.
The embodiment of the present invention also provides a kind of translation lookaside buffer, can include that addressable memory array, static state are deposited
Storage array and write signal generative circuit, addressable memory array therein include that the band masked bits provided by above-described embodiment are looked into
Look for circuit.Addressable memory array is connected with static storage array and write signal generative circuit respectively, for finding ground
The hiting signal of location is sent respectively to static storage array and write signal generative circuit, so that static storage array reads physically
Location.Specifically, addressable memory array may include the basic lookup circuit of multiple parallel connections, and multiple band masked bits in parallel
Circuit is searched, parallel search binary number can be realized.This searches circuit substantially,
The basic control for searching the masked bits that the uncontrolled device of circuit sends.Static storage array and write signal generative circuit can be using existing
The device commonly used in having technology, or realized by those skilled in the art's design, the tool of addressable memory array and other devices
Body connected mode can be realized using the technical scheme that those skilled in the art commonly use.Using above-mentioned translation lookaside buffer,
The speed of binary number lookup can be improved, and then improves the speed of microprocessor access memorizer.
The embodiment of the present invention also provides a kind of memorizer, including translation lookaside buffer, cache memory, memorizer
Address generator and multiple storages unit, wherein, the translation lookaside buffer is connected with storage address maker, for receiving
A high position for the virtual address that the storage address maker sends, and the virtual address is converted into into physical address.By this
The translation lookaside buffer provided using the present embodiment by road translation buffer.
Memorizer can also include mark bit comparison（Tag Compare, abbreviation TAGCMP）Module and access queue module,
Specifically, translation lookaside buffer and cache memory are connected with multiple storage units, receive the data of storage, memorizer ground
Location maker is also connected with cache memory, main to perform address addition, forms virtual address, and by the height of virtual address
Position and low level are sent to translation lookaside buffer and cache memory respectively.Translation lookaside buffer is by the virtual address for obtaining
Physical address is converted into, cache memory is according to the corresponding data of the low level of the virtual address for obtaining index and its physically
Location.TAGCMP modules are queued up with translation lookaside buffer, cache memory and access queue module respectively and are connected, will bypass
The physical address that translation buffer and cache memory are obtained is compared, and determines whether cache memory hits.
If physical address is lacked in cache memory, corresponding data to be read from l2 cache memory or internal memory,
The operation for otherwise reading and writing cache memory will be queued up into access queue module, wait pending.Carried using above-described embodiment
For memorizer, it is possible to increase binary digit search speed, and then improve microprocessor access memorizer speed.
The embodiment of the present invention also provides a kind of microprocessor, including controller, arithmetical unit and memorizer, and wherein memorizer is adopted
The memorizer provided with above-described embodiment.Controller is connected with arithmetical unit and memorizer respectively, for reading from memorizer
Program and data, control carry out data operation and analysis arithmetical unit, then write the result after process in memorizer again.Using
The microprocessor provided by the present embodiment, improves the speed searched to binary digit, and then improves memorizer and conduct interviews
Speed, substantially increase the performance of microprocessor.
Finally it should be noted that：Various embodiments above only to illustrate technical scheme, rather than a limitation；To the greatest extent
Pipe has been described in detail to the present invention with reference to foregoing embodiments, it will be understood by those within the art that：Its according to
So the technical scheme described in foregoing embodiments can be modified, or which part or all technical characteristic are entered
Row equivalent；And these modifications or replacement, do not make the essence of appropriate technical solution depart from various embodiments of the present invention technology
The scope of scheme.
Claims (10)
1. a kind of band masked bits search circuit, it is characterised in that look into including first memory element, second memory element, position
Look for unit and masked bits data input cell；
The masked bits data input cell is used to be input into data to be stored and masked bits, when the masked bits are invalid, described
Masked bits data input cell exports the first data, the second data, the 3rd data and the 4th data, wherein, the first data and the
Two value datas conversely, the 3rd data with the 4th value data conversely, the first data are contrary with the 3rd value data；Cover when described
When code bit is effective, invalid code is searched in the masked bits data input cell output, and the lookup invalid code is used to control institute's rheme
Searching unit does not perform search operation；
The input of first memory element is connected with the masked bits data input cell, for being input into first number
According to the second data, and be stored as the first data storage, the input of the second memory element and the masked bits data
Input block is connected, and for being input into the 3rd data and the 4th data, and is stored as the second data storage；
The outfan of first memory element is connected with a control end of institute's rheme searching unit, and described first is deposited
Storage data send institute's rheme searching unit to be used to compare, outfan and institute's rheme searching unit of the second memory element
Another control end be connected, sending second data storage to institute rheme searching unit is used to compare.
2. band masked bits according to claim 1 search circuit, it is characterised in that the masked bits data input cell bag
Include the first nor gate, the second nor gate, the first not gate, the second not gate and the 3rd not gate；
The first input end of first nor gate is used to be input into the masked bits, and the second input of first nor gate is used
In the data to be stored are input into, the outfan of first nor gate is connected with the input of first not gate, and described the
The outfan of one nor gate is used to export the 3rd data, and the outfan of first not gate is used to export the 4th number
According to；
The first input end of second nor gate is used to be input into the masked bits, the second input of second nor gate with
The outfan connection of the 3rd not gate, the input of the 3rd not gate are used to being input into the data to be stored, and described second
The outfan of nor gate is connected with the input of second not gate, and the outfan of second nor gate is used to exporting described the
One data, the outfan of second not gate are used to export second data.
3. band masked bits according to claim 2 search circuit, it is characterised in that first memory element includes：
First field effect transistor, the second field effect transistor and the cross coupling inverter with storage binary number function, first effect
It is first kind field effect transistor that should manage with the second field effect transistor；
The control end of first field effect transistor is connected to write word line, and the first data terminal of first field effect transistor is used to receive
First data, the second data terminal of first field effect transistor are connected to the positive input of the cross coupling inverter
End；
The control end of second field effect transistor is connected to write word line, and the first data terminal of second field effect transistor is used to receive
Second data, the second data terminal of second field effect transistor are connected to the anti-phase input of the cross coupling inverter
End；
The second memory element is identical with the structure of first memory element；In the second memory element
First data terminal of one field effect transistor is used to receive the 3rd data, the second field effect transistor in the second memory element
The first data terminal be used for receive the 4th data.
4. band masked bits according to claim 3 search circuit, it is characterised in that the cross coupling inverter includes the
Three field effect transistor, the 4th field effect transistor, the 5th field effect transistor and the 6th field effect transistor, the 3rd field effect transistor and the 4th effect
First kind field effect transistor described in Ying Guanwei, the 5th field effect transistor and the 6th field effect transistor are Equations of The Second Kind field effect transistor；
Each data terminal of the 3rd field effect transistor, the 4th field effect transistor, the 6th field effect transistor and the 5th field effect transistor sequentially connects
It is connected into annular；
The control end of the 3rd field effect transistor is connected with the control end of the 5th field effect transistor, and with the 4th field effect
The 6th field effect transistor of Guan Zhongyu connection data terminal connection, also as the cross coupling inverter inverting input with it is described
The second data terminal connection of the second field effect transistor；
The control end of the 4th field effect transistor is connected with the control end of the 6th field effect transistor, and with the 3rd field effect
The data terminal connection of the 5th field effect transistor of Guan Zhongyu connection, and the normal phase input end as the cross coupling inverter and institute
The second data terminal connection of the first field effect transistor is stated, also as the output of first memory element or second memory element
An end control end corresponding with institute rheme searching unit connects.
5. band masked bits according to claim 4 search circuit, it is characterised in that institute's rheme searching unit includes：7th
Field effect transistor, the 8th field effect transistor and the 9th field effect transistor, the 7th field effect transistor, the 8th field effect transistor and the 9th field effect
Manage as the first kind field effect transistor；
The control end of the 7th field effect transistor is connected with the outfan of the second memory element, the 7th field effect transistor
The first data terminal be used to receive binary number to be found, the second data terminal of the 7th field effect transistor and described 8th effect
Should pipe the connection of the first data terminal, the second data terminal of the 8th field effect transistor is used to receive and the binary number to be found
Anti-phase binary number, the control end of the 8th field effect transistor are connected with the outfan of first memory element；
Second data terminal of the 7th field effect transistor is also connected with the control end of the 9th field effect transistor, the 9th effect
Should pipe the first data terminal as institute's rheme searching unit outfan, for exporting lookup result, the 9th field effect transistor
The second data terminal ground connection.
6. it is according to claim 5 band masked bits search circuit, it is characterised in that the quantity of institute's rheme searching unit be to
Few two, the control end in each institute's rheme searching unit is connected with the outfan of corresponding position memory element.
7. band masked bits according to claim 5 search circuit, it is characterised in that the first kind field effect transistor is n ditches
Road field effect transistor, the Equations of The Second Kind field effect transistor are p-channel field effect transistor.
8. a kind of translation lookaside buffer, including addressable memory array, static storage array and write signal generative circuit, its
It is characterised by, the addressable memory array includes that the band masked bits described in multiple any one of claim 1-7 search circuit.
9. a kind of memorizer, including translation lookaside buffer, cache memory, storage address maker and multiple storages
Unit, wherein, the translation lookaside buffer receives the high-order and low level of the virtual address that the storage address maker sends,
And the virtual address is converted into into physical address, it is characterised in that the translation lookaside buffer is using described in claim 8
Translation lookaside buffer.
10. a kind of microprocessor, including controller, arithmetical unit and memorizer, it is characterised in that the memorizer will using right
Seek the memorizer described in 9.
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|---|---|---|---|---|
| US6208544B1 (en) * | 1999-09-09 | 2001-03-27 | Harris Corporation | Content addressable memory cell providing simultaneous read and compare capability |
| CN1702773A (en) * | 2004-05-25 | 2005-11-30 | 英特尔公司 | Programmable parallel lookup memory |
| CN102622434A (en) * | 2011-12-31 | 2012-08-01 | 成都市华为赛门铁克科技有限公司 | Data storage method, data searching method and device |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6208544B1 (en) * | 1999-09-09 | 2001-03-27 | Harris Corporation | Content addressable memory cell providing simultaneous read and compare capability |
| CN1702773A (en) * | 2004-05-25 | 2005-11-30 | 英特尔公司 | Programmable parallel lookup memory |
| CN102622434A (en) * | 2011-12-31 | 2012-08-01 | 成都市华为赛门铁克科技有限公司 | Data storage method, data searching method and device |
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