CN104167372A - Mixed bonding method - Google Patents
Mixed bonding method Download PDFInfo
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- CN104167372A CN104167372A CN201410389773.3A CN201410389773A CN104167372A CN 104167372 A CN104167372 A CN 104167372A CN 201410389773 A CN201410389773 A CN 201410389773A CN 104167372 A CN104167372 A CN 104167372A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L24/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
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Abstract
The invention provides a mixed bonding method. The method includes the steps that two silicon wafers needing bonding are provided, and the bonding interface of each silicon wafer comprises metal and insulating material; the bonding interfaces of the two silicon wafers are aligned, and then the bonding technology and thermal annealing technology are performed on the two silicon wafers; in the processes of performing the bonding technology and the thermal annealing technology, the environmental temperature is controlled to be over 200 DEG C, pressure is exerted on the two silicon wafers, is identical in intensity and opposite in direction and points to the bonding interfaces, and the pressure is over 1,000 N. Through the method, the deformation degree of the bonding interfaces can be lowered, so that the flatness of the wafers on the bonding interfaces is improved, interface dislocation is effectively prevented from occurring, and the success rate of mixed bonding is increased.
Description
Technical field
The present invention relates to semiconductor production line field, relate in particular to a kind of hybrid bonded method.
Background technology
Three dimensional integrated circuits need to be realized the intraconnection of thousands of chips in two wafer bondings, and these need to carry out conductivity bonding to two wafer, general conductivity connects and can realize by simple metal bonding technique and the higher hybrid bonded technique of bond strength, because the intensity that simple metal bonding technique can reach is unsatisfactory, so hybrid bonded technique is the first-selection of bonding technology in current three dimensional integrated circuits.
Hybrid bonded technology is the bonding technology by being provided with metal and insulant on the bonded interface of wafer, and in bonding process, need by the metal on the bonded interface of two wafer align with metal, insulant aligns with insulant, and carry out bonding under certain temperature conditions.Owing to existing the material of two kinds of different coefficients of expansion on bonded interface at least simultaneously, make wafer in the process of bonding, metal on its bonded interface and insulant are under certain temperature action, produce deformation in various degree, it is differential deformation, thereby on bonded interface, there is interface dislocation, and finally cause bonding failure.
The material of the insulant on common bonded interface is silicon dioxide or silicon nitride, and the material of metal is copper, and the difference of thermal expansion coefficients of these materials is fairly obvious, specifically can see table one:
| The common material of semicon industry | Thermal coefficient of expansion (1,000,000// every degree Celsius) |
| Silicon dioxide | 0.55 |
| Silicon nitride | 3.2 |
| Copper | 16.7 |
Table one
By table, the thermal coefficient of expansion of visible insulating material is generally less, and the thermal coefficient of expansion of metal material is generally larger, so carrying out in hybrid bonded process, when after temperature rise, the degrees of expansion that is positioned at insulating material on bonding face and metal is different, metal can expand more violently, as shown in Figure 1, thereby it is not identical to make to be positioned at the overhead height of metal 11 on bonded interface and insulant 12, so can cause bonding failure in bonding process.
Chinese patent (CN 102169845A) discloses a kind of multi-layer mixed synchronization bonding structure for three-dimension packaging and method.The method comprises: on the metal pad surface of a bonded substrate to be mixed, form hard metal conic array; On the metal pad surface of another substrate to be mixed, form soft metal layer; Nonmetal bond pad surface two bonded substrate to be mixed forms dielectric adhesion layer; Hard metal conic array and soft metal layer are aimed at, after heating and pressurize, cone-shaped metal array is inserted in soft metal layer, dielectric adhesion layer interosculates simultaneously, forms the pre-bonding structure of a kind of mixing; Heating, the cone-shaped metal array that makes to be inserted in soft metal layer forms intermetallic compound, and dielectric adhesion layer solidifies combination.
In above-mentioned patent, the mechanical strength in hybrid bonded is improved, but do not consider temperature in hybrid bonded technical process to raise and the difference of the bonded interface material degrees of expansion that causes and the bonding failure that may cause.
Summary of the invention
In view of the above problems, the invention provides a kind of hybrid bonded method.
The technical scheme that technical solution problem of the present invention adopts is:
A kind of hybrid bonded method, wherein, described method comprises:
Two silicon chips that need to carry out bonding are provided, on the bonded interface of every described silicon chip, not only comprise metal but also comprise insulant;
After the bonded interface of described two silicon chips is aimed at, these two silicon chips are carried out to bonding technology and thermal anneal process;
Wherein, carrying out in the process of described bonding technology and thermal anneal process, ambient temperature is controlled at more than 200 DEG C, the while respectively applies an opposite sign but equal magnitude and points to the pressure of described bonded interface on two silicon chips, and described pressure is more than 1000 Ns.
Described hybrid bonded method, wherein, the concrete grammar that the bonded interface of described two silicon chips is aimed at is:
By the metal that needs to be bonded together on the bonded interface of two silicon chips aim at metal, insulant aims at insulant.
Described hybrid bonded method, wherein, described insulant comprises silicon dioxide and silicon nitride.
Described hybrid bonded method, wherein, described metal comprises any one or the multiple combination in copper, tungsten, tin.
Described hybrid bonded method, wherein, the metal on described bonded interface and the top of insulant are in sustained height.
Described hybrid bonded method, wherein, described ambient temperature is 200 DEG C～450 DEG C.
Described hybrid bonded method, wherein, the size of described pressure is 1000～50000 Ns.
Described hybrid bonded method, wherein, the preparation of described bonded interface comprises the following steps:
On top metal device layer in described wafer, prepare metal derby;
Prepare insulant layer and cover described metal derby and described top metal device layer;
Grind described insulant layer to the top of described metal derby, make the top of insulant layer after described grinding and described metal derby in sustained height.
Described hybrid bonded method, wherein, grinds described insulant layer by chemical mechanical milling tech.
Described hybrid bonded method, wherein, prepares described metal derby by electroplating technology.
Technique scheme tool has the following advantages or beneficial effect:
Hybrid bonded method provided by the invention is by carrying out wafer in the process of bonding, wafer is applied to high temperature and high pressure, thereby the insulant and the metal that make to be positioned on wafer bonding interface can be under the effects of high pressure, suppress the thermal expansion effects of part, thereby reduce the degree of deformation, and then the evenness of wafer on bonded interface is improved, and effectively avoid the generation of interface misalignment, improve hybrid bonded success rate.
Brief description of the drawings
With reference to appended accompanying drawing, to describe more fully embodiments of the invention.But appended accompanying drawing only, for explanation and elaboration, does not form limitation of the scope of the invention.
Fig. 1 is the structural representation of bonded interface in the hybrid bonded technique of prior art;
Fig. 2 is the structural representation of the silicon chip for the treatment of bonding in the hybrid bonded method of the present invention;
Fig. 3 is the silicon chip structural representation while carrying out bonding technology in the hybrid bonded method of the present invention.
Embodiment
The invention provides a kind of hybrid bonded method.
The inventive method mainly comprises:
Two silicon chips that need to carry out bonding are provided, wherein, on the bonded interface of every silicon chip, not only comprise metal but also comprise insulant; After the bonded interface of two silicon chips is aimed at, these two silicon chips are carried out to bonding technology and annealing process.Carrying out in the process of bonding technology and thermal anneal process, need to add gentle pressurized operation to two silicon chips, wherein, more than ambient temperature is controlled to 200 DEG C (comprising 200 DEG C), and on two silicon chips, apply a pair of opposite sign but equal magnitude and point to the pressure of bonded interface, for the size of this pressure, need control 1000 Ns above (comprising 1000 Ns) to be advisable.
Below in conjunction with drawings and Examples, the inventive method is elaborated.
As described in Figure 2, first two silicon chips that need to carry out bonding are provided, be respectively the first silicon chip a and the second silicon chip b, in every silicon chip, all include the metal device layer 21 being positioned on substrate 20, on the top of metal device layer 21 (being the bonded interface of wafer), be provided with metal 23 and insulant 22, because the second silicon chip in figure is to be inverted, the second Gold In Silicon Wafers belong to 23 and insulant 22 be arranged at the below of metal device layer 21, metal 23 is all positioned at sustained height with the top of insulant 22, in the present embodiment, metal can be copper, tungsten, any one in tin or multiple combination.
As shown in Figure 3, then, two above-mentioned Gold In Silicon Wafers are belonged to and being alignd with metal, after insulant aligns with insulant, carry out hybrid bonded technique and thermal anneal process, in above-mentioned two technical processs, apply respectively a pair of opposite sign but equal magnitude at the back side of two silicon chips and point to the pressure of bonded interface, be the back side that pressure F1 and pressure F2 act on respectively the first silicon chip a and the second silicon chip b, and the equal and opposite in direction of F1 and F2, the direction of F1 is for straight up, the direction of F2 is for straight down, the size of F1 and F2 need be controlled at 1000 Ns above and 50000 Ns following (as 1000 Ns, 1500 Ns, 50000 Ns etc.), under the effect of a pair of like this pressure, the bonded interface of the first silicon chip a and the second silicon chip b can be aimed at and kept being relatively fixed, avoid producing larger slip.Herein, it is to be noted, pressure F1 in Fig. 3 and pressure F2 are only as a signal of the present invention, for institute's applied pressure, be not limited to this situation, pressure also can apply whole bonding face, on each silicon, exerts pressure, make to act on making a concerted effort and acting on the opposite sign but equal magnitude of making a concerted effort of the pressure on another sheet silicon chip of pressure on a slice silicon chip wherein, and act on same straight line.When two silicon chips are applied to above-mentioned pressure, the temperature that also must control environment, makes ambient temperature at least be greater than 200 DEG C and 450 DEG C following (as 200 DEG C, 300 DEG C, 450 DEG C etc.).In the process of bonding and annealing, adopt above-mentioned high temperature, High Pressure in needing on bonding silicon chip, can reduce, in the bonded interface of silicon chip, relative sliding occurs and the dislocation that causes.
Based on above-described embodiment, treat the preparation process of the bonded interface of bonding silicon chip below and carry out necessary explanation, due to the first silicon chip and the second silicon chip similar in the structure at bonded interface place, therefore, taking the first silicon chip as example, the preparation process at para-linkage interface describes.
First, the top of the metal device layer in the first silicon chip, prepares some metal derbies, equal interval one fixed gap between these some metal derbies.
Then, prepare insulant layer and cover the top of the metal device layer of above-mentioned metal derby and exposure, in this step, preparation technology is controlled, make in prepared insulant layer, be positioned at the surface of part at the top of the metal device layer of exposure higher than the top of above-mentioned metal derby.
Insulant layer to above-mentioned preparation grinds, and makes grinding stop at the top of metal derby, thereby makes the top of insulant layer and the top of some metal derbies after grinding be positioned at sustained height.
So far, complete the preparation of the bonded interface for the treatment of bonding silicon chip.
Above-mentioned metal derby, preferably adopts electroplating technology preparation; The above-mentioned process that insulant layer is ground preferably adopts cmp preparation.
In sum, owing to passing through in bonding technology and annealing process in hybrid bonded method provided by the present invention, the silicon chip for the treatment of bonding applies high temperature, high pressure, thereby make the bonded interface for the treatment of bonding wafer in the process of bonding, the deformation that difficult generation is larger and displacement, improved the success rate of bonding.
For a person skilled in the art, read after above-mentioned explanation, various changes and modifications undoubtedly will be apparent.Therefore, appending claims should be regarded whole variations and the correction of containing true intention of the present invention and scope as.Within the scope of claims, scope and the content of any and all equivalences, all should think and still belong to the intent and scope of the invention.
Claims (10)
1. a hybrid bonded method, is characterized in that, described method comprises:
Two silicon chips that need to carry out bonding are provided, on the bonded interface of every described silicon chip, not only comprise metal but also comprise insulant;
After the bonded interface of described two silicon chips is aimed at, these two silicon chips are carried out to bonding technology and thermal anneal process;
Wherein, carrying out in the process of described bonding technology and thermal anneal process, ambient temperature is controlled at more than 200 DEG C, the while respectively applies an opposite sign but equal magnitude and all points to the pressure of described bonded interface on two silicon chips, and described pressure is more than 1000 Ns.
2. hybrid bonded method as claimed in claim 1, is characterized in that, the concrete grammar that the bonded interface of described two silicon chips is aimed at is:
By the metal that needs to be bonded together on the bonded interface of two silicon chips aim at metal, insulant aims at insulant.
3. hybrid bonded method as claimed in claim 1, is characterized in that, described insulant comprises silicon dioxide and silicon nitride.
4. hybrid bonded method as claimed in claim 1, is characterized in that, described metal comprises any one or the multiple combination in copper, tungsten, tin.
5. hybrid bonded method as claimed in claim 1, is characterized in that, the metal on described bonded interface and the top of insulant are in sustained height.
6. hybrid bonded method as claimed in claim 1, is characterized in that, described ambient temperature is 200 DEG C～450 DEG C.
7. hybrid bonded method as claimed in claim 1, is characterized in that, the size of described pressure is 1000～50000 Ns.
8. hybrid bonded method as claimed in claim 1, is characterized in that, the preparation of described bonded interface comprises the following steps:
On top metal device layer in described wafer, prepare metal derby;
Prepare insulant layer and cover described metal derby and described top metal device layer;
Grind described insulant layer to the top of described metal derby, make the top of insulant layer after described grinding and described metal derby in sustained height.
9. hybrid bonded method as claimed in claim 8, is characterized in that, grinds described insulant layer by chemical mechanical milling tech.
10. hybrid bonded method as claimed in claim 8, is characterized in that, prepares described metal derby by electroplating technology.
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| CN201410389773.3A CN104167372A (en) | 2014-08-08 | 2014-08-08 | Mixed bonding method |
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| CN201410389773.3A CN104167372A (en) | 2014-08-08 | 2014-08-08 | Mixed bonding method |
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Cited By (17)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104925749A (en) * | 2015-04-17 | 2015-09-23 | 上海华虹宏力半导体制造有限公司 | Silicon wafer bonding method |
| CN104979226A (en) * | 2015-06-24 | 2015-10-14 | 武汉新芯集成电路制造有限公司 | Copper mixed bonding method |
| CN104992910A (en) * | 2015-06-24 | 2015-10-21 | 武汉新芯集成电路制造有限公司 | Method for hybrid bonding of metal spurs |
| CN105006440A (en) * | 2015-06-24 | 2015-10-28 | 武汉新芯集成电路制造有限公司 | Vacuum-bonding atmospheric-pressurization hybrid bonding method |
| CN105006441A (en) * | 2015-06-24 | 2015-10-28 | 武汉新芯集成电路制造有限公司 | High-air-pressure thermal-annealing hybrid bonding method |
| CN105140144A (en) * | 2015-09-02 | 2015-12-09 | 武汉新芯集成电路制造有限公司 | Medium pressurized thermal annealing mixed bonding method |
| CN105140143A (en) * | 2015-07-30 | 2015-12-09 | 武汉新芯集成电路制造有限公司 | Wafer bonding process |
| CN105185719A (en) * | 2015-06-24 | 2015-12-23 | 武汉新芯集成电路制造有限公司 | Lock type hybrid bonding method |
| CN106711055A (en) * | 2016-12-29 | 2017-05-24 | 上海集成电路研发中心有限公司 | Mixed bonding method |
| CN106952837A (en) * | 2016-01-06 | 2017-07-14 | 中芯国际集成电路制造(上海)有限公司 | Obtain the method and wafer scale bonding and encapsulating method of thickness of insulating layer |
| CN107731667A (en) * | 2017-08-28 | 2018-02-23 | 长江存储科技有限责任公司 | Possess the hybrid bonded method of metal connecting line and hybrid bonded structure |
| CN107993927A (en) * | 2017-11-20 | 2018-05-04 | 长江存储科技有限责任公司 | The method for improving the hybrid bonded intensity of wafer |
| CN109148415A (en) * | 2018-08-28 | 2019-01-04 | 武汉新芯集成电路制造有限公司 | Polycrystalline circle stacked structure and forming method thereof |
| CN109585346A (en) * | 2019-01-02 | 2019-04-05 | 长江存储科技有限责任公司 | Wafer bonding device and wafer bonding method |
| WO2020227961A1 (en) * | 2019-05-15 | 2020-11-19 | 华为技术有限公司 | Hybrid bonding structure and hybrid bonding method |
| CN111968944A (en) * | 2020-08-24 | 2020-11-20 | 浙江集迈科微电子有限公司 | Ultrathin stacking process for radio frequency module |
| CN112670170A (en) * | 2020-12-30 | 2021-04-16 | 长春长光圆辰微电子技术有限公司 | Method for improving bonding force of silicon wafer |
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Cited By (25)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104925749A (en) * | 2015-04-17 | 2015-09-23 | 上海华虹宏力半导体制造有限公司 | Silicon wafer bonding method |
| CN105185719B (en) * | 2015-06-24 | 2018-04-17 | 武汉新芯集成电路制造有限公司 | A kind of hybrid bonded method of bayonet type |
| CN104979226A (en) * | 2015-06-24 | 2015-10-14 | 武汉新芯集成电路制造有限公司 | Copper mixed bonding method |
| CN104992910A (en) * | 2015-06-24 | 2015-10-21 | 武汉新芯集成电路制造有限公司 | Method for hybrid bonding of metal spurs |
| CN105006440A (en) * | 2015-06-24 | 2015-10-28 | 武汉新芯集成电路制造有限公司 | Vacuum-bonding atmospheric-pressurization hybrid bonding method |
| CN105006441A (en) * | 2015-06-24 | 2015-10-28 | 武汉新芯集成电路制造有限公司 | High-air-pressure thermal-annealing hybrid bonding method |
| CN105185719A (en) * | 2015-06-24 | 2015-12-23 | 武汉新芯集成电路制造有限公司 | Lock type hybrid bonding method |
| CN104992910B (en) * | 2015-06-24 | 2017-07-28 | 武汉新芯集成电路制造有限公司 | A kind of hybrid bonded method of metal bur |
| CN105006440B (en) * | 2015-06-24 | 2018-01-09 | 武汉新芯集成电路制造有限公司 | A kind of hybrid bonded method of vacuum bonding air pressurization |
| CN105140143A (en) * | 2015-07-30 | 2015-12-09 | 武汉新芯集成电路制造有限公司 | Wafer bonding process |
| CN105140143B (en) * | 2015-07-30 | 2019-01-22 | 武汉新芯集成电路制造有限公司 | A kind of wafer bonding technique |
| CN105140144A (en) * | 2015-09-02 | 2015-12-09 | 武汉新芯集成电路制造有限公司 | Medium pressurized thermal annealing mixed bonding method |
| CN106952837B (en) * | 2016-01-06 | 2019-12-31 | 中芯国际集成电路制造(上海)有限公司 | Method for obtaining thickness of insulating layer and wafer-level bonding packaging method |
| CN106952837A (en) * | 2016-01-06 | 2017-07-14 | 中芯国际集成电路制造(上海)有限公司 | Obtain the method and wafer scale bonding and encapsulating method of thickness of insulating layer |
| CN106711055A (en) * | 2016-12-29 | 2017-05-24 | 上海集成电路研发中心有限公司 | Mixed bonding method |
| CN107731667A (en) * | 2017-08-28 | 2018-02-23 | 长江存储科技有限责任公司 | Possess the hybrid bonded method of metal connecting line and hybrid bonded structure |
| CN107993927A (en) * | 2017-11-20 | 2018-05-04 | 长江存储科技有限责任公司 | The method for improving the hybrid bonded intensity of wafer |
| CN109148415A (en) * | 2018-08-28 | 2019-01-04 | 武汉新芯集成电路制造有限公司 | Polycrystalline circle stacked structure and forming method thereof |
| US10867969B2 (en) | 2018-08-28 | 2020-12-15 | Wuhan Xinxin Semiconductor Manufacturing Co., Ltd. | Multi-wafer stacking structure and fabrication method thereof |
| CN109585346A (en) * | 2019-01-02 | 2019-04-05 | 长江存储科技有限责任公司 | Wafer bonding device and wafer bonding method |
| WO2020227961A1 (en) * | 2019-05-15 | 2020-11-19 | 华为技术有限公司 | Hybrid bonding structure and hybrid bonding method |
| US11756922B2 (en) | 2019-05-15 | 2023-09-12 | Huawei Technologies Co., Ltd. | Hybrid bonding structure and hybrid bonding method |
| CN111968944A (en) * | 2020-08-24 | 2020-11-20 | 浙江集迈科微电子有限公司 | Ultrathin stacking process for radio frequency module |
| CN112670170A (en) * | 2020-12-30 | 2021-04-16 | 长春长光圆辰微电子技术有限公司 | Method for improving bonding force of silicon wafer |
| CN112670170B (en) * | 2020-12-30 | 2024-02-02 | 长春长光圆辰微电子技术有限公司 | Method for improving bonding force of silicon wafer |
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