CN104125169A - Link list processing apparatus, link list processing method and related network switch - Google Patents
Link list processing apparatus, link list processing method and related network switch Download PDFInfo
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- CN104125169A CN104125169A CN201410175645.9A CN201410175645A CN104125169A CN 104125169 A CN104125169 A CN 104125169A CN 201410175645 A CN201410175645 A CN 201410175645A CN 104125169 A CN104125169 A CN 104125169A
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Abstract
The invention provides a link list processing apparatus, a link list processing method and a related network switch. The link list processing apparatus has a storage device and a link list controller. The link list controller sets link list information, and writes the link list information into the storage device to create a link list in the storage device. The link list has a plurality of nodes each having a next node address field. The link list information includes a data pattern configured to indicate an end of the link list as well as auxiliary information. The link list controller stores the data pattern into the next node address field of a link-tail node of the link list. The link list processing apparatus, the link list processing method and the related network switch provided by the invention can provide a share link list end structure and fully utilizes storage space.
Description
[technical field]
The present invention is relevant for linked list data structure (link list data structure), more particularly, relevant for the apparatus and method of using chained list tail (link-tail) the storage data pattern (data pattern) of chained list, wherein data pattern is indicated ending and the supplementary (auxiliary information) of chained list.
[background technology]
The network switch (network switch) is the computer network facility of link heterogeneous networks equipment.For instance, the network switch receives the input package that connected first network equipment produces, and package or unmodified package the modification of the package derivation from having received are only transferred to second network equipment, the wherein said package having received is to be received by second network equipment originally.In general, the package having received is comprised of a plurality of data chunk (data chunk) (that is, a plurality of cell datas (cell data)).Therefore, the package of deriving from the package having received is also comprised of a plurality of data chunk (that is, a plurality of cell datas).The network switch has for cushioning the packet buffer of the data chunk that derives package.Yet the idle free memory in packet buffer can not guarantee it is continuous.Therefore, a plurality of data chunk that derive package in being stored into packet buffer after, may be arranged at random packet buffer.
For effectively managing a plurality of data chunk of the derivation package in packet buffer, the network switch can use chained list.Based on linked list data structure, chained list comprises the associated a plurality of nodes of order, and wherein one of a plurality of data chunk of each node and derivation package in packet buffer are relevant, and have next node address field, for storing the address of next node.About the chained list tail node of chained list, because chained list tail node is last node of chained list, there is not the next node with the cascade of chained list tail node.Therefore in conventional design, the next node address field of chained list tail node will store the null pointer (null pointer) that points to address blank (null address), thereby during package transmission, when package transmission circuit reads chained list, inform the ending of package transmission circuit chained list.Because chained list tail node is pointed to " zero " (null), the next node address field of chained list tail has been wasted.
[summary of the invention]
In view of this, spy of the present invention provides following technical scheme:
The embodiment of the present invention provides a kind of chained list processing unit, comprises storage device and chain table controller.Chain table controller is used for arranging chained list information and by chained list information write storage device, to create chained list in storage device; Wherein chained list comprises a plurality of nodes, each node has next node address field, chained list packets of information is containing data pattern, and data pattern is used to indicate ending and the supplementary of chained list, and chain table controller is stored into data pattern the next node address field of the chained list tail node of chained list.
The embodiment of the present invention separately provides a kind of chained list processing method, comprise the chained list information that arranges, wherein chained list packets of information is containing data pattern, and data pattern is used to indicate ending and the supplementary of chained list, and by chained list information write storage device, to create chained list in storage device; Wherein chained list comprises a plurality of nodes, and each node has next node address field, and states the next node address field that data pattern is written into the chained list tail node of chained list.
The embodiment of the present invention provides again a kind of network switch, comprises package receiving circuit, chained list processing unit and package transmission circuit.Package receiving circuit is used for receiving input package, and derives a plurality of the first data chunk from the input package having received; Chained list processing unit, comprise storage device and chain table controller, chain table controller is used for chained list information write storage device, to create chained list in storage device, wherein chained list comprises and a plurality of the first data chunk relevant a plurality of nodes respectively, each node has next node address field, chained list packets of information is containing data pattern, data pattern is used to indicate ending and the supplementary of chained list, and chain table controller is stored into data pattern the next node address field of the chained list tail node of chained list; Package transmission circuit is for deriving a plurality of second data chunk of output package according to chained list from a plurality of the first data chunk, and transmission output package, wherein, when producing output package, package transmission circuit is carried out package with reference to the supplementary of being indicated by chained list tail node and is processed.
Above-described chained list processing unit, chained list processing method and the network switch can provide shares chained list tailstock structure, fully uses memory space.
[accompanying drawing explanation]
Fig. 1 is the schematic diagram according to the network switch of one embodiment of the invention.
Fig. 2 is the operating scheme schematic diagram according to the network switch in Fig. 1 of one embodiment of the invention.
Fig. 3 is the schematic diagram of the state data memory of packet buffer in Fig. 1 and storage device.
Fig. 4 is the schematic diagram according to the network switch of another embodiment of the present invention.
Fig. 5 is the schematic diagram from the data pattern of chain table controller according to the generation of one embodiment of the invention.
Fig. 6 is the operating scheme schematic diagram according to the network switch in Fig. 4 of one embodiment of the invention.
Fig. 7 is the schematic diagram of the state data memory of packet buffer in Fig. 4 and storage device.
[embodiment]
In the middle of specification and claims, used some vocabulary to censure specific assembly.One of skill in the art should understand, and same assembly may be called with different nouns by manufacturer.This specification and claims book is not used as distinguishing the mode of assembly with the difference of title, but the difference in function is used as the benchmark of distinguishing with assembly.In the whole text, in the middle of specification and claims, be open term mentioned " comprising ", therefore should be construed to " comprise but be not limited to ".In addition, " coupling " word comprises directly any and is indirectly electrically connected means at this.Therefore, if describe first device in literary composition, be coupled to the second device, represent that first device can directly be electrically connected in the second device, or be indirectly electrically connected to the second device through other device or connection means.
It is to store supplementary with the next node address field of chained list tail node that the present invention one of mainly imagines.Therefore,, except the ending of indication chained list, chained list tail node also provides with the package of exporting package and processes the additional information (additional information) (for example, control information or data message) being associated.In brief, the invention provides and share chained list tailstock structure, fully to use the memory space being occupied by chained list tail node, thereby save the former additional memory space that is required for buffering package processing relevant information (for example, control information or data message).Sharing the further details of chained list tailstock structure is described below.
Fig. 1 is the schematic diagram according to the network switch of one embodiment of the invention.The network switch 100 is internet/in-house network equipment, and comprise package receiving circuit 102, be coupled to the chained list processing unit 104 of package receiving circuit 102, be coupled to the package transmission circuit 106 of package receiving circuit 102 and chained list processing unit 104, and the package being coupled between package receiving circuit 102 and package transmission circuit 106 forwards (packet forward) circuit 108.Package receiving circuit 102 comprises receiving element 112, packet buffer 114 and buffer management unit 118.Chained list processing unit 104 comprises chain table controller 122 and storage device 124.Note that and in Fig. 1, only illustrated element related to the present invention.In practice, the network switch 100 may comprise additional element to support other functions.Receiving element 112 is for receiving the input package P_IN producing from source network device, and the input package P_IN certainly receiving derives a plurality of data chunk (cell data) 116, and wherein source network device is connected in the network switch 100.For instance, input package P_IN is comprised of a plurality of data chunk 116, and wherein data chunk 116 is received in succession by receiving element 112, and each data chunk 116 is carried a cell data.Buffer management unit 118 is for managing the buffer stores space of packet buffer 114.For instance, buffer management unit 118 is that receiving packet data piece component joins the idle storage space in packet buffer 114, and discharges in packet buffer 114 by transmitting the occupied memory space of use of packet data piece group.Therefore, when receiving element 112 receives the data chunk of input package P_IN, buffer management unit 118 is dynamic assignment one idle storage space in packet buffer 114, and receiving element 112 is stored in the data chunk having received in the idle storage space of distribution.In the present embodiment, before the data chunk having received is stored in packet buffer 114, the data chunk having received does not change.
The positional information of the memory space that the further transmission in buffer management unit 118 has distributed is to chain table controller 122.Chain table controller 122 also has storage management function.The positional information of the memory space based on having distributed, chain table controller 122 distributes a memory space in storage device 124, and information storage is entered to the memory space that distributed to create a node 126 of chained list, the memory space storage data piece group of wherein having distributed, node 126 is relevant to the data chunk having received being stored in packet buffer 114.Node 126 comprises field and next node address field.In the present embodiment, be stored between a plurality of nodes 126 of the chained list creating in a plurality of data chunk 116 in packet buffer 114 and storage device 124 and have man-to-man mapping relations.In other words, a plurality of data chunk of certainly inputting package P_IN and derive and be stored in packet buffer 114 are associated with a plurality of nodes that create and be stored in the chained list in storage device 124 respectively.Therefore, by by chained list from linked list head (link-head) node (that is, first node) pass through (traversing) to chained list tail node (that is, final node), package transmission circuit 106 can take out the data chunk that is stored at random in packet buffer 114 in order to obtain a plurality of data chunk of output package P_OUT.In addition, package repeat circuit 108 obtains the packet data of input package P_IN from receiving element 112, and provides package object information to package transmission circuit 106.Subsequently, package transmission circuit 106 transfers to by output package P_OUT the object network equipment that is connected in the network switch 100.
The data chunk of output package P_OUT successfully transfers to after the object network equipment, and the occupied used memory space of data chunk having been transmitted by this in packet buffer 114 can be released.Thereby buffer management unit 118 is considered as an idle storage space by the memory space that is originally assigned to this data chunk of having transmitted of output package P_OUT.
As shown in Figure 1, chained list node framework has field (data field) and next node address field.According to actual design, consider, the field of each node 126 can be empty.In the present embodiment, the next node address field of each node 126 is designed to for recording next address of node.Thereby, be stored in chained list in storage device 124 and can be configured to a node and be connected in single next node.Chain table controller 122 arranges and is stored in the chained list information INF in storage device 124
lIST, chained list information INF wherein
lISTcan comprise data pattern INF
c, data pattern INF
cbe configured to indicate ending and the supplementary (for example, control information) of chained list.Chain table controller 122 is by data pattern INF
cbe stored in the next node address field of chained list tail node of chained list.In this way, when package transmission circuit 106 reads out data pattern INF from chained list tail node
ctime, package transmission circuit 106 not only identifies the final node that present node is chained list, has also obtained control information simultaneously.When producing output package P_OUT, the supplementary (for example, control information) of package transmission circuit 106 reference list tail node indications is carried out package and is processed.
As shown in Figure 1, storage device 124 at least comprises the first memory space 127 that is positioned at the first address realm and the second memory space 128 that is positioned at the second address realm.Therefore, not all memory spaces of storage device 124 all for storing chained list.Chain table controller 122 is configured to arbitrary chained list to be only stored in the first memory space 127.Please note data pattern INF
cnot point to the null pointer of for example, address blank outside the address realm (, the first address realm and the second address realm) of storage device 124.In the present embodiment, data pattern INF
cthere is the bit pattern (bit pattern) identical with one of second memory space 128 interior a plurality of addresses.That is the null pointer of address blank (that is, be not present in the address in storage device 124) is contrary with using, data pattern INF
cbe set to not use the identical bit pattern in address with in storage device 124 one.Because package transmission circuit 106 is known arbitrary chained list and should be stored in the first memory space 127, when being stored in the bit pattern of next node address field and exceeding the first address realm of the first memory space 127, package transmission circuit 106 can be easy to identify chained list tail node.In addition when detecting the bit pattern of the next node address field that is stored in chained list node, be that while being positioned at the not use address of the second address realm of the second memory space 128, package transmission circuit 106 more obtains control information from chained list node.For instance, control information is used to indicate the reception mistake of the data chunk that input package P_IN is relevant to chained list tail node.
Please also refer to Fig. 2 and Fig. 3.Fig. 2 is the operating scheme schematic diagram according to the network switch 100 in Fig. 1 of one embodiment of the invention.Fig. 3 is the schematic diagram of the state data memory of packet buffer 114 in Fig. 1 and storage device 124.For instance, but be not restriction of the present invention, input package P_IN is straight-through (cut-through) package producing from being connected in the source network device of the network switch 100.Therefore before all data chunk (cell data) of input package P_IN are received, the network switch 100 just starts the data chunk (cell data) of output package P_OUT to transfer to the object network equipment that is connected in the network switch 100.As shown in Figure 2, receiving element 112 orders of package receiving circuit 102 receive data chunk (cell data) RXD0_RXD4 of input package P_IN.When receiving element 112 receives first module data RXD0, and packet buffer 114 is in address 5,10,7 and 12 while having idle storage space, receiving element 112 is stored in first module data RXD0 the memory space of the address 5 that is positioned at packet buffer 114, and therefore chain table controller 122 is used the memory space of the address 5 that is positioned at storage device 124 to create linked list head node.After first module data RXD0 is stored in packet buffer 114, package transmission circuit 106 reads first module data RXD0 from packet buffer 114 immediately, and transmit it as the first data chunk (cell data) TXD0 that exports package P_OUT (that is, RXD0=TXD0).
When receiving element 112 receives second unit data RXD1, and packet buffer 114 is in address 10,7 and 12 while having idle storage space, receiving element 112 is stored in second unit data RXD1 the memory space of the address 10 that is positioned at packet buffer 114, and therefore chain table controller 122 is used the memory space of the address 10 that is positioned at storage device 124 to create node 0, and address 10 is stored into the next node address field of linked list head node, make linked list head node link in node 0.Similarly, after second unit data RXD1 is stored in packet buffer 114, package transmission circuit 106 reads second unit data RXD1 from packet buffer 114 immediately, and transmit it as the second data chunk (cell data) TXD1 that exports package P_OUT (that is, RXD1=TXD1).
About after two cell data RXD2 and RXD3, the same aforesaid operations of carrying out of receiving element 112 and chain table controller 122.Therefore the 3rd cell data RXD2 is stored in the memory space of the address 7 of packet buffer 114, and the 4th cell data RXD3 is stored in the memory space of the address 12 of packet buffer 114.In storage device 124, node 1 and 2 is stored in respectively address 7 and 12, and wherein node 1 is linked in node 2, and node 2 is linked in node 3.
When receiving element 112 receives the 5th cell data RXD4, packet buffer 114 not can be used for cushioning the idle storage space of the 5th cell data RXD4.Therefore there is write error owing to lacking enough storage resources.Receiving element 112 is not stored in the 5th cell data RXD4 receiving in packet buffer 114.Chain table controller 122 arranges write error information as data pattern INF
c, and by data pattern INF
cwrite the next node address field of ingress 2, make node 2 be set to chained list tail node, the reception mistake of the data chunk of the package of indication input simultaneously P_IN (that is, the reception mistake of the 5th cell data RXD4).As the next node address field reading out data pattern INF of package transmission circuit 106 from node 2
ctime, will learn that package is truncated.In the present embodiment, package transmission circuit 106 is attached to output package P_OUT by a default error block group TXD4.When being positioned at the package receiving circuit of the object network equipment and receive producing the output package P_OUT of automatic network switch 100, it will abandon this incomplete package.
In the above-described embodiments, be stored in ending and supplementary that data pattern in the next node address field of chained list tail node is used to indicate chained list, wherein supplementary is control information.Yet it is illustrative object only.In other alternate design, be stored in ending and supplementary that data pattern in the next node address field of chained list tail node can be used for indicating chained list, wherein supplementary is data message.
Please refer to Fig. 4, it is the schematic diagram according to the network switch of another embodiment of the present invention.The structure of the network switch 400 is similar to the network switch 100 shown in Fig. 1.The main difference of the network switch 100 and the network switch 400 is that the network switch 400 more comprises verification and processor 408, and the chain table controller 422 of chained list processing unit 404 is for by data pattern INF
d, comprise data message and (for example produce verification and the D of self checking and processor 408
cKS), be stored to the next node address field of the chained list tail node of chained list, and verification and the D of package transmission circuit 406 based on reading in chained list tail node
cKScarry out verification and calculating, to verify the correctness of output package P_OUT '.For instance, verification and processor 408 calculate verification and the D that derives and be stored in the data chunk (cell data) of the modification in packet buffer 114 from the original data block group (cell data) of inputting package P_IN '
cKS, wherein from inputting package P_IN ', derive and be stored in data chunk in packet buffer 114 and establishment and be stored in the node of the chained list in storage device 124 relevant.About package transmission circuit 406, when producing output package P_OUT ', the supplementary (for example, data message) of package transmission circuit 406 reference list tail node indications is carried out package and is processed (for example, checksum validation).
As mentioned above, storage device 124 at least has the first memory space 127 that is positioned at the first address realm and the second memory space 128 that is positioned at the second address realm.Similarly, because all memory spaces of storage device 124 are not all for storing chained list, chain table controller 422 is configured to arbitrary chained list to be only stored in the first memory space 127.Please note data pattern INF
dnot point to the null pointer of for example, address blank outside the address realm (, the first address realm and the second address realm) of storage device 124.Please refer to Fig. 5, it is the data pattern INF from chain table controller 422 according to the generation of one embodiment of the invention
dschematic diagram.In the present embodiment, data pattern INF
dthere is higher significance bit (more significant bit, be abbreviated as MSB) part and compared with low order (less significant bit, be abbreviated as LSB) part, wherein LSB part as verification and, MSB part is as the prefix (prefix) of check value.More particularly, chain table controller 422 arranges data pattern INF
dmSB partly indicate the ending of chained list, and with the verification and the D that produce self checking and processor 408
cKSlSB part is set.The size of supposing next node address field is 8.If the next node address field of chained list tail node is by the verification of 8 and fully loaded, due to 8 bit checks with data pattern may be identical with one of them data pattern of a plurality of 8 bit address in the first address realm, package transmission circuit 406 may not distinguish in the first address realm of the first memory space 127 8 used address and 8 bit checks that produced by verification and processor 408 and.Therefore, prefix is specifically designed to indicate the ending of chained list.For instance, prefix has 2, and verification and be 6 but not 8.Consider following situation, wherein the first address realm of the first memory space 127 is from 0x00000000 to 0x10000000, and the second address realm of the second memory space 128 is from 0x10000001 to 0x11111111.In chained list each node use in the 0x00000000 to 0x10000000 of Jiang Weizi address, address.Because 6 bit checks and can be in a plurality of bit patterns from 0x000000 to 0x111111 one arrange, the prefix of 2 is deliberately set to 0x11 to guarantee data pattern INF
dthere are 8 bit patterns that are different from the arbitrary address in the first address realm (that is, 0x00000000 to 0x10000000).In other words, chain table controller 422 is by data pattern INF
dmSB be partly set to be different from the common location MSB part of each address in the first address realm of the first memory space 127.
Please also refer to Fig. 6 and Fig. 7.Fig. 6 is the operating scheme schematic diagram according to the network switch 400 in Fig. 4 of one embodiment of the invention.Fig. 7 is the schematic diagram of the state data memory of packet buffer 114 in Fig. 4 and storage device 124.For instance, but be not restriction of the present invention, input package P_IN ' is storage forwarding (store-and-forward) package producing from being connected in the source network device of the network switch 400.Therefore after all data chunk (cell data) of input package P_IN ' are received, the network switch 400 starts the data chunk of output package P_OUT ' to transfer to the object network equipment that is connected in the network switch 400.As shown in Figure 6, receiving element 112 orders of package receiving circuit 102 receive data chunk (cell data) RXD0_RXD3 of input package P_IN ', and amended data chunk (cell data) the RXD0 '-RXD3 ' of correspondence is sequentially stored in to the address 5 of packet buffer 114, in 10,7 and 12 memory space.
For instance, the cell data that can input the original data block group of package P_IN ' by modification produces amended data chunk, and wherein cell data comprises source IP address, tcp source port etc.
When amended first module data RXD0 ' is stored in the memory space of the address 5 that is positioned at packet buffer 114, chain table controller 422 is used the memory space of the address 5 that is positioned at storage device 124 to create linked list head node.When amended second unit data RXD1 ' is stored in the memory space of the address 10 that is positioned at packet buffer 114, chain table controller 422 is used the memory space of the address 10 that is positioned at storage device 124 to create node 0, and address 10 is stored into the next node address field of linked list head node, make linked list head node link in node 0.When amended the 3rd cell data RXD2 ' is stored in the memory space of the address 7 that is positioned at packet buffer 114, chain table controller 422 is used the memory space of the address 7 that is positioned at storage device 124 to create node 1, and address 7 is stored into the next node address field of linked list head node, make node 0 be linked in node 1.When amended the 4th cell data RXD3 ' that certainly inputs the last location data of package P_IN ' and derive is stored in the memory space of the address 12 that is positioned at packet buffer 114, chain table controller 422 is used the memory space of the address 12 that is positioned at storage device 124 to create node 3 as chained list tail node.
When receiving element 112 deposits in packet buffer 114 by amended data chunk (cell data) RXD0 '-RXD3 ' order, receiving element 112 is also delivered to verification and processor 408 by amended data chunk (cell data) RXD0 '-RXD3 ' order.In this way, receive an amended data chunk (cell data), verification and processor 408 calculate and upgrade a verification and.Therefore,, when verification and processor 408 receive amended the 4th cell data RXD4 ', verification and processor 408 produce terminal check and the D of the data chunk (cell data) after inputting all modifications that package P_IN ' derives
cKS.When amended the 4th cell data RXD4 ' that certainly inputs last cell data of package P_IN ' and derive is stored in the memory space of the address 12 that is positioned at packet buffer 114, chain table controller 422 use verification and D
cKSdata pattern INF is set
dlSB part, and by data pattern INF
dbe stored in the next node address field of chained list tail node of address 12 of storage device 124, wherein data pattern INF
dcomprise by the MSB part of prefix " 0x11 " setting with by verification and D
cKSthe LSB part arranging.
Data chunk (cell data) RXD0-RXD3s all due to input package P_IN ' are all received by package receiving circuit 102, and package transmission circuit 406 is allowed to produce and transmission output package P_OUT ' based on amended data chunk (cell data) RXD0 '-RXD3 '.Package transmission circuit 406 reads amended data chunk (cell data) RXD0 '-RXD3 ' and is stored in local FIFO from packet buffer 114 orders with reference to the chained list that is stored in storage device 124, for verify verification and.Subsequently, package transmission circuit 406 reads verification and D from the next node address field of chained list tail node
cKSand verify verification and.If verification and correct, package transmission circuit 406 sequential delivery RXD0 '-RXD3 ' as data chunk (cell data) TXD0-TXD3 of output package P_OUT ' (that is, RXD0 '=TXD0, RXD1 '=TXD1, RXD2 '=TXD2, and RXD3 '=TXD3).If verification and incorrect, package transmission circuit 406 will abandon above-mentioned data.
The chained list framework applications proposing is in the above-described embodiments in the network switch 100/400, for example, for example, for indicate control information (, write error information) or data message (, verification with) with shared chained list tail node.Yet it is illustrative object only, can not be as restriction of the present invention.That is the electronic equipment of the chained list framework that arbitrary use proposes all falls into scope of the present invention.
The foregoing is only preferred embodiment of the present invention, the equivalence that those skill in the art related make according to spirit of the present invention changes and revises, and all should be encompassed in claims.
Claims (23)
1. a chained list processing unit, is characterized in that, comprises:
Storage device; And
Chain table controller, for chained list information being set and described chained list information being write to described storage device, to create chained list in described storage device;
Wherein said chained list comprises a plurality of nodes, each node has next node address field, described chained list packets of information is containing data pattern, described data pattern is used to indicate ending and the supplementary of described chained list, and described chain table controller is stored into described data pattern the described next node address field of the chained list tail node of described chained list.
2. chained list processing unit according to claim 1, is characterized in that, described data pattern is not pointed to the null pointer of address blank.
3. chained list processing unit according to claim 1, it is characterized in that, described storage device at least comprises the first memory space that is positioned at the first address realm and the second memory space that is positioned at the second address realm, described chain table controller is for arbitrary chained list is only stored in to described the first memory space, and described data pattern has the bit pattern identical with one of a plurality of addresses in described the second memory space.
4. chained list processing unit according to claim 1, is characterized in that, described supplementary is control information.
5. chained list processing unit according to claim 4, is characterized in that, the reception mistake of the data chunk that described control information indication is relevant to described chained list tail node.
6. chained list processing unit according to claim 5, it is characterized in that, when nothing can be used to cushion the resource of described data chunk, described chain table controller arranges write error information as described data pattern, and described write error information storage is entered to the described next node address field of described chained list tail node.
7. chained list processing unit according to claim 1, is characterized in that, described supplementary is data message.
8. chained list processing unit according to claim 7, is characterized in that, described data message be to described a plurality of nodes of described chained list respectively relevant a plurality of data chunk verification and.
9. chained list processing unit according to claim 8, it is characterized in that, described data pattern has higher significance bit part and compared with low order part, described in described chain table controller arranges, higher significance bit part to be to indicate the described ending of described chained list, and utilize described verification and arrange described in compared with low order.
10. chained list processing unit according to claim 9, it is characterized in that, described storage device at least comprises the first memory space that is positioned at the first address realm and the second memory space that is positioned at the second address realm, described chain table controller is for arbitrary chained list is only stored in to described the first memory space, and the described higher significance bit of described data pattern is partly different from the higher significance bit part in common location of each address in described the first address realm.
11. 1 kinds of chained list processing methods, is characterized in that, comprise:
Chained list information is set, and wherein said chained list packets of information is containing data pattern, and described data pattern is used to indicate ending and the supplementary of chained list; And
By described chained list information write storage device, to create described chained list in described storage device;
Wherein said chained list comprises a plurality of nodes, and each node has next node address field, and described in state the described next node address field that data pattern is written into the chained list tail node of described chained list.
12. chained list processing methods according to claim 11, is characterized in that, described data pattern is not pointed to the null pointer of address blank.
13. chained list processing methods according to claim 11, it is characterized in that, described storage device at least comprises the first memory space that is positioned at the first address realm and the second memory space that is positioned at the second address realm, arbitrary chained list is only stored in described the first memory space, and described data pattern has the bit pattern identical with one of a plurality of addresses in described the second memory space.
14. chained list processing methods according to claim 11, is characterized in that, described supplementary is control information.
15. chained list processing methods according to claim 14, is characterized in that, the reception mistake of the data chunk that described control information indication is relevant to described chained list tail node.
16. chained list processing methods according to claim 15, is characterized in that, the step that described chained list information is set comprises:
When nothing can be used to cushion the resource of described data chunk, write error information is set as described data pattern, make described write error information be stored into the described next node address field of described chained list tail node.
17. chained list processing methods according to claim 11, is characterized in that, described supplementary is data message.
18. chained list processing methods according to claim 17, is characterized in that, described data message be to described a plurality of nodes of described chained list respectively relevant a plurality of data chunk verification and.
19. chained list processing methods according to claim 18, is characterized in that, described data pattern has higher significance bit part and compared with low order part, and the step that described chained list information is set comprises:
Described in arranging, higher significance bit part is to indicate the described ending of described chained list; And
Utilize described verification and arrange described compared with low order.
20. chained list processing methods according to claim 19, it is characterized in that, described storage device at least comprises the first memory space that is positioned at the first address realm and the second memory space that is positioned at the second address realm, arbitrary chained list is only stored in described the first memory space, and the described higher significance bit of described data pattern is partly different from the higher significance bit part in common location of each address in described the first address realm.
21. 1 kinds of network switchs, is characterized in that, comprise:
Package receiving circuit for receiving input package, and is derived a plurality of the first data chunk from the described input package having received;
Chained list processing unit, comprises:
Storage device; And
Chain table controller, for chained list information is write to described storage device, to create chained list in described storage device, wherein said chained list comprises and described a plurality of the first data chunk relevant a plurality of nodes respectively, each node has next node address field, described chained list packets of information is containing data pattern, described data pattern is used to indicate ending and the supplementary of described chained list, and described chain table controller is stored into described data pattern the described next node address field of the chained list tail node of described chained list; And
Package transmission circuit, for deriving a plurality of second data chunk of output package according to described chained list from described a plurality of the first data chunk, and transmit described output package, wherein, when producing described output package, described package transmission circuit is processed with reference to carrying out package by the described supplementary of described chained list tail node indication.
22. network switchs according to claim 21, is characterized in that, described supplementary is indicated the reception mistake of the data chunk of described input package; And when reading described chained list tail node, described package transmission circuit will be preset error block group and be attached to described output package.
23. network switchs according to claim 21, is characterized in that, more comprise:
Verification and processor, for calculate described a plurality of the first data chunk verification and;
Wherein said chain table controller utilizes described verification and described supplementary is set; And when the described output package of transmission, described package transmission circuit is according to reading in a plurality of the second data chunk described in the described checksum validation of described chained list tail node.
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| US201361816243P | 2013-04-26 | 2013-04-26 | |
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| US14/176,133 US9319314B2 (en) | 2013-04-26 | 2014-02-09 | Apparatus and method for using link-tail of link list to store data pattern which is indicative of end of link list and auxiliary information |
| US14/176,133 | 2014-02-09 |
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