CN104123259A - USB resource utilization method - Google Patents

USB resource utilization method Download PDF

Info

Publication number
CN104123259A
CN104123259A CN201310152801.5A CN201310152801A CN104123259A CN 104123259 A CN104123259 A CN 104123259A CN 201310152801 A CN201310152801 A CN 201310152801A CN 104123259 A CN104123259 A CN 104123259A
Authority
CN
China
Prior art keywords
equipment
compatible
controller
data routing
usb
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
CN201310152801.5A
Other languages
Chinese (zh)
Inventor
汉斯·凡安特卫普
赫尔夫·勒图尔纳
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Cypress Semiconductor Corp
Original Assignee
Cypress Semiconductor Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Cypress Semiconductor Corp filed Critical Cypress Semiconductor Corp
Priority to CN201310152801.5A priority Critical patent/CN104123259A/en
Publication of CN104123259A publication Critical patent/CN104123259A/en
Pending legal-status Critical Current

Links

Abstract

The invention relates to a USB resource utilization method. One or more downlink interfaces can be connected with USB 3.0 compatible equipment and USB 2.0 compatible equipment at the same time and can be in communication with the USB 3.0 compatible equipment and the USB 2.0 compatible equipment at the same time through downlink ports respectively.

Description

The USB utilization of resources
Related application
This utility patent requires in the right of priority of the U.S. Provisional Application sequence number 61/388,061 of submission on September 30th, 2010, and this provisional application is all incorporated to herein by reference.
Background
USB (universal serial bus) (USB) technology has been very successful and their application is almost ubiquitous.The arrival of USB3.0 compatibility standard provides the performance of enhancing by larger message transmission rate.USB3.0 standard adopts SSTX and SSTR signal (" hypervelocity " signal hereinafter referred to as) to realize larger message transmission rate.In order to keep general character, back compatible keeps by also comprising D+ and the D-signal (" at a high speed " signal hereinafter referred to as) of USB2.0 compatibility, and the older USB device that makes not to be configured to process ultra high speed signal can still be used USB2.0 signal (for example at a high speed, at full speed and/or low speed) signal communication.
Accompanying drawing explanation
Accompanying drawing shows the realization of the design of passing in this application.The feature of shown realization can be by more easily being understood with reference to the following description of understanding by reference to the accompanying drawings.Similar reference number is used to indicate similar element in all feasible parts in each accompanying drawing.In addition the figure that, the leftmost numeral reception and registration reference number of each reference number is introduced first and the discussion being associated.
Fig. 1 is can be according to the process flow diagram of the USB resource utilization method of various embodiments realizations.
Fig. 2 shows the embodiment of the system 200 that effectively utilizes USB resource.
Fig. 2 A shows the embodiment of the realization of scheme 212 in equipment 220.
Fig. 2 B shows another embodiment of the realization of scheme 212 in equipment 240.
Fig. 2,2A, 2B and 3-7 are the USB utilization of resources technology that can adopt according to various embodiments of the present invention.
Embodiment
This patent relates to USB (universal serial bus) (USB) technology and relates to particularly the resource of utilizing USB technology to use.USB3.0 is relatively new standard, and it provides than the better performance of existing USB2.0 technology.USB3.0 also keeps the back compatible to USB2.0 equipment.In brief, USB3.0 compatibility interface comprises first group of hypervelocity wire (SSTX and SSRX signal) and second group of high speed USB 2.0 wire (D+ and D-signal).
In many operational versions, USB interface stops in comprising the USB port of socket.Socket can allow user that the plug of upstream device such as flash memory dongle equipment, camera, mouse etc. is inserted in USB port.If upstream device is USB3.0 compatibility, utilize first group of hypervelocity wire with the data communication of upstream device so.Otherwise second group of high speed USB 2.0 wire can be utilized.Such system provides back compatible, and the USB device that makes plug be inserted into any the unknown in port works suitably.
Yet other application does not have the factor of this unknown.For example, USB technology can be used to known parts to be permanently connected together.Under these circumstances, prior known upstream device be USB3.0 compatibility or USB2.0 compatibility.Under these circumstances, first group of hypervelocity wire and second group of compatible wire of USB2.0 of redundancy do not provide the dirigibility of enhancing, but instead only cause the cost of increase and/or the performance of reduction, because in connector is not used.
As used herein, term " USB3.0 " or " USB3.0 compatibility " are for meaning support as USB-IF(Implementers Forum), the equipment of Inc. defined hypervelocity signaling in USB3.0 standard (it can comprise the parts of one or more compatibilities).Similarly, be used in reference to can be for as the D+/D-circuit of USB-IF defined low speed, full speed or high speed signaling in USB2.0 standard for term " high speed wire ".In addition, possible USB3.0 compatible equipment is supported all or some in the defined ability of USB2.0 standard, and USB2.0 compatible equipment is supported some in the defined ability of USB3.0 standard.These two standards are only used as an example, and the spirit not being defined as with respect to method and apparatus embodiment described herein or their equivalents is restrictive.
Fig. 1 is can be for the given performance of increase of system configuration and/or the embodiment of the method 100 of the cost of reduction are provided to user.102, the method is supplied to USB3.0 compatibility interface the upstream device of the hypervelocity part known USB3.0 of being compatibility and that therefore only use interface.104, the method provides the compatible equipment to USB2.0 by the compatible part of the USB2.0 not used of USB3.0 interface.Therefore, single USB3.0 interface can be communicated by letter for the upstream device different from two.In one case, USB3.0 compatibility interface can comprise the downstream port that comprises hypervelocity wire and high speed wire.Hypervelocity wire can be connected in USB3.0 compatible equipment, and high speed wire can be connected in USB2.0 compatible equipment.Therefore, single port can be served two equipment.Therefore,, for given system resource set, final user or consumer can receive than the better and/or more function of possible before function.
In some embodiments, method 100 and/or can be stored on computer-readable recording medium as computer-readable instruction for realizing the additive method of current design.Processor for example controller can object computer instructions with manner of execution.
Fig. 2 shows the embodiment of the system 200 that effectively utilizes USB resource.System 200 comprises main process equipment 202 and two upstream devices 204 and 206.In this case, the known USB3.0 of the being compatibility of upstream device 204 (or having USB3.0 ability at least) equipment, and upstream device 206 known be USB2.0 compatible equipment.For the object of explaining, about by the first scheme 210 below discussing in more detail and alternative plan 212 interpre(ta)tive systems 200.
Main frame 202 can be supplied the interface 214 that comprises first group of wire 216 and second group of wire 218.Interface 214 can be USB3.0 compatibility.In this case, first group of wire 216 is SSTX and SSTR circuits that hypervelocity (USB3.0) is compatible.Similarly, second group of D+ and D-circuit that wire 218 can be (USB2.0) compatibility at a high speed.
In the embodiment of describing in scheme 210, upstream device 204 is known USB3.0 compatible equipments.Therefore, first group of wire 216 be for the communication between main process equipment 202 and upstream device 204, and second group of wire 218 keeps not being utilized, as in 220 indications.Therefore, the viewpoint of using from resource, interface 214 is underused as the resource in scheme 210.The embodiment of a contrast is below being described about scheme 212.
In the embodiment of describing in scheme 212, upstream device 204 is connected in main process equipment 202 in the mode identical with scheme 210.Yet second group of wire 218 is connected in upstream device 206 to increase the utilization of resources.Therefore the interface 214, being connected with single upstream device in scheme 210 can be now for being connected in two upstream devices.Therefore,, for the given cost of main process equipment 202, final user can be than be provided more function in scheme 210 in scheme 212.In other situation, can be USB3.0 compatible equipment and upstream device 204 by implementation 212 be connected in the example of interface 214 in common permanent mode at known upstream device 204.As used herein, common permanent mode means final user and does not expect easily and disconnect continually upstream device 204 and be connected some other upstream device.
Fig. 2 A shows the embodiment of the realization of scheme 212 in equipment 220.In this case, equipment 220 comprises mainboard 222, and mainboard 222 is the graphics card 224 of the known equipment that has USB3.0 ability and is the sound card 226 of known USB2.0 equipment by comprising that the single USB interface 228 of port 230 is coupled in.USB interface is provided to the hypervelocity connector 232 of graphics card 224 and arrives the high speed connector 234 of sound card 226.
Fig. 2 B shows another embodiment of the realization of scheme 212 in equipment 240.In this case, equipment 240 comprises mainboard 242, and it is the graphics card 244 of known USB3.0 equipment that mainboard 242 is coupled in.Mainboard is also coupled in external USB 2.0 compatible connectors 246.External USB 2.0 compatible connectors 246 can be used as can receive the USB socket of any USB2.0 compatible equipment such as memory stick, card reader, keyboard, mouse etc. to represent.Mainboard is connected in graphics card and external USB 2.0 compatible connectors 246 by comprising the single USB interface 248 of port 250.USB interface 248 is provided to the hypervelocity connector 252 of graphics card 244 and arrives the high speed connector 254 of external USB 2.0 compatible connectors 246.
Fig. 3 shows another embodiment of the system 300 that can effectively utilize USB resource.System 300 comprises as docking station 302 and the equipment realized.The principle of describing about docking station 302 can be by other the equipment utilization that can adopt USB technology.In the present embodiment, docking station 302 comprises six outside ports with respect to housing 303 location.One in outside port is the upstream port 304 of going to PC.Remaining five port is with the compatible USB port 306(1 of three USB3.0), 306(2) and 306(3) (be illustrated as USB compatible socket), the downstream port of the form of an ethernet port 308 and a video port 310.Docking station circuit 312 shows the schematic diagram of docking station 302.In the present embodiment, docking station comprises three chipsets: hub chipsets 314, video chipset 316 and Ethernet chip group 318.Hub chipsets 314 can be configured to work as 4 port usb hubs, as in 320 indications.(although 4 port concentrator embodiment, this illustrate, are not crucial about this quantity, and other realization can relate to have or many or or the usb hub of few port).
Video chipset 316 can be configured to provide USB3.0 to video capability, as in 322 indications.Ethernet chip group 318 can be configured to provide USB2.0 to ethernet feature, as in 324 indications.Therefore, hub chipsets 314 is connected in upstream port 304 by interface 326.Hub chipsets 314 is by interface 328(1) be connected in USB3.0 port 306(1), by interface 328(2) be connected in USB3.0 port 306(2), and by interface 328(3) be connected in USB3.0 port 306(3).In addition, hub chipsets is by interface 328(4) be connected in video chipset 316 and Ethernet chip group 318.Finally, video chipset 316 is connected in video port 310 by interface 330.Similarly, Ethernet chip group 318 is connected in ethernet port 308 by interface 332.Note, in the present embodiment, between hub chipsets 314 and video chipset 316 and Ethernet chip group 318, pass through interface 328(4) connection can be considered to relative " fixing ".For example, if there is no the fault of in chipset and replacing subsequently, connect so do not expect disturbed.Can be considered to relatively-stationary a kind of scheme is that chipset is welded on the situation on printed circuit board (PCB) (PCB).
Interface 328(4) can be configured to consistent with the description about the scheme 212 of Fig. 2 above.In this realization, recall docking station 302 and comprise four port usb hubs 320.For example, yet communication can be used-the 306(3 of Wu Ge downstream mechanism (USB3.0 port 306(1)), video chipset 316 and Ethernet chip group 318) set up.Therefore the resource that, this realization utilizes four port concentrators to provide than previous technology better.
Although system 300 explained in the content of docking station, design of the present invention can for example realize in hub, repeater, shunt, monitor, ASIC, computing equipment, camera and memory device and other equipment at any amount of equipment.
Fig. 4 shows another embodiment of the system 400 that can effectively utilize USB resource.System 400 comprises the equipment of the form of the notebook computing equipment 402 to comprise PC chipset 404 in inside.The principle of describing about notebook computing equipment 402 can be by other the equipment utilization that can adopt USB technology.In the present embodiment, notebook computing equipment 402 comprises that the compatible downstreams of two external USBs 3.0 connect or port 406(1) and 406(2) (be illustrated as USB socket), a USB3.0 solid-state drive 408 and a USB2.0 optical drive 410.PC chipset 404 comprises a USB3.0 console controller 412 and three USB3.0 interface 414(1), 414(2) and 414(3).
Console controller 412 is by USB3.0 interface 414(1) be coupled in USB3.0 port 406(1) and by USB3.0 interface 414(2) be coupled in USB3.0 port 406(2).Console controller 412 is by USB3.0 interface 414(3) be coupled in USB3.0 solid-state drive 408 and optical drive 410.In this specific situation, interface 414(3) can allow ultra high speed signal to transmit between USB3.0 console controller 412 and USB3.0 solid-state drive 408.Interface 414(3) can also allow (and/or low speed and/or full-speed signal) at a high speed to transmit between console controller 412 and optical drive 410.Therefore, this realization can allow USB3.0 console controller 412 and four ports and/or utilize the only devices communicating of three interfaces.Therefore, this realization utilizes available resources better than previous technology.
Fig. 5 shows another embodiment of the system 500 that can effectively utilize USB resource.System 500 comprises main frame or upstream equipment 502 and two upstream devices 504 and 506.In the present embodiment, upstream device 504 is known USB3.0 compatible equipments, and upstream device 506 is known USB2.0 compatible equipments.
Main process equipment 502 comprises the host chip group 510 that comprises controller 512 and limit interface 514.(host chip group 510 can also limit and be not shown on this but the interface of shown in Figure 3 other for example).Interface 514 can limit the first data or signal path 516 and the second data or signal path 518.The first data routing 516 can extend to allow the communication between these two equipment between main process equipment 502 and upstream device 504.Similarly, the second data routing 518 can extend to allow the communication between these two equipment between main process equipment 502 and upstream device 506.
The first data routing 510 can comprise first group of wire 520, and the second data routing 512 can comprise second group of wire 522.First group of SSTX and SSTR circuit that wire 520 can be USB3.0 compatibility.Similarly, second group of D+ and D-circuit that wire 522 can be USB2.0 compatibility.
Interface 514 can allow the data communication between controller 512 and the first and second upstream devices 504 and 506.In addition, in this realization, data routing 516 and 518 can allow respectively between downstream equipment 504 and controller 512 and downstream equipment 506 and controller between time communication.For example, upstream device 504 can send data to controller by data routing 516, and upstream device 506 sends data to controller by data routing 518.This configuration can prevent the entanglement of the data that communication occurs may be due to data routing by shared time.
Fig. 6 and 7 shows for allowing between main process equipment and two upstream devices two optional configurations of the embodiment of the communication by individual interface.
Fig. 6 shows the hub chipsets 602 according to an embodiment.Hub chipsets comprises controller 604, bus 606 and interface 608.Interface forms two data routing 610(1) and 610(2).Data routing 610(1) ultra high speed signal can be worked as when data routing is coupled in the equipment 612 of USB3.0 ability and be passed to bus 606 by interface 608.Data routing 610(2) standard speed or high speed signal can be worked as when data routing is coupled in the equipment 614 of USB2.0 ability and be passed to bus 606 by interface 608.
Fig. 7 shows another embodiment of the hub chipsets in hub chipsets 702.Hub chipsets 702 comprises two controller 704(1) and 704(2) and interface 708.Interface can comprise two data routing 710(1) and 710(2).Data routing 710(1) ultra high speed signal can being worked as when data routing is connected to the equipment 712 of USB3.0 ability transmits by interface 708.Data routing 710(2) standard speed or high speed signal can being worked as when data routing is connected to the equipment 714 of USB2.0 ability transmits by interface 708.
Above-described realization allows single USB3.0 interface to be coupled in two different upstream devices and is provided with the gratifying of two upstream devices and communicated by letter by single USB3.0 interface.
Add up to, realization of the present invention provides shares single USB3.0 interface to connect the mode of two separated USB device.From another viewpoint, technology of the present invention provides the available circuit or the wire that make in USB3.0 host interface use special-purpose USB3.0 wire to connect USB3.0 equipment and use special-purpose USB2.0 wire to connect the mode of USB2.0 equipment.These technology make one that deviser can be in known connected equipment and support that USB3.0(for example has USB3.0 ability) design in whole USB3.0 port is not caused to waste.Therefore, these technology allow given design to provide more port to the hardware of given group than existing technology.
Although be described with architectural feature and/or the method distinctive language of taking action about the technology, method, equipment, system etc. of utilizing USB resource, it should be understood that, the theme limiting in the appended claims is not necessarily limited to described specific feature or action.More properly, specific feature and action are disclosed as realizing the exemplary form of the method advocated, equipment, system etc.

Claims (22)

1. an equipment, comprising:
At least one downstream interface,
Wherein each downstream interface is configured to be connected in equipment and the USB2.0 compatible equipment of USB3.0 ability simultaneously.
2. equipment according to claim 1, wherein said at least one downstream interface comprises first group of wire and second group of wire, the equipment that has USB3.0 ability described in wherein said first group of wire is configured to the USB3.0 signal to be sent to, and described second group of wire is configured to USB2.0 signal to be sent to described USB2.0 compatible equipment.
3. equipment according to claim 1, wherein said equipment also comprises the controller that is coupled in bus, and wherein said at least one downstream interface be included in described bus and described in have the first data routing and the second data routing between described bus and described USB2.0 compatible equipment between the equipment of USB3.0 ability.
4. equipment according to claim 3, wherein said the first data routing is separated and is different from each other with described the second data routing.
5. equipment according to claim 1, wherein said equipment also comprises the first controller and second controller, and wherein said at least one downstream interface comprises the first data routing and the second data routing, and wherein said the first data routing has the device coupled of USB3.0 ability in described the first controller by described, and described the second data routing is coupled in described second controller by described USB2.0 compatible equipment.
6. equipment according to claim 1, wherein said at least one downstream interface is configured to transmit described USB3.0 signal and described USB2.0 signal simultaneously.
7. equipment according to claim 1, wherein said equipment comprises console controller, hub controller, the SOC (system on a chip) that comprises console controller or the SOC (system on a chip) that comprises hub controller.
8. an equipment, comprising:
Upstream port; And
At least one downstream port, wherein each downstream port is configured to use USB3.0 signal to having the equipment of USB3.0 ability that the first connection is provided and using USB2.0 signal to provide the second connection to USB2.0 compatible equipment.
9. equipment according to claim 8, a wherein said USB3.0 connects and is independent of described the 2nd USB2.0 and connects.
10. equipment according to claim 8, communicates by letter when wherein said at least one downstream port allows described equipment to receive equipment from the described USB3.0 of having ability with described USB2.0 compatible equipment.
11. equipment according to claim 8, the equipment of the wherein said USB3.0 of having ability is video chipset, and described USB2.0 compatible equipment is Ethernet chip group.
12. equipment according to claim 8, also comprise USB controller, and wherein said USB controller is configured at the described USB3.0 signal of use and described USB3.0 devices communicating and uses between USB2.0 signal and described USB2.0 devices communicating replace.
13. equipment according to claim 8, also comprise the USB controller and the 2nd USB controller that are coupled in described each downstream port, described the first controller is configured to process described USB3.0 signal, and described second controller is configured to process described USB2.0 signal.
14. equipment according to claim 8, comprise usb hub or USB shunt.
15. 1 kinds of systems, comprising:
Usb hub equipment, it is arranged in housing and comprises Upstream Interface and at least one downstream interface; And
Each downstream interface, it has the first group of USB3.0 wire that is connected in USB3.0 compatible chipset and the second group of USB2.0 wire that is connected in USB2.0 compatible chipset.
16. systems according to claim 15, wherein said each downstream interface is configured to described USB3.0 compatible chipset the first data routing and the first memory buffer are provided and provide the second data routing and the second memory buffer to described USB2.0 compatible chipset.
17. systems according to claim 16, wherein said USB3.0 wire is welded in described USB3.0 compatible chipset, and described second group of USB2.0 wire is welded in described USB2.0 compatible chipset.
18. systems according to claim 15, wherein said usb hub equipment comprises controller, and wherein said first group of USB3.0 wire provides the first data routing between described USB3.0 compatible chipset and described controller, and wherein said second group of USB2.0 wire provides the second data routing between described USB2.0 compatible chipset and described controller.
19. systems according to claim 18, wherein said the first data routing and described the second data routing allow from described USB3.0 compatible chipset to described controller to communicate by letter with from described USB2.0 compatible chipset to described controller time.
20. systems according to claim 16, wherein said USB3.0 compatible chipset is to comprise the video chipset that is positioned at the video port on described housing, and wherein said USB2.0 compatible chipset is the Ethernet chip group that is included in the ethernet port on described housing.
21. 1 kinds of methods, comprising:
By downstream port, communicate by letter with USB3.0 compatible equipment; And
By described downstream port, communicate by letter with USB2.0 compatible equipment simultaneously.
22. one or more computer-readable recording mediums, it has instruction stored thereon, and described instruction realizes the method for claim 21 when being carried out by controller.
CN201310152801.5A 2013-04-27 2013-04-27 USB resource utilization method Pending CN104123259A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN201310152801.5A CN104123259A (en) 2013-04-27 2013-04-27 USB resource utilization method

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN201310152801.5A CN104123259A (en) 2013-04-27 2013-04-27 USB resource utilization method

Publications (1)

Publication Number Publication Date
CN104123259A true CN104123259A (en) 2014-10-29

Family

ID=51768674

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201310152801.5A Pending CN104123259A (en) 2013-04-27 2013-04-27 USB resource utilization method

Country Status (1)

Country Link
CN (1) CN104123259A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN105893295A (en) * 2016-04-22 2016-08-24 福州瑞芯微电子股份有限公司 Multiplexing system based on USB 3.0 port
WO2018049770A1 (en) * 2016-09-14 2018-03-22 广州视睿电子科技有限公司 Usb peripheral device
CN109473836A (en) * 2018-12-03 2019-03-15 苏州欧康诺电子科技股份有限公司 USB network hub

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20060179144A1 (en) * 2005-01-27 2006-08-10 Nec Electronics Corporation USB hub, USB-compliant apparatus, and communication system
US20090286421A1 (en) * 2008-05-15 2009-11-19 Seagate Technology Llc Data storage device compatible with multiple interconnect standards
US20100169511A1 (en) * 2008-12-31 2010-07-01 Dunstan Robert A Universal serial bus host to host communications
WO2012044937A1 (en) * 2010-09-30 2012-04-05 Cypress Semiconductor Corporation Utilizing usb resource

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20060179144A1 (en) * 2005-01-27 2006-08-10 Nec Electronics Corporation USB hub, USB-compliant apparatus, and communication system
US20090286421A1 (en) * 2008-05-15 2009-11-19 Seagate Technology Llc Data storage device compatible with multiple interconnect standards
US20100169511A1 (en) * 2008-12-31 2010-07-01 Dunstan Robert A Universal serial bus host to host communications
WO2012044937A1 (en) * 2010-09-30 2012-04-05 Cypress Semiconductor Corporation Utilizing usb resource

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN105893295A (en) * 2016-04-22 2016-08-24 福州瑞芯微电子股份有限公司 Multiplexing system based on USB 3.0 port
CN105893295B (en) * 2016-04-22 2019-07-09 福州瑞芯微电子股份有限公司 One kind being based on USB3.0 multiplexed port system
WO2018049770A1 (en) * 2016-09-14 2018-03-22 广州视睿电子科技有限公司 Usb peripheral device
CN109473836A (en) * 2018-12-03 2019-03-15 苏州欧康诺电子科技股份有限公司 USB network hub

Similar Documents

Publication Publication Date Title
US8645598B2 (en) Downstream interface ports for connecting to USB capable devices
CN107111588B (en) Data transfer using PCIe protocol via USB port
CN109558371B (en) Method for communicating with a microcontroller, and computing system
US9141152B2 (en) Interface card mount
CN203870529U (en) Universal serial bus server
US10162784B2 (en) Adapter for transmitting signals
JP7477237B2 (en) DisplayPort Alternate Mode Communication Detection
US9043528B2 (en) Bridge between a peripheral component interconnect express interface and a universal serial bus 3.0 device
US9760525B2 (en) Sideband signal consolidation fanout using a clock generator chip
CN108780430B (en) Sending Universal Serial Bus (USB) data over an alternate mode connection
US20080244141A1 (en) High bandwidth cable extensions
US20130124772A1 (en) Graphics processing
CN105068955A (en) Local bus structure and data interaction method
CN104123259A (en) USB resource utilization method
US10186010B2 (en) Electronic device and graphics processing unit card
WO2016200380A1 (en) Card edge connector couplings
EP3637270A1 (en) External electrical connector and computer system
US20140052883A1 (en) Expansion module and control method thereof
US20200285292A1 (en) Power adapters for component interconnect ports
JP2012058887A (en) Device equipment
US20140032802A1 (en) Data routing system supporting dual master apparatuses
CN104243173A (en) Interface configuration method, master card and high-speed daughter card
CN109582620A (en) A kind of UART interface conversion equipment and interface conversion method
CN107247677A (en) A kind of conversion equipment and electronic equipment
CN102567170B (en) Server blade mainboard test board

Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
WD01 Invention patent application deemed withdrawn after publication
WD01 Invention patent application deemed withdrawn after publication

Application publication date: 20141029