CN104123249B - A kind of new dynamic memory SDDR architecture arrays of serial access - Google Patents
A kind of new dynamic memory SDDR architecture arrays of serial access Download PDFInfo
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- CN104123249B CN104123249B CN201410349073.1A CN201410349073A CN104123249B CN 104123249 B CN104123249 B CN 104123249B CN 201410349073 A CN201410349073 A CN 201410349073A CN 104123249 B CN104123249 B CN 104123249B
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Abstract
The present invention relates to computer-readable storage medium, the new dynamic memory SDDR architecture arrays of specifically a kind of serial access.The present invention solves the problems, such as that active computer storage medium is difficult to further speed-raising and dilatation.A kind of new dynamic memory SDDR architecture arrays of serial access, including n roads SDDR memories, SDDR storage array controllers, computer host interface；Wherein, 1 SDDR controller, m SDDR memory node, m+1 UNI, 1 BoW are included per road SDDR memories；Each SDDR memory nodes include 1 SDDR memories control interface, 1 DDR controller, 1 DDR memory.The present invention is applied to computer and stored.
Description
Technical field
The present invention relates to computer-readable storage medium, the new dynamic memory SDDR framework battle arrays of specifically a kind of serial access
Row.
Background technology
Under prior art conditions, computer-readable storage medium is commonly the computer accessed based on parallel bus and stored and is situated between
Matter.Practice have shown that such a computer-readable storage medium constantly upgrades with itself, its own pin is more and more, thus causes it
It is difficult to further speed-raising and dilatation, so as to cause it can not meet higher and higher computer memory requirement.Based on this, it is necessary to
A kind of brand-new computer-readable storage medium is invented, is difficult to asking for further speed-raising and dilatation to solve active computer storage medium
Topic.
The content of the invention
The present invention in order to solve the problems, such as active computer storage medium be difficult to further speed-raising and dilatation, there is provided one kind
The new dynamic memory SDDR architecture arrays of serial access.
The present invention adopts the following technical scheme that realization：A kind of new dynamic memory SDDR framework battle arrays of serial access
Row, including n roads SDDR memories, SDDR storage array controllers, computer host interface；Wherein, it is equal per road SDDR memories
Including 1 SDDR controller, m SDDR memory node, m+1 UNI（Unified Node Interface, unified node
Interface）, 1 BoW（Bus only Write, a write bus）；Each SDDR memory nodes include 1 SDDR memory control
Interface processed, 1 DDR controller, 1 DDR memory；M DDR memory and m DDR controller one per road SDDR memories
One corresponding connection；Connected one to one per m DDR controller of road SDDR memories with m SDDR memory control interface；Often
M SDDR memories control interface of road SDDR memories connects one to one with wherein m UNI；Per road SDDR memories
SDDR controllers are connected with remaining 1 UNI；It is connected per m+1 UNI of road SDDR memories with BoW；Stored per road SDDR
The SDDR controllers of device are connected with SDDR storage array controllers；SDDR storage array controllers connect with computer host interface
Connect；N, m is positive integer.
Specific work process is as follows：
First, SDDR memories are initialized：Computer host interface will be initial by SDDR storage array controllers
Change order to send simultaneously to the SDDR controllers of n roads SDDR memories.Initialization command is packaged into message package by SDDR controllers,
And message package is sent to SDDR memory control interfaces by BoW.SDDR memory control interfaces parse to message package
And initialization command is extracted, then initialization command is sent to DDR controller.DDR controller is according to initialization command pair
DDR memory is initialized；
2nd, to SDDR memory write data：Computer host interface by the parallel data stream of 1 n-bit position send to
SDDR storage array controllers.The parallel data stream of 1 n-bit position is converted into n 1 bits by SDDR storage array controllers
Serial data stream, and the SDDR that the serial data stream of n 1 bits is respectively sent to n roads SDDR memories simultaneously is controlled
Device.The serial data stream of 11 bit is packaged into message package by SDDR controllers, and is sent message package to selected by BoW
In SDDR memory nodes SDDR memory control interfaces.SDDR memory control interfaces are parsed and carried to message package
The serial data stream of 11 bit is taken out, then by the converting serial data streams of 11 bit into parallel data stream, and will
Parallel data stream is sent to DDR controller.Parallel data stream is write DDR memory by DDR controller；
3rd, data are read from SDDR memories：The DDR controller of selected SDDR memory nodes is from DDR memory
Parallel data stream is read, and parallel data stream is sent to SDDR memory control interfaces.SDDR memories control interface will simultaneously
Row stream compression changes the serial data stream of 11 bit into, and the serial data stream of 11 bit is packaged into message package,
Then message package is sent to SDDR controllers by BoW.The SDDR controllers of n roads SDDR memories parse to message package
And the serial data stream of n 1 bits is extracted, then the serial data stream of n 1 bits is synchronously sent to SDDR and stored
Array control unit.SDDR storage array controllers by the converting serial data streams of n 1 bits into 1 n-bit position and line number
Sent according to stream, and by the parallel data stream of 1 n-bit position to computer host interface.
Based on said process, compared with active computer storage medium, a kind of serial access of the present invention it is new
Dynamic memory SDDR architecture arrays are no longer based on parallel bus access, but are accessed based on serial BoW, therefore even if DDR is deposited
Reservoir itself pin is more and more, and SDDR remains able to further speed-raising and dilatation, so as to fully meet higher and higher meter
Calculation machine memory requirement.
The present invention it is rational in infrastructure, ingenious in design, efficiently solve active computer storage medium be difficult to further speed-raising and
The problem of dilatation, stored suitable for computer.
Brief description of the drawings
Fig. 1 is the structural representation of the present invention.
Fig. 2 is the structural representation of the SDDR memory nodes of the present invention.
Embodiment
A kind of new dynamic memory SDDR architecture arrays of serial access, including n roads SDDR memories, SDDR storage battle array
Row controller, computer host interface；
Wherein, include per road SDDR memories 1 SDDR controller, m SDDR memory node, m+1 UNI, 1
BoW；
Each SDDR memory nodes include 1 SDDR memories control interface, 1 DDR controller, 1 DDR storage
Device；
Connected one to one per m DDR memory of road SDDR memories with m DDR controller；
Connected one to one per m DDR controller of road SDDR memories with m SDDR memory control interface；
Connected one to one per m SDDR memories control interface of road SDDR memories with wherein m UNI；
It is connected per the SDDR controllers of road SDDR memories with remaining 1 UNI；
It is connected per m+1 UNI of road SDDR memories with BoW；
It is connected per the SDDR controllers of road SDDR memories with SDDR storage array controllers；
SDDR storage array controllers are connected with computer host interface；
N, m is positive integer.
When it is implemented, the DDR memory is DDR memory or DDR2 memories or DDR3 memories or DDR4 storages
Device；The DDR controller is DDR controller or DDR2 controllers or DDR3 controllers or DDR4 controllers.
Claims (1)
- A kind of 1. new dynamic memory SDDR architecture arrays of serial access, it is characterised in that：Including n roads SDDR memories, SDDR storage array controllers, computer host interface；Wherein, 1 SDDR controller, m SDDR memory node, m+1 unified node are included per road SDDR memories to connect Mouth UNI, 1 write bus BoW；Each SDDR memory nodes include 1 SDDR memories control interface, 1 DDR controller, 1 DDR memory；Connected one to one per m DDR memory of road SDDR memories with m DDR controller；Connected one to one per m DDR controller of road SDDR memories with m SDDR memory control interface；The m SDDR memories control interface per road SDDR memories corresponds with wherein m unified node interface UNI to be connected Connect；SDDR controllers per road SDDR memories are connected with remaining 1 unified node interface UNI；The m+1 unified node interface UNI per road SDDR memories is connected with a write bus BoW；It is connected per the SDDR controllers of road SDDR memories with SDDR storage array controllers；SDDR storage array controllers are connected with computer host interface；N, m is positive integer.
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| CN201410349073.1A CN104123249B (en) | 2014-07-22 | 2014-07-22 | A kind of new dynamic memory SDDR architecture arrays of serial access |
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| CN201410349073.1A CN104123249B (en) | 2014-07-22 | 2014-07-22 | A kind of new dynamic memory SDDR architecture arrays of serial access |
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| CN104123249A CN104123249A (en) | 2014-10-29 |
| CN104123249B true CN104123249B (en) | 2018-03-09 |
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Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102272745A (en) * | 2009-01-08 | 2011-12-07 | 美光科技公司 | Memory system controller |
| CN103136162A (en) * | 2013-03-07 | 2013-06-05 | 太原理工大学 | ASIC (application specific integrated circuit) on-chip cloud architecture and design method based on same |
Family Cites Families (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7953931B2 (en) * | 1999-08-04 | 2011-05-31 | Super Talent Electronics, Inc. | High endurance non-volatile memory devices |
| US7366864B2 (en) * | 2004-03-08 | 2008-04-29 | Micron Technology, Inc. | Memory hub architecture having programmable lane widths |
| CN102012791B (en) * | 2010-10-15 | 2013-06-19 | 中国人民解放军国防科学技术大学 | Flash based PCIE (peripheral component interface express) board for data storage |
| CN102521200A (en) * | 2011-12-13 | 2012-06-27 | 四川赛狄信息技术有限公司 | System for configuring multi-processor in single Flash in embedded manner |
| CN103049397B (en) * | 2012-12-20 | 2015-09-16 | 中国科学院上海微系统与信息技术研究所 | A kind of solid state hard disc inner buffer management method based on phase transition storage and system |
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2014
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Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102272745A (en) * | 2009-01-08 | 2011-12-07 | 美光科技公司 | Memory system controller |
| CN103136162A (en) * | 2013-03-07 | 2013-06-05 | 太原理工大学 | ASIC (application specific integrated circuit) on-chip cloud architecture and design method based on same |
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