CN104102547B - The synchronous method and its sychronisation of multicomputer system - Google Patents
The synchronous method and its sychronisation of multicomputer system Download PDFInfo
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- CN104102547B CN104102547B CN201410359916.6A CN201410359916A CN104102547B CN 104102547 B CN104102547 B CN 104102547B CN 201410359916 A CN201410359916 A CN 201410359916A CN 104102547 B CN104102547 B CN 104102547B
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Abstract
The present invention relates to application and management process, operating procedure, release steps and the forwarding step of a kind of synchronous method of multicomputer system, including hardware lock.In the application and management process of hardware lock, hardware lock is managed and distributed by synchronizing management device, processor is no longer polled to hardware lock, improves the efficiency of multicomputer system processing affairs；When hardware lock is in upstate, after processor access, its state is automatically changeb to lock-out state, the processor obtains the hardware lock simultaneously, after simultaneously operating is completed, the state of the hardware lock is set to upstate, so as to reduce the number of communications between processor and hardware lock, improves the efficiency of multicomputer system processing affairs.In addition, the present invention also provides a kind of synchronizing management device of multicomputer system.
Description
Technical field
The present invention relates to field of computer technology, the synchronous method of more particularly to a kind of multicomputer system and its synchronous dress
Put.
Background technology
In a multi-processor system, processor usually requires to conduct interviews shared resource or synchronize mutually exclusive operation to be equal
Step operation using hardware lock to shared resource, it is necessary to be protected, to ensure shared resource at synchronization can only be by one
Device is managed to access.
In conventional multi-processor system, when processor needs to use a hardware lock, processor will go poll should
Hardware lock, " its state during upstate 0 ", is just set to " lock-out state 1 ", while it is hard to obtain this when finding that the hardware lock is in
Part is locked；If it find that the hardware lock be in " during lock-out state 1 ", just inquire about the state of this hardware lock again every for a period of time,
Constantly the hardware lock is polled.In this synchronization mechanism, processor is constantly polled for hardware lock, behaviour
Make that step is more, cause the efficiency of multicomputer system processing affairs to reduce, operation of the simultaneous processor to hardware lock for " read-alter-
Write " three communication back and forth is carried out between atomic operation, with hardware lock, also reduce the efficiency of multicomputer system processing affairs.
The content of the invention
The main object of the present invention is to provide a kind of synchronous method of multicomputer system, it is intended to improves multicomputer system
Handle the efficiency of affairs.
The bright another object of we is to provide a kind of sychronisation of multicomputer system, it is intended to improves multicomputer system
Handle the efficiency of affairs.
In order to realize above-mentioned main purpose, the synchronous method of multicomputer system provided by the invention, the multiprocessor system
System comprises at least two processors, and the synchronous method includes：The application of hardware lock and management process, synchronizing management device are receiving
After the request of application hardware lock is sent to processor, check in application record corresponding with the hardware lock whether there is its elsewhere
Manage the request of the device application hardware lock；If not provided, send confirmation to the processor；Otherwise the request of the processor is remembered
Record in application record and be sent to no lock information；Operating procedure, apply for that the processor of hardware lock is receiving confirmation
Afterwards, the state of the hardware lock is read, if the hardware lock is in upstate, the state of the hardware lock switchs to from upstate automatically
Lock-out state, apply for that the processor of the hardware lock obtains the hardware lock and carries out simultaneously operating；Release steps, when application hardware lock
Processor complete simultaneously operating after, the state of the hardware lock of occupancy is set to upstate and discharges the hardware lock, at the same to
Synchronizing management device sends the information of hardware lock release；Forwarding step, synchronizing management device are receiving the letter of hardware lock release
After breath, apply for that the processor of the hardware lock sends the information of hardware lock release into application record, and by corresponding application record
Reset.
From above scheme, due to hardware lock is managed and distributed by synchronizing management device, processor is no longer
Hardware lock is polled, improves the efficiency of multicomputer system processing affairs；In addition, if hardware lock is in " upstate
When 0 ", after processor access, its state be automatically changeb to " lock-out state 1 ", while the processor obtains the hardware lock,
After completing simultaneously operating, the state of the hardware lock is set to " upstate 0 ", compared with existing " read-modify-write " atomic operation,
Its need " read-write " atomic operation, the number of communications between processor and hardware lock is reduced, improve multicomputer system processing thing
The efficiency of business.
Specific scheme is in aforesaid operations step, if hardware lock is in the lock state, to apply for the processing of hardware lock
Device is to synchronizing management device dispatcher queue information, and synchronizing management device is after the queueing message of processor transmission is received, by this
The request of processor is recorded in the application record of corresponding hardware lock.
From above scheme, after processor accesses hardware lock, it is found that the hardware lock is in and " during lock-out state 1 ", pass through
To synchronizing management device dispatcher queue information, from by hardware lock etc. it is to be operated transfer synchronizing management device to, can carry out
Other operations, without being polled, improve the efficiency of multicomputer system processing affairs.
More specifically scheme is, in aforesaid operations step, applies for that the processor of hardware lock is sent out to synchronizing management device
After sending queueing message, the pending affairs in processing transaction queues are carried out, are receiving the hardware lock of synchronizing management device transmission
Release information is simultaneously disposed after Current transaction, sends the request for applying for the hardware lock to synchronizing management device again.
From above scheme, the processor of these dispatcher queue information is by handling the pending thing in transaction queues
Business, so as to improve the efficiency of multicomputer system processing affairs, and monitoring information of the synchronizing management device to hardware lock is waited, then
Applied for the hardware lock next time.
Preferable scheme is in aforesaid operations step, to apply for that the processor of hardware lock after no lock information is received, enters
Pending affairs in row processing transaction queues, receiving the information of the hardware lock release of synchronizing management device transmission and processing
After finishing Current transaction, the request for applying for the hardware lock is sent to synchronizing management device again.
From above scheme, these receive the processor of no lock information by handling latter pending affairs, so as to carry
The efficiency of high multicomputer system processing affairs, and monitoring information of the synchronizing management device to hardware lock is waited, then carry out next
Secondary application hardware lock.
Preferred scheme is that above-mentioned hardware lock includes trigger and door and NOT gate；The output end of trigger is connected to non-
The input of door, the output end of NOT gate is connected to the first input end with door, with the output end of door and the output end of clock signal
It is respectively connecting to two inputs of trigger；Application hardware lock processor read hardware lock state action be by with
Second input of door sends the status signal for the output end reading hardware lock for reading signal and slave flipflop to hardware lock；Processing
By the operation that the state of hardware lock is set to upstate triggered by the replacement input of trigger after device completes simultaneously operating
Flip-flop states are overturn；Trigger is level trigger or edge triggered flip flop.
From above scheme, the hardware lock, can be automatically from " upstate 0 " is changed into after processor access
" lock-out state 1 ", so as to realize that processor only needs to carry out " read-write " atomic operation, improve multicomputer system processing affairs
Efficiency.
In order to realize above-mentioned another object, the sychronisation of multicomputer system provided by the invention, the multiprocessor system
System includes at least two processors, and the sychronisation includes：Management by synchronization module, for being sent to Shen receiving processor
Please be after the request of hardware lock, whether check has other processor applications hardware lock in application record corresponding with the hardware lock
Request, if not provided, to the processor send confirmation, otherwise by the request of the processor be recorded in application record and to
It is sent without lock information；It is also, hard to this after receiving processor and sending the information of hardware lock release to management by synchronization module
Apply for that the processor of the hardware lock sends the information of hardware lock release in application record corresponding to part lock, and corresponding application is remembered
Record is reset；First judge module, the processor for applying for hardware lock read the shape of the hardware lock after confirmation is received
State, it is to be in upstate or lock-out state to judge the hardware lock；First operation module, judge for the first judge module
Hardware lock is that the state of the hardware lock switchs to lock-out state from upstate automatically, applies for the hardware lock when being in upstate
Processor obtain the hardware lock and carry out simultaneously operating；Release module, for being completed synchronously when the processor of application hardware lock
After operation, the state of the hardware lock of occupancy is set to upstate and discharged, while sent hardware lock to management by synchronization module and release
The information put.
Specific scheme is that the sychronisation of above-mentioned multicomputer system also includes the second operation module, sentences for first
When disconnected module judges that the hardware lock is in the lock state, apply for that the processor of hardware lock is believed to the dispatcher queue of management by synchronization module
Breath；Management by synchronization module is used for after the queueing message of processor transmission is received, and the request of the processor is recorded in correspondingly
In the application record of hardware lock.
More specifically scheme is that the sychronisation of above-mentioned multicomputer system also includes the 3rd operation module, the second judgement
Module and the 4th operation module；Wherein, the 3rd operation module is used to apply that the processor of hardware lock to be sent to synchronizing management device
After queueing message, the pending affairs in processing transaction queues are carried out；Second judge module receives lock-in tube for processor
After the information for managing the hardware lock release that module is sent, judge whether the processor is disposed Current transaction；4th operation module
Judge that processor is disposed after Current transaction for the second judge module, send application hardware to synchronizing management device again
The request of lock.
Preferable scheme also includes the 5th operation module, the 3rd judge module for the sychronisation of above-mentioned multicomputer system
And the 6th operation module；Wherein, the 5th operation module be used for that processor to receive that management by synchronization module sends without lock information after, enter
Pending affairs in row processing transaction queues；3rd judge module is used for processor and receives the hard of management by synchronization module transmission
After the information of part lock release, judge whether the Current transaction that is disposed；6th operation module is judged for the 3rd judge module
Processor is disposed after Current transaction, sends the request of application hardware lock to management by synchronization module again.
Preferred scheme is that above-mentioned hardware lock includes trigger and door and NOT gate；The output end of trigger is connected to non-
The input of door, the output end of NOT gate is connected to the first input end with door, with the output end of door and the output end of clock signal
It is respectively connecting to two inputs of trigger；Application hardware lock processor read hardware lock state action be by with
Another the second of door enters the status signal that hardware lock is read at end to the output end of hardware lock transmission reading signal and slave flipflop；Processing
By the operation that the state of hardware lock is set to upstate triggered by the replacement input of trigger after device completes simultaneously operating
Flip-flop states are overturn；Trigger is level trigger or edge triggered flip flop.
Brief description of the drawings
Fig. 1 is the workflow diagram of the synchronous method embodiment of multicomputer system of the present invention;
Fig. 2 is the structured flowchart of the sychronisation embodiment of multicomputer system of the present invention；
Fig. 3 be multicomputer system of the present invention sychronisation embodiment in hardware lock electrical schematic diagram；
Fig. 4 is clock signal CP in Fig. 3, reads signal In, hardware lock status signal Out, setting signal S and reset signal
R waveform voltage signal figure；
Fig. 5 is the state upset schematic diagram of Fig. 3 hardware locks.
Below in conjunction with drawings and the specific embodiments, the present invention is further illustrated.
Embodiment
The synchronous method embodiment of multiprocessing system
Referring to Fig. 1, the synchronous method of this multicomputer system is by application step S11, judgment step S12, allocation step
S13, the first judgment step S14, processing step S15, the second judgment step S16, operating procedure S17, release steps S18 and open
Disconnected step S19 is formed.
Apply for step S11, apply for that the processor of hardware lock closes local interruption, and it is hard to synchronizing management device transmission application
The request of part lock, skips to judgment step S12.
Whether judgment step S12, queuing corresponding to the hardware lock for judging to be applied in synchronizing management device have place in recording
Manage device and be lined up record, if so, being sent to processor without lock information and skipping to out interrupt step S19, if not having, skip to allocation step
S13。
Allocation step S13, synchronizing management device send confirmation to processor, skip to the first judgment step S14.
First judgment step S14, processor read hardware lock state, if " upstate 0 ", skip to the first operation step
Rapid S17, if " lock-out state 1 ", to synchronizing management device send application hardware lock queueing message and skip to processing step
S15。
Processing step S15, open processor and locally interrupt, processor carries out the place of the pending affairs in transaction queues
Reason, is disposed after Current transaction, skips to the second judgment step S16.
Second judgment step S16, judge whether to receive the information of the hardware lock release of synchronizing management device transmission, if receiving
Arrive, skip to application step S11, if not receiving, skip to processing step S15.
First operating procedure S17, access shared resource or synchronize mutually exclusive operation, skip to release steps S18.
Release steps S18, is set to that " upstate 0 " simultaneously discharges hardware lock, skips to out by the state write hardware lock
Interrupt step S19.
Interrupt step S19 is opened, opens the local interruption of the processor, processor carries out the pending affairs in transaction queues
Processing, be disposed Current transaction and receive synchronizing management device transmission hardware lock release information after, skip to application
Step S11.
The sychronisation embodiment of multicomputer system
Referring to Fig. 2, sychronisation 1 of the invention is by management by synchronization module 11, the first judge module 12, the first operation module
13rd, release module 14, the second operation module 15 form, the 3rd operation module 16, the second judge module 17, the 4th operation module
18th, the 5th operation module 19, the 3rd judge module 101 and the 6th operation module 102 are formed.
Management by synchronization module 11 is used for after receiving processor and being sent to apply for the request of hardware lock, checks hard with this
Whether the request of other the processor application hardware lock is had corresponding to part lock in application record, if not provided, being sent out to the processor
Confirmation is sent, otherwise the request of the processor is recorded in application record and is sent to no lock information.Management by synchronization mould
Block 11 is additionally operable to after receiving processor and being sent to the information of hardware lock release, into application record corresponding to the hardware lock
Apply for that the processor of the hardware lock sends the information of hardware lock release, and corresponding application record is reset.Management by synchronization module
11 are additionally operable to after the queueing message of processor transmission is received, and the request of the processor is recorded in the application of corresponding hardware lock
In record.
The processor that first judge module 12 is used to apply for hardware lock reads the hardware lock after confirmation is received
State, it is to be in " upstate 0 " or " lock-out state 1 " to judge the hardware lock.
First operation module 13 for the first judge module judge hardware lock be in " during upstate 0 ", the hardware
The state of lock is automatically from " upstate 0 " switchs to " lock-out state 1 ", apply for that the processor of the hardware lock obtains the hardware lock and gone forward side by side
Row simultaneously operating.
Release module 14 is used for after the processor for applying for hardware lock completes simultaneously operating, by the state of the hardware lock of occupancy
Be set to " upstate 0 " simultaneously discharges, at the same to management by synchronization module send hardware lock release information.
Second operation module 15 is judged that the hardware lock is in for the first judge module and " during lock-out state 1 ", applied hard
The processor of part lock is to management by synchronization module dispatcher queue information.
3rd operation module 16 is used to applying that the processor of hardware lock to after management by synchronization module dispatcher queue information, to be carried out
The processing of pending affairs in transaction queues.
After second judge module 17 is used for the information of hardware lock release that processor receives the transmission of management by synchronization module, sentence
Whether the processor that breaks is disposed Current transaction.
4th operation module 18 judges that processor is disposed after Current transaction for the second judge module, again to same
Walk the request that management module sends application hardware lock.
5th operation module 19 be used for that processor to receive that management by synchronization module sends without lock information after, carry out transaction queues
In pending affairs processing.
After 3rd judge module 101 is used for the information of hardware lock release that processor receives the transmission of management by synchronization module,
Judge whether the Current transaction that is disposed.
6th operation module 102 judges that processor is disposed after Current transaction for the 3rd judge module, again to
Management by synchronization module sends the request of application hardware lock.
Referring to Fig. 3, above-mentioned hardware lock is formed by trailing edge trigger 21, with door 22 and NOT gate 23.Trailing edge trigger 23
Output end be connected to the input of NOT gate 23, the output end of NOT gate 23 is connected to the first input end with door 22, with door 22
The output end of output end and clock signal is respectively connecting to two different inputs of trigger 21.
The action that the processor of above-mentioned application hardware lock reads the state of hardware lock be by the second input with door to
The output end of hardware lock transmission reading signal and slave flipflop reads the status signal of the hardware lock；Processor completes simultaneously operating
Afterwards, it is to trigger flip-flop states by the replacement input of trigger to turn over the state of hardware lock to be set into the operation of upstate
Turn.
Referring to Fig. 4, after system reset, the status signal Out of hardware lock is low level electric signal, i.e. hardware lock is in
" upstate 0 ", when status signal Out is high level signal, hardware lock is in " lock-out state 1 ".At the T1 moment, processor
The state of hardware lock is read, i.e., to the reading signal In that a high level pulse is sent with the second input of door 22, and from decline
Along the output end read state signal Out of trigger 21.At the T2 moment, clock signal CP trailing edge arrives, trailing edge triggering
The electric signal of the output end of device 21 is high level from low level upset, i.e., the state of hardware lock is from " automatic turning of upstate 0 " is
" lock-out state 1 ".At the T3 moment, another processor reads the state of the lock of the hardware, can not change the state of the hardware lock, and
The hardware lock is read from status signal Out and is in " lock-out state 1 ".At the T4 moment, the processor for taking the hardware lock is completed
After simultaneously operating, the state of trigger is set to by " upstate 0 " by reset signal R.
Referring to Fig. 5, after system reset, hardware lock is in and " upstate 0 ", the hardware lock is read when there is a processor
Afterwards, its state is from " automatic turning of upstate 0 " is " lock-out state 1 "；" during lock-out state 1 ", only accounted for when hardware lock is in
Could be by its state from " lock-out state 1 " is set to " upstate 0 ", other processors by resetting with the processor of the hardware lock
Any operation can not all change the state of the hardware.
In the above-described embodiments, the record sheet corresponding with the ID of hardware lock is established in synchronizing management device, for recording
Applied for the processor of the hardware lock.
In the above-described embodiments, each processor has a corresponding transaction queues, and place has been recorded in the transaction queues
The pending affairs that will be handled are managed, after processor can not be applied to hardware lock the affairs for being currently needed for processing,
Just carry out handling the current pending affairs for coming the first position in transaction queues, and the affairs for being currently needed for processing are placed on
First of transaction queues；If the pending affairs handled are also required to hardware lock and can not applied to hardware lock, to row
In transaction queues it is deputy it is pending handled, and the pending affairs being presently processing are come into transaction queues
Second, by that analogy.It can also be by establishing two task queues, and one is used to be lined up the affairs for needing to wait for hardware lock,
Another is used for the queuing of pending affairs.
In the above-described embodiments, the trigger of hardware lock can also be rising edge flip-flops, high level trigger and low electricity
Flat trigger.
Claims (10)
1. the synchronous method of multicomputer system, the multicomputer system includes at least two processors；
It is characterised in that it includes following steps：
The application of hardware lock and management process, synchronizing management device are sent to the request of application hardware lock receiving processor
Afterwards, whether check has the request of other processor applications hardware lock in corresponding with hardware lock application record；If not provided,
Confirmation is sent to the processor；Otherwise the request of the processor is recorded in application record and is sent to believe without lock
Breath；
Operating procedure, apply for that the processor of hardware lock after confirmation is received, reads the state of the hardware lock, if the hardware
Lock is in upstate, and the state of the hardware lock switchs to lock-out state from upstate automatically, applies for the processor of the hardware lock
Obtain the hardware lock and carry out simultaneously operating；
Release steps, after the processor for applying for hardware lock completes simultaneously operating, the state of the hardware lock of occupancy is set to available
State simultaneously discharges the hardware lock, while the information of hardware lock release is sent to synchronizing management device；
Forwarding step, synchronizing management device apply for the hardware lock into application record after the information of hardware lock release is received
Processor send the information of hardware lock release, and corresponding application record is reset；
The hardware lock includes trigger and door and NOT gate；
The output end of the trigger is connected to the input of the NOT gate, and the output end of the NOT gate is connected to described with door
First input end, the output end with the output end of door and clock signal are respectively connecting to two inputs of the trigger
End；
The action for the state that the processor of application hardware lock reads hardware lock be by it is described with the second input of door to described
Hardware lock sends the status signal for reading signal and the hardware lock being read from the output end of the trigger；
It is weight by the trigger by the operation that the state of hardware lock is set to upstate after processor completes simultaneously operating
Put input and trigger the flip-flop states upset.
2. the synchronous method of multicomputer system according to claim 1, it is characterised in that：
In the operating procedure, if hardware lock is in the lock state, apply for that the processor of hardware lock is sent out to synchronizing management device
Queueing message is sent, the request of the processor is recorded in by synchronizing management device after the queueing message of processor transmission is received
In the application record of corresponding hardware lock.
3. the synchronous method of multicomputer system according to claim 2, it is characterised in that：
In the operating procedure, apply for that the processor of hardware lock is post-processing affairs team to synchronizing management device dispatcher queue information
Pending affairs in row, receiving the information of the hardware lock release of synchronizing management device transmission and the Current transaction that is disposed
Afterwards, the request for applying for the hardware lock is sent to synchronizing management device again.
4. according to the synchronous method of any one of claims 1 to 3 multicomputer system, it is characterised in that：
In the operating procedure, apply for that the processor of hardware lock is pending in no lock information post processing transaction queues are received
Affairs, after the information of hardware lock release of synchronizing management device transmission and the Current transaction that is disposed is received, again to same
Walk managing device and send the request for applying for the hardware lock.
5. the synchronous method of multicomputer system according to claim 1, it is characterised in that：
The trigger is level trigger or edge triggered flip flop.
6. the sychronisation of multicomputer system, the multicomputer system includes at least two processors；
It is characterised in that it includes：
Management by synchronization module, for after receiving processor and being sent to apply for the request of hardware lock, checking and the hardware lock
Whether the request of other the processor application hardware lock is had in corresponding application record, if not provided, being sent to the processor true
Recognize information, otherwise the request of the processor is recorded in application record and is sent to no lock information；Also, receiving everywhere
After managing the information that device sends hardware lock release to management by synchronization module, apply for the hardware into application record corresponding to the hardware lock
The processor of lock sends the information of hardware lock release, and corresponding application record is reset；
First judge module, the processor for applying for hardware lock read the state of the hardware lock after confirmation is received,
It is to be in upstate or lock-out state to judge the hardware lock；
First operation module, judge that hardware lock is the state of hardware lock when being in upstate for the first judge module
Automatically switch to lock-out state from upstate, apply for that the processor of the hardware lock obtains the hardware lock and carries out simultaneously operating；
Release module, for after the processor for applying for hardware lock completes simultaneously operating, the state of the hardware lock of occupancy to be set to
Upstate is simultaneously discharged, while the information of hardware lock release is sent to management by synchronization module；
The hardware lock includes trigger and door and NOT gate；
The output end of the trigger is connected to the input of the NOT gate, and the output end of the NOT gate is connected to described with door
First input end, the output end with the output end of door and clock signal are respectively connecting to two inputs of the trigger
End；
The action for the state that the processor of application hardware lock reads hardware lock be by it is described with the second input of door to described
Hardware lock sends the status signal for reading signal and the hardware lock being read from the output end of the trigger；
It is weight by the trigger by the operation that the state of hardware lock is set to upstate after processor completes simultaneously operating
Put input and trigger the flip-flop states upset.
7. the sychronisation of multicomputer system according to claim 6, it is characterised in that：
Also include the second operation module, second operation module judges that the hardware lock is in locking for the first judge module
During state, apply the processor of hardware lock to management by synchronization module dispatcher queue information；
The management by synchronization module is used for after the queueing message of processor transmission is received, and the request of the processor is recorded in
In the application record of corresponding hardware lock.
8. the sychronisation of multicomputer system according to claim 7, it is characterised in that：
Also include the 3rd operation module, the second judge module and the 4th operation module；
3rd operation module is used to apply that the processor of hardware lock to post-process thing to management by synchronization module dispatcher queue information
The pending affairs being engaged in queue；
After second judge module is used for the information of hardware lock release that processor receives the transmission of management by synchronization module, judge
Whether the processor is disposed Current transaction；
4th operation module judges that processor is disposed after Current transaction for second judge module, again to
Management by synchronization module sends the request of application hardware lock.
9. according to the sychronisation of any one of claim 6 to 8 multicomputer system, it is characterised in that：
Also include the 5th operation module, the 3rd judge module and the 6th operation module；
5th operation module is used for processor and receives being post-processed without lock information in transaction queues for management by synchronization module transmission
Pending affairs；
After 3rd judge module is used for the information of hardware lock release that processor receives the transmission of management by synchronization module, judge
Whether be disposed Current transaction；
6th operation module judges that processor is disposed after Current transaction for the 3rd judge module, again to
Management by synchronization module sends the request of application hardware lock.
10. the sychronisation of multicomputer system according to claim 6, it is characterised in that：
The trigger is level trigger or edge triggered flip flop.
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| 在双端口SRAM中实现同步硬件原语;姚丽娜 等;《微计算机信息》;20080415;第24卷(第11期);第273页左栏第1行-第274页左栏第14行 * |
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| CN104102547A (en) | 2014-10-15 |
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