CN104090740A - Execution method for microcontroller instruction set - Google Patents
Execution method for microcontroller instruction set Download PDFInfo
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- CN104090740A CN104090740A CN201410228925.1A CN201410228925A CN104090740A CN 104090740 A CN104090740 A CN 104090740A CN 201410228925 A CN201410228925 A CN 201410228925A CN 104090740 A CN104090740 A CN 104090740A
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Abstract
The invention discloses an execution method for a microcontroller instruction set. The execution method comprises the following steps: carrying out instruction address computation by a microcontroller, obtaining the address of an instruction, to be executed, stored in a program counter, wherein the length of the address of the instruction is fixed 16 bits; carrying out a fetch instruction by the microcontroller, and obtaining the 16-bit instruction in the address of the instruction to be executed; coding by the microcontroller, translating a binary system operation code field in the 16-bit instruction into an output signal, and indicating the function of the instruction to be executed; carrying out address computation by the microcontroller, and obtaining the operand address in the instruction to be executed; obtaining one or more operands through the operand address, carrying out function operation appointed by the instruction on the one or more operands by the microcontroller; ending when no operand is returned; carrying out computation of the operand address if operands are returned. The coding for the instruction set adopts the length of fixed 16 bits, so that the speed of the fetch instruction is improved.
Description
Technical field
The present invention relates to the method for executing instruction operations, particularly, relate to a kind of manner of execution of microcontroller instruction set.
Background technology
Along with the development of embedded technology, be applied to real every field as the microcontroller of the core of function control nuclear information processing, microcontroller is to carry out process information in the mode of machine instruction, thereby can directly carry out various programs.Therefore, this process is actually and is completed by a series of machine instructions, and in microcontroller, the set of all instructions has formed microcontroller instruction set, and it should possess integrality, regularity, high-level efficiency and compatible feature.In the design process of micro controller system, the design of instruction set occupies very consequence, and reasonably instruction set is very important for the performance that improves microcontroller.
Although part microcontroller instruction set has adopted reduced instruction set computer (RISC) order set of more simplifying at present, but reasonably do not design on microcontroller, cause the complexity of order set, as the patent " microcontroller instruction set " (number of patent application 200480038058.X, publication number CN1898641A) of Mikrochip Technology Corp. application discloses a kind of instruction set of the behavior for the treatment of microcontroller.This patent has orthogonal (symmetry) instruction set, allows two file registers for the instruction of some two operands, and does not need by W register, and therefore strengthened performance and reduced the utilization factor of program storage.The weak point of this patent is: the addressing mode complexity of instruction set operand, has reduced instruction execution speed; Change between two file registers and transmit data although give up W register, with respect to the mode of setting up specially register file, be short of the dirigibility of certain storage data; Because program's memory space has 2M byte through amendment, therefore programmable counter (PC) is increased to 21 from 13, and cause the change of jump instruction form, to load 21 place values for programmable counter, destroy the coded system of instruction set fixed length, thus the complexity that coded system is become.
Summary of the invention
The object of the invention is to overcome the complicated problem that coded system becomes, the manner of execution of the simple microcontroller instruction set of a kind of coded system is provided.
To achieve these goals, the invention provides a kind of manner of execution of microcontroller instruction set, this instruction set is reduced instruction set and supports streamline to carry out, the method comprises: S101, microcontroller carries out instruction address calculating, obtain the address of an instruction will carrying out of depositing in programmable counter, the length of described instruction address is 16 that fix;
S102, in microcontroller access sheet, data space or the outer data space of sheet carry out instruction fetch, obtain 16 bit instructions in the instruction address that will carry out;
S103, microcontroller carries out the decoding of instruction operation code, and the binary operation code field in 16 bit instructions is translated into output signal, indicates the command function that needs execution;
S104, microcontroller carries out operand address calculating, obtains the address of operand in the instruction that will carry out;
S105, carries out fetch operand by microcontroller, obtains one or more operands by operand address;
S106, carries out operand feature operation by microcontroller, the one or more operands that obtain is carried out to the feature operation of instruction appointment;
S107, has judged whether to return operand, and in the time that nothing is returned to operand, instruction is finished; In the time returning to operand, microcontroller executable operations is counted address computation, obtains the operand address that need to return; And
S108, microcontroller is carried out and is deposited operand, and the result after command operating is delivered in storer or I/O register.
Preferably, the addressing mode of instruction operands comprises: single register directly address, pair register directly address, the directly address of I/O register, register indirect addressing and program storage addressing.
Further preferably, described interior data space comprises following interval: between the first interval, Second Region, the 3rd interval and the 4th interval, wherein, described the first interval is 16 general-purpose registers; Between described Second Region, be 32 special function registers; Described the 3rd interval is internal data memory; And described the 4th interval is stack space.
Further preferably, by the Address space mappinD of described general-purpose register in internal data memory.
Further preferably, last 6 the register combination of two by address sort in 16 general-purpose registers are formed respectively to following 3 address pointer registers: the first address pointer register, the second address pointer register and the 3rd address pointer register.
Further preferably, described the first address pointer register, the second address pointer register and the 3rd address pointer register are accessed data space or the outer data space of sheet in sheet by indirect addressing mode.
Further preferably, described the first address pointer register is set to ROM address pointer register in sheet; Described the second address pointer register is set to the outer address ram pointer register of sheet; Described the 3rd address pointer register is set to the outer ROM address pointer register of sheet.
Further preferably, by the pointer of any register of pointed of described the first address pointer register, described the second address pointer register and described the 3rd address pointer register.
Preferably, the content in outer sheet RAM storer is stored in general-purpose register by the indirect addressing of the second address pointer register and the pointer of the second address pointer register constant;
The pointer that stores content in general-purpose register into the outer ram register of sheet and the second address pointer register by the indirect addressing of the second address pointer register is constant;
The least-significant byte that stores the content in sheet internal program storer ROM into general-purpose register by the first address pointer register and get a word corresponding to this address packs in first object register, and most-significant byte packs in the next register of first object register; And
The least-significant byte that stores the content in outer sheet program memory ROM into general-purpose register by the 3rd address pointer register and get a word corresponding to this address packs in the second destination register, and most-significant byte packs in the next register of the second destination register.
Preferably, the method also comprises: by the instruction that needs redirect by comparison order to realize the function of redirect; When register value equates with setting value, carry out next instruction; When register value and setting value unequal, skip next instruction and carry out the instruction after next.
Pass through said method, described instruction set encoding is taked 16 bit lengths of fixing, not only be convenient to decoding, make fetching simple to operate, improve the speed of instruction fetch, also reduced the mistake in fetching operating process simultaneously, improve the reliability of system, described instruction set supports streamline to carry out, and has reduced microcontroller and has carried out the required clock period of instruction, has further improved the execution speed of instruction.
Other features and advantages of the present invention are described in detail the embodiment part subsequently.
Brief description of the drawings
Accompanying drawing is to be used to provide a further understanding of the present invention, and forms a part for instructions, is used from explanation the present invention, but is not construed as limiting the invention with embodiment one below.In the accompanying drawings:
Fig. 1 is the process flow diagram of the manner of execution of a kind of microcontroller instruction set of the preferred embodiment of the present invention;
Fig. 2 is the data memory addresses distribution diagram of the manner of execution of a kind of microcontroller instruction set of the preferred embodiment of the present invention;
Fig. 3 is the interior data-carrier store map of sheet of the manner of execution of a kind of microcontroller instruction set of the preferred embodiment of the present invention;
Fig. 4 is the register inter access sequential chart of the manner of execution of a kind of microcontroller instruction set of the preferred embodiment of the present invention;
Fig. 5 is the interior data store access sequential chart of sheet of the manner of execution of a kind of microcontroller instruction set of the preferred embodiment of the present invention;
Fig. 6 is program storage structure and the address space figure of the manner of execution of a kind of microcontroller instruction set of the preferred embodiment of the present invention;
The general register architecture schematic diagram of the manner of execution of a kind of microcontroller instruction set that Fig. 7 (a) is the preferred embodiment of the present invention;
Address register X, the Y of the manner of execution of a kind of microcontroller instruction set that Fig. 7 (b) is the preferred embodiment of the present invention, the structural representation of Z;
Fig. 8 is the special function register map listing of the manner of execution of a kind of microcontroller instruction set of the preferred embodiment of the present invention;
Fig. 9 be a kind of microcontroller instruction set of the preferred embodiment of the present invention manner of execution can bit addressing special function register list;
Figure 10 is the block scheme of the program status register of the manner of execution of a kind of microcontroller instruction set of the preferred embodiment of the present invention;
Figure 11 is the data transition diagram of the manner of execution of a kind of microcontroller instruction set of the preferred embodiment of the present invention; And
Figure 12 is the instruction encoding format chart of the manner of execution of a kind of microcontroller instruction set of the preferred embodiment of the present invention.
Embodiment
Below in conjunction with accompanying drawing, the specific embodiment of the present invention is elaborated.Should be understood that, embodiment described herein only, for description and interpretation the present invention, is not limited to the present invention.
Fig. 1 is the process flow diagram of the manner of execution of a kind of microcontroller instruction set of the preferred embodiment of the present invention; Fig. 2 is the data memory addresses distribution diagram of the manner of execution of a kind of microcontroller instruction set of the preferred embodiment of the present invention; Fig. 3 is the interior data-carrier store map of sheet of the manner of execution of a kind of microcontroller instruction set of the preferred embodiment of the present invention; Fig. 4 is the register inter access sequential chart of the manner of execution of a kind of microcontroller instruction set of the preferred embodiment of the present invention; Fig. 5 is the interior data store access sequential chart of sheet of the manner of execution of a kind of microcontroller instruction set of the preferred embodiment of the present invention; Fig. 6 is program storage structure and the address space figure of the manner of execution of a kind of microcontroller instruction set of the preferred embodiment of the present invention; The general register architecture schematic diagram of the manner of execution of a kind of microcontroller instruction set that Fig. 7 (a) is the preferred embodiment of the present invention; Address register X, the Y of the manner of execution of a kind of microcontroller instruction set that Fig. 7 (b) is the preferred embodiment of the present invention, the structural representation of Z; Fig. 8 is the special function register map listing of the manner of execution of a kind of microcontroller instruction set of the preferred embodiment of the present invention; Fig. 9 be a kind of microcontroller instruction set of the preferred embodiment of the present invention manner of execution can bit addressing special function register list; Figure 10 is the block scheme of the program status register of the manner of execution of a kind of microcontroller instruction set of the preferred embodiment of the present invention; Figure 11 is the data transition diagram of the manner of execution of a kind of microcontroller instruction set of the preferred embodiment of the present invention; And the instruction encoding format chart of the manner of execution of Figure 12 a kind of microcontroller instruction set that is the preferred embodiment of the present invention.
As shown in Figure 1, to achieve these goals, the invention provides a kind of manner of execution of microcontroller instruction set, this instruction set is reduced instruction set and supports streamline to carry out, the method comprises: S101, microcontroller carries out instruction address calculating, obtains the address of an instruction will carrying out of depositing in programmable counter, and the length of described instruction address is 16 that fix; S102, in microcontroller access sheet, data space or the outer data space of sheet carry out instruction fetch, obtain 16 bit instructions in the instruction address that will carry out; S103, microcontroller carries out the decoding of instruction operation code, and the binary operation code field in 16 bit instructions is translated into output signal, indicates the command function that needs execution; S104, microcontroller carries out operand address calculating, obtains the address of operand in the instruction that will carry out; S105, carries out fetch operand by microcontroller, obtains one or more operands by operand address; S106, carries out operand feature operation by microcontroller, the one or more operands that obtain is carried out to the feature operation of instruction appointment; S107, has judged whether to return operand, and in the time that nothing is returned to operand, instruction is finished; In the time returning to operand, microcontroller executable operations is counted address computation, obtains the operand address that need to return; And S108, microcontroller is carried out and is deposited operand, and the result after command operating is delivered in storer or I/O register.
Pass through said method, described instruction set encoding is taked 16 bit lengths of fixing, not only be convenient to decoding, make fetching simple to operate, improve the speed of instruction fetch, also reduced the mistake in fetching operating process simultaneously, improve the reliability of system, described instruction set supports streamline to carry out, and has reduced microcontroller and has carried out the required clock period of instruction, has further improved the execution speed of instruction.
In another embodiment, wherein perform step built-in function and reference-to storage or the I/O operation that can be divided into microcontroller.Step 1, microcontroller execution instruction address calculating operation, obtaining next that deposit in programmable counter needs the address of instruction of carrying out; Step 2, carries out instruction fetch operation, obtains 16 bit instructions in the instruction address that will carry out; Step 3, executing instruction operations decoding, translates into control signal by the binary operation code field in instruction, indicates the command function that needs execution; Step 4, executable operations is counted address computation, obtains the address of operand in the instruction that will carry out; Step 5, carries out fetch operand, obtains the operand information needing according to the address of instruction operands, it should be noted that the difference according to instruction, and the operand obtaining has one or two; Step 6, executing data operation, carries out one or two data of obtaining the feature operation of instruction appointment, if when command function end of operation and nothing are returned to operand, return to execution step one, if desired returns to operand and carries out next step; Step 7, executable operations is counted address computation, obtains the address that need to return to operand; Step 8, operand is deposited in execution, result after command operating is delivered in storer or I/O, after a final instruction is finished, again performed step one operation, pass through above-mentioned steps, described instruction set encoding is taked 16 bit lengths of fixing, not only be convenient to decoding, make fetching simple to operate, improve the speed of instruction fetch, also reduced the mistake in fetching operating process, improved the reliability of system simultaneously.
In one embodiment, the addressing mode of instruction operands comprises: single register directly address, pair register directly address, the directly address of I/O register, register indirect addressing and program storage addressing, in above 5, addressing mode, by simplifying complicated addressing mode taking addressing between register as main mode has improved access speed, has reduced the generation of pipelining conflict.The addressing mode of instruction operands mainly contains following five kinds: single register directly address, and specify the content of a register Rd as operand by instruction, the address realm of addressing is the register file of specifying; Pair register directly address, similar with single register addressing, two register Rd that instruction is pointed out and the content of Rr are as operand, and result leaves in Rd register; The directly address of I/O register, specifies the content of an I/O register as first operand by instruction, and second operand is Rd or Rr, by the data of IN and OUT instruction read-write I/O register; Register indirect addressing, utilizes eight bit register in register file or the 16 bit register Y address pointer register as RAM (256B) and maximum RAM (64K), uses LOAD and STORE instruction access data memory space; The addressing mode of program storage, the scope that the absolute jump instruction JMP in the design can redirect is whole ROM (8K) space, jump instruction RJMP also can jump to any place in ROM (8K) space up and down relatively.
In another embodiment, data space can comprise following interval in sheet: between the first interval, Second Region, the 3rd interval and the 4th interval, wherein, described the first interval is 16 general-purpose registers; Between described Second Region, be 32 special function registers; Described the 3rd interval is internal data memory; And described the 4th interval is stack space.As shown in Figure 2, the Address Allocation's Situation of data-carrier store is as described below, the data of each address storage 8bit, in sheet, data space, from 00H～FFH, is total to 256B, 00H～0FH is that first interval 16 general-purpose registers are used, 10H～2FH is that between Second Region, 32 special function registers are used, and 30H～XXH is the 3rd interval internal RAM data memory space, and XXH～FFH is the 4th interval stack space, the outer data space of sheet, from 0000H～FFFFH, is total to 8KB.Wherein 16 general-purpose registers and 32 special function registers are mapped in data space, as shown in Figure 3.
One preferred embodiment in, described general-purpose register is mapped to internal data memory, use as general-purpose register, can be used for the operand of arithmetic operator, also can be used for address register stores intermediate address or data register and carry out data transmission.
It should be noted that, in the above-described embodiment, in the time carrying out the instruction of access internal register, get register manipulation number, execution arithmetic logic unit (ALU) operation and result write-back and complete within 1 clock period, therefore total execution time is 1 cycle, as shown in Figure 4.In the time carrying out the instruction of data-carrier store in access sheet, first calculate the storage address that needs access, the operation just reading and writing data in the time that address is effective, the operation that is reference-to storage is longer with respect to the time of access register, conventionally need 2 clock period, memory access sequential is as Fig. 5.
One preferred embodiment in, will in 16 general-purpose registers, be finally that 6 register combination of two at end, described the first interval form respectively following 3 address pointer registers: the first address pointer register X, the second address pointer register Y and the 3rd address pointer register Z by address sort.Wherein, 16 register mappings, to internal data memory, are used as general-purpose register, can be used for the operand of arithmetic operator, also can be used for address register stores intermediate address or data register and carry out data transmission.Wherein, R10:R11, R12:R13, R14:R15 form respectively address pointer register X, Y, the Z of 3 16, realize the access of data space by indirect addressing.X is as ROM address pointer register in sheet, and Y is as the outer address ram pointer register of sheet, and Z is as the outer ROM address pointer register of sheet, and these 3 address pointer registers can be set to point to the pointer of any register, and generally not as other purposes.General register architecture and X wherein, Y, Z address pointer register structure are as shown in Fig. 7 (a) and Fig. 7 (b).In instruction set of the present invention, all general-purpose register operational orders are all with directive, and can in the single clock cycle, access all registers.Each register has a data memory address, they is mapped directly to 16 addresses of data memory space.Although the physics realization of register file is not RAM, this memory organization mode has great dirigibility aspect access register, because X, Y, Z address pointer register can be set to point to the pointer of any register.In the time using coding, should note the difference between these 16 general-purpose registers.The access of data space is realized by instruction LD and ST, and this is the feature of risc type microcontroller, is to realize by LD and two instructions of ST to the access of storer.By X to the access of data space in the present invention, Y, Z address register does a location addressing and realizes.
In the above-described embodiment, relate to the instruction feature of 3 address pointer register X, Y, Z as follows:
1, utilize Y indirect addressing to store RAM content into register (the outer RAM of sheet),
Instruction mnemonic: LD Rd, Y
Function: the data in the outer RAM of the sheet that is Y by pointer are sent register, and pointer is constant.
Operand: 0≤Rd≤15
Operation: Rd ← (Y)
Machine code: 1111_1000_0000_XXXX
Impact on zone bit: nothing
A kind of concrete embodiment is:
LD?R1，Y
Before instruction is carried out:
R1＝？
(Y)＝2FH
After instruction is carried out:
R1＝2FH
(Y)＝2FH
2, utilize Y indirect addressing to store content of registers into RAM (the outer RAM of sheet)
Instruction mnemonic: ST Y, Rr
Function: sending Y by content of registers is that in the outer RAM of sheet of pointer, Y pointer does not change.
Operand: 0≤Rr≤15
Operation: (Y) ← Rr
Machine code: 1111_1000_0001_XXXX
Impact on zone bit: nothing
A kind of concrete embodiment is:
ST?Y，R1
Before instruction is carried out:
R1＝0AH
(Y)＝？
After instruction is carried out:
R1＝0AH
(Y)＝0AH
3, utilize the X load register (sheet in ROM) of peeking from program memory ROM
Instruction mnemonic: LD Rd, X
Function: utilize the interior ROM of the sheet address of X address pointer register storage, the least-significant byte of getting a word corresponding to this address packs in destination register Rd, and most-significant byte packs in Rd+1.
Operand: 0≤Rd≤15
Operation: Rd+1:Rd ← (X)
Machine code: 1111_1000_0010_XXXX
Impact on zone bit: nothing
A kind of concrete embodiment is:
LD?R1，X
Before instruction is carried out:
R1＝？
R2＝？
(X)＝A17CH
After instruction is carried out:
R1＝7CH
R2＝A1H
(X)＝A17CH
4, utilize the Z load register (ROM outside sheet) of peeking from program memory ROM
Instruction mnemonic: LD Rd, Z
Function: utilize the outer ROM of the sheet address of Z address pointer register storage, the least-significant byte of getting a word corresponding to this address packs in destination register Rd, and most-significant byte packs in Rd+1.
Operand: 0≤d≤12
Operation: Rd+1:Rd ← (Z)
Machine code: 1111_1000_0011_XXXX
Impact on zone bit: nothing
A kind of concrete embodiment is:
LD?R1，Z
Before instruction is carried out:
R1＝？
R2＝？
(Z)＝5B37H
After instruction is carried out:
R1＝37H
R2＝5BH
(Z)＝5B37H
5, word adds immediate
Instruction mnemonic: ADW Rdl, #data6
Function: the same immediate of register pair (word) (0～63) is added, and result is put into register team pair.
Operand: Rdl:00,01,10, can represent with X, Y, Z 0≤#data6≤63
Operation: X/Y/Z ← X/Y/Z+data6
Machine code: 1110_0111_XXXX_XXXX
Impact on zone bit: H S V N Z C
A kind of concrete embodiment is:
ADW?X，1AH
Before instruction is carried out:
(X)＝6230H
After instruction is carried out:
(X)＝624AH
6, word subtracts immediate
Instruction mnemonic: SBW Rdl, #data6
Function: the same immediate of register pair (word) (0～63) is subtracted each other, and result is put into register team pair.
Operand: Rdl:00,01,10, can represent with X, Y, Z 0≤#data6≤63
Operation: X/Y/Z ← X/Y/Z-data6
Machine code: 1110_1010_XXXX_XXXX
Impact on zone bit: H S V N Z C
A kind of concrete embodiment is:
SBW?Z，15H
Before instruction is carried out:
(Z)＝0029H
After instruction is carried out:
(Z)＝0014H
7, redirect indirectly
Instruction mnemonic: IJMP
Function: indirectly jump to 16 bit address that Z pointer register points to.Z pointer register is 16 bit wides, allows redirect in present procedure storage space 64K word (128K byte).
Operand: nothing
Operation: PC ← Z
Machine code: 1111_1000_1111_0000
Impact on zone bit: nothing
A kind of concrete embodiment is:
Addr0：IJMP
Addr1：
Addr2：
Before instruction is carried out:
PC＝Addr0
Z＝Addr2
After instruction is carried out:
PC＝Addr2
Z＝Addr2
8, indirect call
Instruction mnemonic: ICALL
Function: the subroutine that indirect call is pointed to by (16 bit pointer register) in Z register.Address pointer register Z is 16, allows to be invoked at the subroutine in present procedure storage space 64K word (128K byte).
Operand: nothing
Operation: STACK ← PC+1, SP ← SP-2, PC ← Z
Machine code: 1111_1000_1111_0001
Impact on zone bit: nothing
A kind of concrete embodiment is:
Addr0：ICALL
Addr1：
Addr2：
Before instruction is carried out:
PC＝Addr0
STACK＝？
SP＝FFH
Z＝Addr2
After instruction is carried out:
PC＝Addr2
STACK＝Addr1
SP＝FDH
Z＝Addr2
In one embodiment, instruction set can addressing sheet internal program storer be 64K, the instruction of each address storage 16bit, sheet internal program storage space 0000H～1FFFH, wherein 0000H～0003H storage interrupt vector address, 0004H～XXXXH storage needs the program of carrying out, and XXXXH～1FFFH stores read-only data.The outer program storage of sheet is 128K, the instruction of 16bit is also stored in each address, the outer program memory space 0000H～FFFFH of sheet, the same with sheet internal program storer, 0000H～0003H storage interrupt vector address, 0004H～XXXXH storage needs the program of carrying out, and XXXXH～FFFFH stores read-only data.The structure of the outer program storage of sheet internal program storer and sheet and address space are as shown in Figure 6.
In one embodiment, Fig. 8 is special function register map listing, has shown the service condition of special function register in data-carrier store, and front 28 addresses are used for respectively depositing each special function register used, rear 8 addresses retain, so that the expansion of microcontroller.Wherein, status register SREG is used for depositing the state of the zone bit affecting in program operation process, and when some zone bits are " 1 ", the represented state of this zone bit is effective; Port register PORTA, PORTB, PORTC store respectively the 8bit data that input or output; Port data direction register DDRA, DDRB, the DDRC direction that storage port data are transmitted respectively, judge that by it data are output or input; The address of the program that the lower bar of programmable counter PC storage will be carried out; The address of stacked, to go out stack operation instruction is carried out in stack register SP storage; The instruction that order register IR storage is being carried out; Timer/counter mode mask register TMOD is used for the working method of control timer/counter T0 and T1; Timer/counter control register TCON be used for the opening of control timer/counter T0 and T1, stop, overflow indicator and external interrupt signal triggering mode; Timer 0 and timer 1 counter register storage are for the 16bit data of timing and counting; Serial Port Control register SCON is used for controlling and indicates the mode of serial data communication to select, receive and send the status indicator of control and serial port; Power supply control register PCON is for controlling the duty of power supply; Serial ports buffer register SBUF is for the temporary data that input or output serial ports; Interrupt allowing control register IE for controlling opening or the shielding of microcontroller to interrupt source, and whether each interrupt source allow to interrupt; Interrupt priority level control register IP is for the control bit of each interrupt source priority of latch.Fig. 9 be can bit addressing special function register list, in 32 special function registers, only have SREG, PORTA, PORTB, PORTC, TCON, SCON, PCON, IE, IP can carry out bit addressing operation, wherein each of each special function register distributes a bit address for bit addressing, if exceed the operation of bit addressing scope, be considered as disable instruction, will not carry out.
In one embodiment, status register SREG is a 8bit flag register, is used for depositing the mark that has off status and result after instruction is carried out.In status register, bit states normally produces in the implementation of instruction, but also can be according to user need to use special instruction change.Figure 10 is the block scheme of status register, is followed successively by from high to low: carry flag bit C; Result is zero flag position Z; Result is negative zone bit N; 2 complement code Overflow flag V; N ⊕ V, for the zone bit S of sign test; In operation, produce the zone bit H of half carry; User Defined zone bit I.
One preferred embodiment in, described the first address pointer register X, the second address pointer register Y and the 3rd address pointer register Z access in sheet data space or the outer data space of sheet by indirect addressing mode.
Figure 11 is the data transition diagram of instruction set of the present invention, because the present invention has adopted RISC system, adopt the register file of 16 register compositions, therefore make most operational order all between register, carry out, improve microcontroller processing speed, thereby a register can be carried out alternately with another register, and the while, address register X, Y, Z wherein had identical function.In immediate and sheet, data-carrier store RAM can directly carry out with register the transmission of data, and the outer data-carrier store RAM of sheet could transmit data after need to doing indirect addressing by address register Y.After in sheet or outside sheet, program memory ROM also needs to do indirect addressing by address register X and Z simultaneously, ability is in energy move instruction.
In order to realize the present invention, in one embodiment, the elementary instruction of microcontroller is made up of two parts, i.e. operational code and operand, and operational code has indicated the action type that microcontroller need to be carried out, and operand has indicated the amount of carrying out computing in instruction.As shown in figure 12, be the instruction encoding format chart of instruction set of the present invention, instruction set is taked 16 bit lengths of fixing, not only be convenient to decoding, make fetching simple to operate, improve the speed of instruction fetch, also reduced the mistake in fetching operating process, improved the reliability of system simultaneously.Wherein, it should be noted that due to the difference of the figure place of the Different Effects operational code of operand figure place, can be divided into 4 bit manipulation codes, 8 bit manipulation codes, 12 bit manipulation codes and four kinds of instruction encoding forms of 16 bit manipulation codes.The operand field that table 1 is instruction set of the present invention is described list.
Table 1
In the present invention, instruction set comprises totally 58 instructions of data movement instruction, operational order, the instruction of controls metastasis class, bit manipulation instruction and other instructions 5 classes.Table 2 is the data movement instruction list of microcontroller instruction set, comprises general move instruction (MOV, LD, ST), IO mouth move instruction (IN, OUT) and stack instruction (PUSH, POP).Table 3 is the operational order list of microcontroller instruction set, comprises add instruction (ADD, ADC, ADW, INC), subtraction instruction (SUB, SBC, SBW, DEC), multiplying order (MUL), divide instruction (DIV), logical and instruction (AND), logical OR instruction (OR), logic XOR instruction (XOR), gets complement instruction (NEG).Table 4 is the control transfer instruction of microcontroller instruction set, comprises jump instruction (JMP, RJMP, IJMP), call instruction (CALL, RCALL, ICALL), link order (RET, RETI), comparison order (CPE, CPNE, SBRZ, SBRO, SBSZ, SBSO).Table 5 is microcontroller instruction set bit manipulation instruction and other instructions, comprises left shift instruction (LSL, ROL), right shift instruction (LSR, ROR, ASR), nibble exchange instruction (SWAP), set instruction (BSET), clear " 0 " instruction (BCLR), non-operation instruction (NOP).
Table 2
Table 3
Table 4
Table 5
In one embodiment, described the first address pointer register is set to ROM address pointer register in sheet; Described the second address pointer register is set to the outer address ram pointer register of sheet; Described the 3rd address pointer register is set to the outer ROM address pointer register of sheet.
One preferred embodiment in, by the pointer of any register of pointed of described the first address pointer register, described the second address pointer register and described the 3rd address pointer register.
In one embodiment, the content in outer sheet RAM storer is stored in general-purpose register by the indirect addressing of the second address pointer register and the pointer of the second address pointer register constant; The pointer that stores content in general-purpose register into the outer ram register of sheet and the second address pointer register by the indirect addressing of the second address pointer register is constant; The least-significant byte that stores the content in sheet internal program storer ROM into general-purpose register by the first address pointer register and get a word corresponding to this address packs in first object register, and most-significant byte packs in the next register of first object register; And the least-significant byte that stores the content in outer sheet program memory ROM into general-purpose register by the 3rd address pointer register and get a word corresponding to this address packs in the second destination register, most-significant byte packs in the next register of the second destination register.
One preferred embodiment in, the method also comprises: by the instruction that needs redirect by comparison order to realize the function of redirect; When register value equates with setting value, carry out next instruction; When register value and setting value unequal, skip next instruction and carry out the instruction after next.
Above-mentioned preferred embodiment in, compared with the conditional branch instruction of traditional microcontroller instruction set, instruction set conditional branch instruction of the present invention does not provide address or the side-play amount of redirect, but in the situation that meeting comparison condition, skip the instruction that next will be carried out, while not meeting comparison condition, order is carried out next instruction, can in next of a conditional branch instruction instruction, place jump instruction and determine and need the address of redirect or side-play amount, the instruction feature that relates to conditional transfer is as follows:
1, register comparison, equal skip next instruction (do not wait can carry out redirect)
Instruction mnemonic: CPE Rd, Rr
Function: this instruction completes the comparison of two register Rd and Rr, if Rd=Rr jumps a line and carries out instruction.
Operand: 0≤Rd≤15,0≤Rr≤15
Operation: If Rd=Rr then PC ← PC+2 (or3) else PC ← PC+1
Machine code: 1111_0000_XXXX_XXXX
Impact on zone bit: nothing
A kind of concrete embodiment is:
Addr0：CPE?R1，R2
Addr1：
Addr2：
Before instruction is carried out:
PC＝Addr0
R1＝3DH
R2＝3DH
After instruction is carried out:
PC＝Addr2
R1＝3DH
R2＝3DH
2, register comparison, unequally skips next instruction (equate can carry out redirect)
Instruction mnemonic: CPNE Rd, Rr
Function: this instruction completes the comparison of two register Rd and Rr, if Rd ≠ Rr jumps a line and carries out instruction.
Operand: 0≤Rd≤15,0≤Rr≤15
Operation: If Rd ≠ Rr then PC ← PC+2 (or3) else PC ← PC+1
Machine code: 1111_0001_XXXX_XXXX
Impact on zone bit: nothing
A kind of concrete embodiment is:
Addr0：CPNE?R1，R2
Addr1：
Addr2：
Before instruction is carried out:
PC＝Addr0
R1＝75H
R2＝2AH
After instruction is carried out:
PC＝Addr2
R1＝75H
R2＝2AH
3, register-bit is skipped next instruction for " 0 "
Instruction mnemonic: SBRZ Rd, bit
Function: this instruction testing register bit position, if this position is cleared, jumps a line and carry out instruction.
Operand: 0≤Rr≤15,0≤bit≤7
Operation: If Rd (bit)=0then PC ← PC+2 (or3) else PC ← PC+1
Machine code: 1111_0010_XXXX_-XXX
Impact on zone bit: nothing
A kind of concrete embodiment is:
Addr0：SBRZ?R1，0
Addr1：
Addr2：
Before instruction is carried out:
PC＝Addr0
R1＝0000_1110
After instruction is carried out:
PC＝Addr2
R1＝0000_1110
4, register-bit is skipped next instruction for " 1 "
Instruction mnemonic: SBRO Rd, bit
Function: this instruction testing register b position, if this position is set, jumps off a line and carry out instruction.
Operand: 0≤Rr≤15,0≤bit≤7
Operation: If Rd (bit)=l then PC ← PC+2 (or3), else PC ← PC+l
Machine code: 1111_0011_XXXX_-XXX
Impact on zone bit: nothing
A kind of concrete embodiment is:
Addr0：SBRO?R1，2
Addr1：
Addr2：
Before instruction is carried out:
PC＝Addr0
R1＝0000_1110
After instruction is carried out:
PC＝Addr2
R1＝0000_1110
5, next instruction is skipped for " 0 " in special function register position
Instruction mnemonic: SBSZ bit_addr
Function: this instruction testing special function register specific bit, if this position is cleared, jumps a line and carry out instruction.
Operand: 00≤bit_addr≤47
Operation: If (bit_addr)=0then PC ← PC+2 (or3), else PC ← PC+1
Machine code: 1111_0100_XXXX_XXXX
Impact on zone bit: nothing
A kind of concrete embodiment is:
Addr0：SBSZ0FH
Addr1：
Addr2：
Before instruction is carried out:
PC＝Addr0
0FH：PORTA＝0
After instruction is carried out:
PC＝Addr2
0FH：PORTA＝0
6, next instruction is skipped for " 1 " in special function register position
Instruction mnemonic: SBSO bit_addr
Function: this instruction testing special function register specific bit, if this position is set, jumps a line and carry out instruction.
Operand: 00≤bit_addr≤47
Operation: If (bit_addr)=l then PC ← PC+2 (or3), else PC ← PC+1
Machine code: 1111_0101_XXXX_XXXX
Impact on zone bit: nothing
A kind of concrete embodiment is:
Addr0：SBSO2EH
Addr1：
Addr2：
Before instruction is carried out:
PC＝Addr0
2EH：SM1＝1
After instruction is carried out:
PC＝Addr2
2EH：SM1＝1
Below describe by reference to the accompanying drawings the preferred embodiment of the present invention in detail; but; the present invention is not limited to the detail in above-mentioned embodiment; within the scope of technical conceive of the present invention; can carry out multiple simple variant to technical scheme of the present invention, these simple variant all belong to protection scope of the present invention.
It should be noted that in addition, each concrete technical characterictic described in above-mentioned embodiment, in reconcilable situation, can combine by any suitable mode, for fear of unnecessary repetition, the present invention is to the explanation no longer separately of various possible array modes.
In addition, also can carry out combination in any between various embodiment of the present invention, as long as it is without prejudice to thought of the present invention, it should be considered as content disclosed in this invention equally.
Claims (10)
1. a manner of execution for microcontroller instruction set, is characterized in that, this instruction set is that reduced instruction set computer (RISC) and support streamline are carried out, and the method comprises:
S101, microcontroller carries out instruction address calculating, obtains the address of an instruction will carrying out of depositing in programmable counter, and the length of described instruction address is 16 that fix;
S102, in microcontroller access sheet, data space or the outer data space of sheet carry out instruction fetch, obtain 16 bit instructions in the instruction address that will carry out;
S103, microcontroller carries out the decoding of instruction operation code, and the binary operation code field in 16 bit instructions is translated into output signal, indicates the command function that needs execution;
S104, microcontroller carries out operand address calculating, obtains the address of operand in the instruction that will carry out;
S105, carries out fetch operand by microcontroller, obtains one or more operands by operand address;
S106, carries out operand feature operation by microcontroller, the one or more operands that obtain is carried out to the feature operation of instruction appointment;
S107, has judged whether to return operand, and in the time that nothing is returned to operand, instruction is finished; In the time returning to operand, microcontroller executable operations is counted address computation, obtains the operand address that need to return; And
S108, microcontroller is carried out and is deposited operand, and the result after command operating is delivered in storer or I/O register.
2. the manner of execution of a kind of microcontroller instruction set according to claim 1, it is characterized in that, the addressing mode of described manner of execution comprises: single register directly address, pair register directly address, the directly address of I/O register, register indirect addressing and program storage addressing.
3. the manner of execution of a kind of microcontroller instruction set according to claim 1, it is characterized in that, described interior data space comprises following interval: between the first interval, Second Region, the 3rd interval and the 4th interval, wherein, described the first interval is 16 general-purpose registers; Between described Second Region, be 32 special function registers; Described the 3rd interval is internal data memory; And described the 4th interval is stack space.
4. the manner of execution of a kind of microcontroller instruction set according to claim 3, is characterized in that, by the Address space mappinD of described general-purpose register in described internal data memory.
5. the manner of execution of a kind of microcontroller instruction set according to claim 3, it is characterized in that, last 6 the register combination of two by address sort in described 16 general-purpose registers are formed respectively to following 3 address pointer registers: the first address pointer register, the second address pointer register and the 3rd address pointer register.
6. the manner of execution of a kind of microcontroller instruction set according to claim 5, it is characterized in that, described the first address pointer register, described the second address pointer register and described the 3rd address pointer register are accessed data space or the outer data space of sheet in sheet by indirect addressing mode.
7. the manner of execution of a kind of microcontroller instruction set according to claim 5, is characterized in that, described the first address pointer register is set to ROM address pointer register in sheet; Described the second address pointer register is set to the outer address ram pointer register of sheet; Described the 3rd address pointer register is set to the outer ROM address pointer register of sheet.
8. the manner of execution of a kind of microcontroller instruction set according to claim 7, it is characterized in that, by the pointer of any register of pointed of described the first address pointer register, described the second address pointer register and described the 3rd address pointer register.
9. the manner of execution of a kind of microcontroller instruction set according to claim 8, it is characterized in that, the content in described outer RAM storer is stored in general-purpose register by the indirect addressing of described the second address pointer register and the pointer of described the second address pointer register constant;
The pointer that stores content in described general-purpose register into the outer ram register of sheet and described the second address pointer register by the indirect addressing of described the second address pointer register is constant;
The least-significant byte that stores the content in sheet internal program storer ROM into described general-purpose register by described the first address pointer register and get a word corresponding to this address packs in first object register, and most-significant byte packs in the next register of described first object register; And the least-significant byte that stores the content in outer sheet program memory ROM into general-purpose register by described the 3rd address pointer register and get a word corresponding to this address packs in described the second destination register, most-significant byte packs in the next register of described the second destination register.
10. instruction set according to claim 1, the method also comprises: by the instruction that needs redirect by comparison order to realize the function of redirect; When register value equates with setting value, carry out next instruction; When register value and setting value unequal, skip next instruction and carry out the instruction after next.
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Application publication date: 20141008 |