CN104079308A - Carrier wave eliminating system circuit applied to NFC receiver - Google Patents
Carrier wave eliminating system circuit applied to NFC receiver Download PDFInfo
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- CN104079308A CN104079308A CN201410331807.3A CN201410331807A CN104079308A CN 104079308 A CN104079308 A CN 104079308A CN 201410331807 A CN201410331807 A CN 201410331807A CN 104079308 A CN104079308 A CN 104079308A
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Abstract
The invention belongs to the technical field of electrons, and particularly discloses a carrier wave eliminating system circuit applied to an NFC receiver. The carrier wave eliminating system circuit comprises a down-conversion mixer circuit, an integrator circuit, an up-conversion mixer circuit, a low pass filter circuit and the like. The down-conversion mixer circuit moves a carrier wave signal to the direct current position. The integrator circuit amplifies the direct current signal and attenuates a non-direct-current signal. The up-conversion mixer circuit moves the amplified direct current signal to the carrier wave frequency position. The low pass filter circuit filters out an upper half sideband signal after down-conversion mixing is carried out, and meanwhile a base band signal is amplified to obtain a useful base band signal. By means of the carrier wave eliminating system circuit, strong carrier waves are eliminated, the self-blocking problem in the NFC receiver is accordingly solved, and the sensitivity of the NFC receiver is improved.
Description
Technical field
The invention belongs to electronic technology field, the carrier wave that is specifically related to a kind of NFC of being applied to receiver is eliminated circuit system.
Background technology
NFC(Near Field Communication) technology is that a kind of operating frequency is 13.56MHz, communication distance is the wireless communication technology of marching into the arena in 10 centimetres generally, in particular, it is that one can provide mobile device, consumer electronics product, PC and smart control equipment room carry out in-plant contactless identification and interconnected wireless communication standard.
Fig. 1 is an existing NFC receiver, and this NFC receiver is connected to antenna by a coupling capacitance, thereby obtains energy, and receiver obtains the signal on antenna by resistance pressure-dividing network.Why because transmitter signal is exported after power amplification by the reason that electric resistance partial pressure is connected to antenna, then be connected to antenna by matching network, due to the effect of matching network impedance transformation, now the carrier signal on antenna is generally tens to one hectovolt spies.So large voltage has exceeded the trouble free service voltage range of chip already, therefore receives signal and must after electric resistance partial pressure, just can be connected to the input of receiver.
Although input voltage has met the requirement of the trouble free service of chip, but problem occurred, because resistance pressure-dividing network is an attenuation network in fact, it does not have frequency selectivity, so in the time that it is decayed to antenna carrier, signal is also corresponding has been attenuated identical multiple.The sensitivity that can suppose receiver is-80dBm, and potential-divider network decay 40dB is to ensure that under the strongest radio-frequency (RF) magnetic field, input voltage maintains within the scope of safe voltage, and this reception function detects the just only have-40dBm of minimum signal on antenna so.If attenuation network decay 20dBm, that minimum signal that can detect is exactly-60dBm that, if do not decay, that is exactly-80dBm.Obviously, the bottleneck of receiver sensitivity is just limited by potential-divider network.Owing to being necessary to the decay of carrier wave, and to preferably not decay of signal, that can design an attenuation network with frequency selectivity, only carrier wave is decayed and is not affected signal? adding notch filter is a solution, Fig. 2 is the NFC receiver that adds notch filter, but the cost of chip external device is seemingly unacceptable, if notch filter is accomplished to chip internal, but the inductance that the notch filter that centre frequency is 13.56MHz needs, in uH rank, integratedly on sheet may be realized hardly.Therefore, how to realize an attenuation network with frequency selectivity at chip internal and become the key that improves receiver sensitivity.
The present invention has designed the decay cyclic system with frequency selectivity that can realize at chip internal, complete circuit design, can effectively solve in NFC receiver from obstructing problem, thereby the sensitivity that improves traditional NFC receiver.
Summary of the invention
The object of the present invention is to provide a kind of loop carrier of the sensitivity that can improve traditional NFC receiver to eliminate circuit system.
Carrier wave provided by the invention is eliminated circuit system, and referring to Fig. 3, this system has well realized the inhibition for carrier wave, thus solved NFC receiver from obstructing problem.Circuit comprises: I/Q two-way down-conversion mixer, integrator, upper frequency mixer and low pass filter; Its annexation is: antenna is connected with two-way down-conversion mixer input, the output of two-way down-conversion mixer is connected with the input of two-way integrator respectively, also be connected with the input of two-way low pass filter below simultaneously, the output of two-way integrator is connected with the input of two-way upper frequency mixer, the input that the output of two-way upper frequency mixer feeds back to system again subtracts each other, thereby forms a closed loop.Wherein:
Described down-conversion mixer is for carrying out downward frequency translation by carrier signal and useful signal, because the carrier frequency of the signal of input is 13.56MHz, by carrying out lower mixing with the local oscillator of 13.56MHz, carrier signal can be moved to direct current place, at this moment the size of direct current signal has just been reacted the size of input carrier signal.
Described low pass filter carries out filtering for the signal of first sideband to after lower mixing, baseband signal is amplified simultaneously, thereby obtains useful baseband signal.
Described integrator is used for amplifying direct current signal, and other signal of decaying, because the signal that system will feedback is only carrier signal part, and do not wish useful signal also to feed back to input, through the existing carrier signal part of signal after down-conversion mixer, also have most important baseband signal, integrator only amplifies the direct current signal that represents carrier signal power, decay for baseband signal part, thereby realize the frequency-selecting effect of only carrier signal being fed back.
Described upper frequency mixer carries out uppermixing for the direct current signal after integrator is amplified, and direct current signal is converted to 13.56MHz, then the signal of export and inputting subtracts each other, thereby realization is only for the decay of carrier signal.
In the present invention, described down-conversion mixer, input adopts pseudo-differential NMOS input, has adopted current multiplexing technology to increase input mutual conductance simultaneously, improves conversion gain, reduces equivalent input noise.Output adopts resistance as load, in the case of identical pressure drop, can obtain better noise.
In the present invention, described integrator adopts active integrator structure, is realizing in identical unity gain bandwidth situation, and area is less, and noiseproof feature is also better.Trsanscondutance amplifier in active integrator has adopted two-stage structure for amplifying, gain mean allocation, and the difference mode gain of output stage can regulate by common-mode feedback resistor.
In the present invention, described upper frequency mixer input adopts collapsible PMOS differential pair tube, and voltage margin is improved;
Output stage by common-mode feedback by output DC point clamper at Vdd/2 the output voltage swing with maximum signal.
In the present invention, described low pass filter has used the Butterworth second-order low-pass filter of MFB structure, not high to the sensitivity of passive device, more easily realizes fully differential, operational amplifier wherein adopts fully differential structure, realizes common-mode feedback by common-mode resistance.
Brief description of the drawings
Fig. 1, existing NFC receiver structure.
The NFC receiver of Fig. 2, increase notch filter.
Fig. 3, orthogonal negative feedback carrier wave cancellation receiver block diagram.
Fig. 4, down-conversion mixer circuit.
Fig. 5, integrator circuit structure.
Transconductance amplifier circuit in Fig. 6, integrator.
Fig. 7, upper frequency mixer circuit.
Fig. 8, low-pass filter circuit structure.
Discharge circuit in Fig. 9, low pass filter.
Embodiment
Below in conjunction with drawings and Examples, technical solution of the present invention is further described.For those of ordinary skill in the art, do not paying under the prerequisite of creative work, can also obtain other accompanying drawings and other embodiment according to the present invention.These all belong to the scope of protection of the invention.
Carrier wave provided by the invention is eliminated the physical circuit of system, comprises down-conversion mixer circuit, integrator circuit, upper frequency mixer circuit and low-pass filter circuit.Its annexation is: antenna is connected with two-way down-conversion mixer input, the output of two-way down-conversion mixer is connected with the input of two-way integrator respectively, also be connected with the input of two-way low pass filter below simultaneously, the output of two-way integrator is connected with the input of two-way upper frequency mixer, the input that the output of two-way upper frequency mixer feeds back to system again subtracts each other, thereby forms a closed loop.The concrete structure of each circuit module will be illustrated below.
In the present invention, the circuit of down-conversion mixer is with reference to figure 4.Radio-frequency input signals is loaded into input to pipe transistor M1, the grid of M2, and transistor M3, M4 be as auxiliary input pipe, and its grid is respectively by corresponding capacitor C 1, the C2 input signal that is coupled; Transistor M5, M6, M7, M8 is switching tube, wherein, the source electrode of transistor M5, M6 respectively with input pipe M2, the drain electrode of M4 is connected, the source electrode of transistor M7, M8 is connected with the drain electrode of input pipe M1, M3 respectively, and the grid of transistor M5, M7 meets local oscillator LO, and the grid of transistor M6, M8 connects the reverse signal of local oscillator LO; The drain electrode output of transistor M5, M8 is connected with load resistance R1, and the drain electrode output of transistor M6, M7 is connected with load resistance R2.Because supply voltage is 1.2V, consider voltage margin, so rf inputs uses pseudo-differential NMOS to pipe M1, M2, as input, adopts current multiplexing technology simultaneously, and PMOS is managed to M3, M4 is as assisting pipe, provide extra electric current to increase input mutual conductance, improve conversion gain, reduce equivalent input noise., reduce because flow through the direct current of load resistance, pressure drop reduces meanwhile, thereby the linearity of input can improve.Adopt resistance as load at output, in the case of identical pressure drop, can obtain better noise.
In the present invention, the circuit structure of integrator is with reference to figure 5.Integrator adopts active structure, and in the case of realizing identical unity gain bandwidth, area is less, and noiseproof feature is also better.Input signal Vin receives the negative terminal input of trsanscondutance amplifier by resistance R 3, capacitor C 5 is connected across between the positive-negative input end mouth of trsanscondutance amplifier; Trsanscondutance amplifier positive input port ground connection; Capacitor C 6 is connected across between the negative input port and output port of trsanscondutance amplifier; Load resistance R4 and load capacitance C7 are also connected between trsanscondutance amplifier output port and ground.
After integrator structure and parameter are determined, the most importantly design of trsanscondutance amplifier, referring to Fig. 6.Differential input signal is received the grid end of PMOS pipe M19, M20, and the grid end of NMOS pipe M13, M14 is received respectively in the drain electrode output of PMOS pipe M19, M20, and NMOS manages M13, and the drain terminal of M14 connects output; Feedback resistance R9, R10 are serially connected between output port, its dividing potential drop V
cMreceive the grid of PMOS pipe M18; Trsanscondutance amplifier adopts two-stage structure for amplifying, difference input PMOS pipe M19, M20 provide first order gain, difference output NMOS pipe M13, M14 provide second level gain, and gain is in two inter-stage mean allocation, and the difference mode gain of output stage can regulate by common-mode feedback resistor R9, R10.By controlling feedback resistance R9, the dividing potential drop of R10 is recently controlled feedback voltage V
cM, and then form negative feedback mechanism, keep the common-mode voltage of output stable.
In the present invention, the circuit of upper frequency mixer is referring to Fig. 7.Consider the wide dynamic range requirement of upper frequency mixer centering frequency input terminal mouth, here adopt folding difference PMOS pipe to input as intermediate frequency M21, M22 pipe, input signal is received the grid of difference PMOS pipe to M21, M22, transistor M25, M26, M27, M28 are switching tubes, wherein, transistor M25, M27 grid termination local oscillation signal LO, transistor M26, M28 connect the reverse signal of local oscillator LO.The drain electrode of input PMOS pipe M21 is connected with the source electrode of transistor M25, M26, and the drain electrode of input PMOS pipe M22 is connected with the source electrode of transistor M27, M28.The output of the frequency mixer first order adopts PMOS diode connection to do low-resistance load, the grid end of transistor M29, M30 is connected with drain terminal and forms the low-resistance load of diode connection, the drain terminal of transistor M25, M28 is connected with the drain terminal of transistor M29, and the drain terminal of transistor M26, M27 is connected with the drain terminal of transistor M30; Signal output form adopts electric current output, and transistor M31, M32 form output stage, and load resistance R13, R14 adopt capacitor C 10, C11 AC coupled with output stage transistor M31, M32 respectively.Output stage simultaneously by common-mode feedback resistor R11, R12 by output DC point clamper at Vdd/2 the output voltage swing with maximum signal.While considering the conversion gain of upper frequency mixer, it should be noted that it is to wish that local oscillator input is operated in linear magnifying state but not on off state to pipe M25, M26, M27, M28 here.In fact, upper frequency mixer is typical gilbert's multiplier unit.Intermediate frequency input is all operated in to pipe M25, M26, M27, M28 the saturation region that differential linearity is amplified to pipe M21, M22 and local oscillator.
In the present invention, the circuit structure of low pass filter is referring to Fig. 8.Here the Butterworth second-order low-pass filter that adopts MFB structure, this structure more easily realizes fully differential, and not high to the sensitivity of passive device.Its annexation is: input signal Vin is connected with resistance R 15 left ends, resistance R 17 is serially connected between resistance R 15 right-hand members and amplifier negative input end, capacitor C 12 is connected between resistance R 15 right-hand members and ground, resistance R 16 one end are connected with resistance R 15 right-hand members, one termination amplifier output, capacitor C 13 1 termination amplifier negative input ends, a termination output, amplifier positive input terminal ground connection.
After filter construction is determined, crucial is the wherein design of operational amplifier, and operation amplifier circuit is referring to Fig. 9 here.Amplifier adopts two-stage fully differential structure, and difference NMOS, to managing M36, M37 and M40, M41 as input, provides the first order to amplify.Input signal Vin+ receives the grid end of NMOS pipe M36, M41, and Vin-receives the grid end of NMOS pipe M37, M40; Transistor M42, M43, as efferent duct, provide the second level to amplify.The grid end of transistor M42, M43 is connected with the drain terminal of NMOS pipe M36, M37 respectively, and the drain terminal of transistor M42, M43 is connected with the drain terminal of transistor M40, M41 respectively, and meanwhile, the drain terminal of transistor M42, M43 is amplifier output port.Resistance R 18, R19, R20, R21 are common-mode feedback resistor, and they are connected across respectively between the grid leak of transistor M38, M39, M44, M45.
The distribution of gain between two-stage can be first determined in the design of circuit, thereby can substantially determine the value of common-mode resistance.The output resistance of the second level can not be excessive as the output resistance of amplifier.Excessive output resistance can affect the gain of filter, and general output resistance is at least less than 1/10th of feedback resistance.Zero point can be by regulating g to the compensation of the second limit
m40,41realize.
Claims (5)
1. the carrier wave that is applied to NFC receiver is eliminated a circuit system, it is characterized in that, comprising: I/Q two-way down-conversion mixer, integrator, upper frequency mixer and low pass filter; Its annexation is: antenna is connected with two-way down-conversion mixer input, the output of two-way down-conversion mixer is connected with the input of two-way integrator respectively, also be connected with the input of two-way low pass filter below simultaneously, the output of two-way integrator is connected with the input of two-way upper frequency mixer, the input that the output of two-way upper frequency mixer feeds back to system again subtracts each other, thereby forms a closed loop; Wherein:
Described down-conversion mixer is for carrying out downward frequency translation by carrier signal and useful signal, because the carrier frequency of the signal of input is 13.56MHz, by carrying out lower mixing with the local oscillator of 13.56MHz, carrier signal is moved to direct current place, the size of the at this moment size of direct current signal reaction input carrier signal;
Described low pass filter carries out filtering for the signal of first sideband to after lower mixing, baseband signal is amplified simultaneously, thereby obtains useful baseband signal;
Described integrator is used for amplifying direct current signal, and decay baseband signal;
Described upper frequency mixer carries out uppermixing for the direct current signal after integrator is amplified, and direct current signal is converted to 13.56MHz, then the signal of export and inputting subtracts each other, thereby realization is only for the decay of carrier signal;
Described down-conversion mixer, input adopts pseudo-differential NMOS input, adopts current multiplexing technology to increase input mutual conductance simultaneously; Output adopts resistance as load, in the case of identical pressure drop, to obtain better noise;
Described integrator adopts active integrator structure, and the trsanscondutance amplifier in active integrator adopts two-stage structure for amplifying, gain mean allocation, and the difference mode gain of output stage regulates by common-mode feedback resistor;
Described upper frequency mixer input adopts collapsible PMOS differential pair tube, and voltage margin is improved; Output stage by common-mode feedback by output DC point clamper at Vdd/2 the output voltage swing with maximum signal;
Described low pass filter uses the Butterworth second-order low-pass filter of MFB structure, and operational amplifier wherein adopts fully differential structure, realizes common-mode feedback by common-mode resistance.
2. the carrier wave that is applied to NFC receiver according to claim 1 is eliminated circuit system, it is characterized in that the circuit structure of described down-conversion mixer is as follows: radio-frequency input signals is loaded into the grid of input transistors to M1, M2; Transistor M3, M4 be as auxiliary input pipe, and its grid is respectively by corresponding capacitor C 1, the C2 input signal that is coupled; Transistor M5, M6, M7, M8 is switching tube, wherein, the source electrode of transistor M5, M6 is connected with the drain electrode of input pipe M2, M4 respectively, and the source electrode of transistor M7, M8 is connected with the drain electrode of input pipe M1, M3 respectively, the grid of transistor M5, M7 meets local oscillator LO, and the grid of transistor M6, M8 connects the reverse signal of local oscillator LO; The drain electrode output of transistor M5, M8 is connected with load resistance R1, and the drain electrode output of transistor M6, M7 is connected with load resistance R2.
3. the carrier wave that is applied to NFC receiver according to claim 2 is eliminated circuit system, it is characterized in that described integrator adopts active structure, wherein, input signal Vin receives the negative terminal input of trsanscondutance amplifier by resistance R 3, capacitor C 5 is connected across between the positive-negative input end mouth of trsanscondutance amplifier; Trsanscondutance amplifier positive input port ground connection; Capacitor C 6 is connected across between the negative input port and output port of trsanscondutance amplifier; Load resistance R4 and load capacitance C7 are also connected between trsanscondutance amplifier output port and ground; Wherein, the structure of trsanscondutance amplifier is: differential input signal is received the grid end of PMOS pipe M19, M20, and the grid end of NMOS pipe M13, M14 is received respectively in the drain electrode output of PMOS pipe M19, M20, and NMOS manages M13, and the drain terminal of M14 connects output; Feedback resistance R9, R10 are serially connected between output port, its dividing potential drop V
cMreceive the grid of PMOS pipe M18.
4. the carrier wave that is applied to NFC receiver according to claim 3 is eliminated circuit system, the circuit structure that it is characterized in that described upper frequency mixer is: adopt folding difference PMOS pipe to input as intermediate frequency M21, M22 pipe, input signal is received the grid of difference PMOS pipe to M21, M22, transistor M25, M26, M27, M28 are switching tubes, wherein, transistor M25, M27 grid termination local oscillation signal LO, transistor M26, M28 connect the reverse signal of local oscillator LO; The drain electrode of input PMOS pipe M21 is connected with the source electrode of transistor M25, M26, and the drain electrode of input PMOS pipe M22 is connected with the source electrode of transistor M27, M28; The output of the frequency mixer first order adopts PMOS diode connection to do low-resistance load, the grid end of transistor M29, M30 is connected with drain terminal and forms the low-resistance load of diode connection, the drain terminal of transistor M25, M28 is connected with the drain terminal of transistor M29, and the drain terminal of transistor M26, M27 is connected with the drain terminal of transistor M30; Signal output form adopts electric current output, and transistor M31, M32 form output stage, and load resistance R13, R14 adopt capacitor C 10, C11 AC coupled with output stage transistor M31, M32 respectively; Output stage simultaneously by common-mode feedback resistor R11, R12 by output DC point clamper at Vdd/2 the output voltage swing with maximum signal.
5. the carrier wave that is applied to NFC receiver according to claim 4 is eliminated circuit system, the circuit structure that it is characterized in that described low pass filter is as follows: input signal Vin is connected with resistance R 15 left ends, resistance R 17 is serially connected between resistance R 15 right-hand members and operational amplifier negative input end, capacitor C 12 is connected between resistance R 15 right-hand members and ground, resistance R 16 one end are connected with resistance R 15 right-hand members, one termination amplifier output, capacitor C 13 1 termination amplifier negative input ends, one termination output, amplifier positive input terminal ground connection; Wherein, described operational amplifier adopts two-stage fully differential structure, and difference NMOS, to managing M36, M37 and M40, M41 as input, provides the first order to amplify; Input signal Vin+ receives the grid end of NMOS pipe M36, M41, and Vin-receives the grid end of NMOS pipe M37, M40; Transistor M42, M43, as efferent duct, provide the second level to amplify; The grid end of transistor M42, M43 is connected with the drain terminal of NMOS pipe M36, M37 respectively, and the drain terminal of transistor M42, M43 is connected with the drain terminal of transistor M40, M41 respectively, and meanwhile, the drain terminal of transistor M42, M43 is amplifier output port; Resistance R 18, R19, R20, R21 are common-mode feedback resistor, and they are connected across respectively between the grid leak of transistor M38, M39, M44, M45.
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| CN104639205A (en) * | 2014-12-08 | 2015-05-20 | 李青花 | Signal enhancement system based on near field communication |
| CN104639194A (en) * | 2014-12-08 | 2015-05-20 | 李青花 | Signal receiving system based on zigbee |
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| CN115913263A (en) * | 2022-11-11 | 2023-04-04 | 江苏稻源科技集团有限公司 | Wireless receiver structure |
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| CN104639205A (en) * | 2014-12-08 | 2015-05-20 | 李青花 | Signal enhancement system based on near field communication |
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| CN107769737A (en) * | 2017-10-18 | 2018-03-06 | 上海芯北电子科技有限公司 | A kind of operational amplifier calibration method and circuit |
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Application publication date: 20141001 |