CN104064223B - Flash memory verification apparatus - Google Patents
Flash memory verification apparatus Download PDFInfo
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- CN104064223B CN104064223B CN201310091311.9A CN201310091311A CN104064223B CN 104064223 B CN104064223 B CN 104064223B CN 201310091311 A CN201310091311 A CN 201310091311A CN 104064223 B CN104064223 B CN 104064223B
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Abstract
The invention discloses a flash memory verification apparatus, which comprises a test controller and a characteristic adjusting circuit. The test controller provides supply voltage, and is used for verifying read-write operation of the flash memory. The characteristic adjusting circuit is coupled between the test controller and the flash memory, is controlled by the test controller for determining actuation, and provides supply voltage to the flash memory while actuating. The test controller can actuates the characteristic adjusting circuit during a power supply preparation period, uses supply voltage for starting the flash memory, and the verification apparatus is used for verifying the flash memory.
Description
Technical field
The invention relates to a kind of checking device, and in particular to a kind of checking device of flash memories.
Background technology
Flash memories (Flash Memory) element can repeatedly carry out being stored in, read, wiping for data due to having
Action, and the advantage that the data being stored in also will not disappear after a loss of power, so having become PC and electronic equipment institute extensively
Using a kind of non-volatile memory device.
In general, manufacturer all can carry out the test and checking of flash memories before shipment, use and filter defective products,
The quality of the flash memories of output to guarantee.In actual application, because flash memories can be widely applicable for not
With electronic installation to perform the function of data access, operations specifications and the circuit configurations of each of which electronic installation respectively have difference
It is different, and described operations specifications all may affect with the difference of circuit configurations corresponding flash memories reading, write or
Erasing operation.In other words, flash memories might have the situation of characteristic deviation when being configured in different electronic installations, all
Occur, and described characteristic deviation is then likely to result in the operation failure of flash memories.
However, in the test and validation mechanism of existing flash memories, checking device is only capable of with regard to flash memories
Default specification verified, and cannot the operation that is located under different qualities of verification flash memory memorizer whether pass through.Furthermore, due to electricity
The species of sub-device is various with specification, and manufacturer is also difficult to the state being configured at for flash memories in each electronic installation
Verified and tested.
The content of the invention
The present invention provides a kind of checking device of flash memories, and the power initiation of its adjustable flash memories resets
（power on reset）Characteristic, and flash memories are verified according to this.
The present invention proposes a kind of checking device of flash memories, including test controller and performance regulator circuit.Survey
Examination controller provides supply voltage, and to the read-write operation of verification flash memory memorizer.Performance regulator circuit is coupled to test
Between controller and flash memories, it is controlled by test controller and decides whether enable, and by supply voltage when enable
There is provided to flash memories.Wherein, enable performance regulator circuit after test controller is during power supply preparation, with using power supply electricity
Pressure starts flash memories, and flash memories are verified according to this.
In an embodiment of the present invention, the running voltage of flash memories is interior during starting gradually is promoted to from low level
Operation level, the interior multiple time points during startup of test controller sequentially send reading instruction, with verification flash memory memorizer
Interior first time during startup reads the time point for passing through.
In an embodiment of the present invention, the running voltage of flash memories is interior during starting gradually is promoted to from low level
Operation level, the interior multiple time points during startup of test controller sequentially send write instruction, with verification flash memory memorizer
The time point that interior first time write during startup passes through.
In an embodiment of the present invention, flash memories have a power end, and performance regulator circuit include power switch with
And first resistor.To receive supply voltage, the second end of power switch couples the first end coupling test controller of power switch
Power end, and the control end of power switch receives the first control signal of test controller, wherein power switch is controlled according to first
Signal processed and on or off.Second end of one end coupling power switch of first resistor and power end, and first resistor is another
One end couples ground voltage.
In an embodiment of the present invention, test controller is promoted to after operation level in the running voltage of flash memories and cuts
Only power switch so that running voltage is gradually lowered, and when running voltage is down to the first level, test controller is led again
Logical power switch sends reading instruction or write instruction with verification flash memory memorizer from different starting flash memories
Read-write operation when first level starts.
In an embodiment of the present invention, performance regulator circuit also includes capacitor cell.Capacitor cell coupling power switch
Second end and power end, wherein capacitor cell Jing are controlled and the equivalent capacity of adjustment power end, use control flash memories
Charge rate, test controller send reading instruction or write instruction with verification flash memory memorizer under different charge rates
Read-write operation.
In an embodiment of the present invention, capacitor cell includes multiple electric capacity and multiple switch.The plurality of electric capacity difference
With different capacitances.One end of the plurality of switch is respectively coupled to the plurality of electric capacity, and the plurality of switch is another
Coupling flash memories are held, wherein capacitor cell Jing is controlled and turned on one of the plurality of switch, by corresponding electricity
Hold and be coupled to flash memories.
In an embodiment of the present invention, capacitor cell includes variable capacitance, and wherein capacitor cell Jing is controlled and adjusted variable
The capacitance of electric capacity.
In an embodiment of the present invention, test controller is more to the erasing operation of verification flash memory memorizer, and verifies dress
Put and also include discharge circuit.Discharge circuit couples performance regulator circuit and flash memories.Discharge circuit is controlled by testing and control
Device and decide whether enable, and provide discharge path when enable.Test controller sends erasing instruction so that flash memory storage
Device carries out erasing operation, and interior disable feature adjustment circuit and enable during flash memories carry out the erasing of erasing operation
Discharge circuit so that flash memories are discharged via discharge path, uses whether inspection flash memories occur excessively wiping
Remove（over-erase）.
In an embodiment of the present invention, flash memories have power end, and discharge circuit includes discharge switch and second
Resistance.The first end coupling power end of discharge switch, and the control end of discharge switch receives the second control letter of test controller
Number, wherein discharge switch is according to the second control signal and on or off.The second of one end coupling discharge switch of second resistance
End, and the other end coupling ground voltage of the second electricity group.
In an embodiment of the present invention, test controller multiple time point disable features in the erase period interior in order are adjusted
Whole circuit and discharge switch is turned on, to check respectively for whether over-erasure occurring under the plurality of time point.
Based on a kind of above-mentioned, checking device of flash memories of embodiment of the present invention proposition, it is using characteristic adjustment electricity
Road resets characteristic come the power initiation for accordingly adjusting flash memories so that test controller can be for flash memories not
Same power initiation to reset and be written and read the checking of operation under characteristic, and then improves the accuracy of checking.
It is that the features described above and advantage of the present invention can be become apparent, special embodiment below, and coordinate institute's accompanying drawings
It is described in detail below.
Description of the drawings
Fig. 1 is a kind of schematic diagram of the checking device of flash memories.
Fig. 2 resets the schematic diagram of characteristic for the power initiation of flash memories.
Fig. 3 is the schematic diagram of the checking device of the flash memories of one embodiment of the invention.
Fig. 4 is the circuit diagram according to the checking device of the flash memories of Fig. 3 embodiments.
Fig. 5 for one embodiment of the invention from different voltage levels starts when power initiation replacement characteristic schematic diagram.
Fig. 6 resets the schematic diagram of characteristic for the power initiation under the different charge rates of one embodiment of the invention.
Fig. 7 is the schematic diagram of the checking device of the flash memories of another embodiment of the present invention.
Fig. 8 carries out the signal schematic representation of erasing operation for the flash memories of one embodiment of the invention.Fig. 9 is according to Fig. 7
The circuit diagram of the checking device of the flash memories of embodiment.Wherein, description of reference numerals is as follows：
10：Flash memories
12：Start reset circuit
14：Memory circuitry
100、300、400、700、900：Checking device
310、710：Test controller
312、712：Power subsystem
320、420、720：Performance regulator circuit
422：Power switch
424、934：Resistance
426：Capacitor cell
730、930：Discharge circuit
932：Discharge switch
C1～Cn：Electric capacity
CS1：First control signal
CS2：Second control signal
CUV1、CUV2：Characteristic curve
ES1～ES4：Stage
DBUS：Data/address bus
SW1～SWn：Switch
T0～tn：Time point
TD1：During first electric discharge
TD2：During second electric discharge
TE：During erasing
TO、TO1、TO2：During startup
TP1：During first is default
TP2：During second is default
TI：During initialization
TS：During power supply prepares
VCC：Running voltage
VDD：Supply voltage
V1、V1’：Level
VL：Low level
VI：Initialization level
VW：Operation level
VWL：Minimum operation level
Specific embodiment
Fig. 1 is a kind of schematic diagram of the checking device of flash memories.The manufacturer of general flash memories all can go out
Using checking device 100 as shown in Figure 1 come the read-write operation of verification flash memory memorizer before goods.Fig. 1 is refer to, device is verified
100 can provide supply voltage VDD gives flash memories 10 so that the startup reset circuit 12 of flash memories 10 is reacted on and connect
The supply voltage VDD of receipts and produce running voltage VCC.Then, the memory circuitry 14 of flash memories 10 can be heavy according to starting
Running voltage VCC produced by circuits 12 and initialized and started, to make flash memories 10 normally to be read
Write operation.
After flash memories 10 start, checking device 100 can send reading instruction or write via data bus dbus
Instruct to flash memories 10 so that flash memories 10 carry out corresponding reading or the behaviour for writing according to the instruction for being received
Make.Then, flash memories 10 can be back to the result for reading or writing in checking device 100 via data bus dbus,
So that checking device 100 can be verified by comparing sent out read/write instruction with the read/write result for being received
The read-write operation of flash memories 10 is to pass through（pass）Or failure（fail）.
When flash memories 10 are configured at different electronic installations, the power initiation of flash memories 10 resets
（power-on reset）Characteristic can be changed according to the operations specifications of corresponding electronic installation with circuit configurations.It is described
Power initiation reset characteristic change the initialization of memory circuitry 14 or read-write operation may be impacted, and then
The reading and write for making flash memories 10 occurs abnormal.However, the abnormality of this type is generally difficult to using checking device
100 detect.
Hereinafter, simply the power initiation of flash memories 10 resets characteristic and is illustrated, wherein flash memories 10
Power initiation reset characteristic it is as shown in Figure 2.Referring to Fig. 1 and Fig. 2, in flash memories 10 supply voltage is received
During VDD, starting reset circuit 12 can react on supply voltage VDD and produce from low level VL during starting in TO（Such as 0V）
Gradually it is promoted to operation level VW（Such as 3V）Running voltage VCC, wherein memory circuitry 14 can be in running voltage VCC from low
In a period of level VL is promoted to initialization level VI（TI during initializing）Initialized, and in running voltage VCC
Terminate initialized action during more than initialization level VI.During starting after TO, running voltage VCC is then stably maintained at
Operation level VW.
In general, flash memories 10 reach minimum operation level VWL and pre- through a section first in running voltage VCC
If period TP1（Such as 10 microseconds（μs））Can successfully be read afterwards, and flash memories 10 are in running voltage
VCC reaches initialization level VI（Complete initialization）And through one section of second default period TP2（Such as 1 millisecond（ms））After be
Write operation can successfully be carried out.Therefore, flash memories 10 can be according to the access requirement of corresponding electronic installation, and in its work
Make to carry out first time reading or write when voltage VCC not yet reaches operation level VW.It should be noted, however, that flash memory is deposited
Reservoir 10 actually can successfully carry out the time point of first time read operation and first time write operation also suffer from circuit design or
The factors such as technique affect and have changed.
When 100 verification flash memory memorizer 10 of device is verified, TS is steady during checking device 100 can be prepared using one section of power supply
The fixed supply voltage VDD that its is provided, and reading instruction is just sent after the supply voltage VDD for being provided is stable or write refers to
Order carrys out verification flash memory memorizer 10, uses and avoids causing the authentication error of flash memories 10 because supply voltage VDD is unstable.
Wherein, TS generally needs the time of several ms to hundreds of milliseconds during power supply prepares.In comparison, flash memories 10 are being opened
After dynamic, TO only needs the time of several microseconds to several milliseconds during its startup.Therefore, after the TS during power supply prepares, work electricity
Pressure VCC has generally been stably maintained in operation level VW.
In other words, verify that device 100 only can be during power supply prepares after TS, to operating in stable running voltage
Flash memories 10 under VCC are written and read the checking of operation, and cannot be for flash memories 10 during starting in TO
First time read-write operation is verified.Therefore, verify device 100 and cannot measure flash memories 10 during starting in TO into
Carry out the time point of first time reading/first time write work(.
When on the other hand, in the electronic installation that flash memories 10 are configured at different size or species, because flash memory is deposited
The equivalent capacity of the power end of reservoir 10 can be affected by different operations specifications and circuit configurations and be changed, thus make
The charge rate of flash memories 10 is affected, the charge rate of wherein flash memories 10 refers to running voltage VCC from low
Level VL is promoted to the time needed for operation level VW.The difference of charge rate then can directly have influence on the first of flash memories
The length of TI during beginningization, and TI may result in the initialization mistake of memory circuitry 14 during different initialization, enter
And cause the read-write operation exception of flash memories 10.
Additionally, when flash memories 10 are closed during normal operating, running voltage VCC can be from operation level VW
Low level VL is gradually decreased to, during so that flash memories 10 being again started up, initialization level VI can be promoted in running voltage VCC
Initialized action is carried out before.In other words, the state that memory circuitry 14 need to be in running voltage VCC less than initialization level VI
Lower startup can just carry out initialized action.However, may be because of circuit design or the shadow of technique due to initializing level VI
Ring and deviate expected design load, and the skew for initializing level VI then may be such that the operation generation of flash memories 10 is non-
Expected mistake.For example, when flash memories 10 are not yet down to initialization level VI and are waken up in running voltage VCC,
Flash memories 10 can cause read-write operation exception because of initialized action is not carried out.Therefore, how to verify initial
The actual value for changing level VI is also considerable problem.
It follows that flash memories 10 can successfully carry out time of first time read/write, charge rate and initial
Changing the parameter of the power initiations such as level replacement characteristic all affects the key factor of the read-write operation of flash memories 10.However, checking
Device 100 is only capable of being verified with regard to the default specification of flash memories 10, and cannot be verified for each above-mentioned parameter.
In order to solve the above problems, the present embodiment proposes a kind of framework of checking device, as shown in Figure 3.Fig. 3 is the present invention
The schematic diagram of the checking device of the flash memories of one embodiment.Fig. 3 is refer to, checking device 300 includes test controller 310
And performance regulator circuit 320.Test controller 310 provides supply voltage VDD, and to the reading of verification flash memory memorizer 10
Write operation.Performance regulator circuit 320 is coupled between test controller 310 and flash memories 10, is controlled by test controller
310 and decide whether enable, and supply voltage VDD is provided to flash memories 10 when enable.
Specifically, when verifying that device 300 connects flash memories 10 to be measured with the mechanism for starting checking, test control
The power subsystem 312 of device processed 310 can output supply voltage VDD, and interior during one section of power supply prepares carry out stabilized power source electricity
The action of pressure VDD.Wherein, power subsystem 312 is coupled to flash memories 10 to provide power supply electricity via performance regulator circuit 320
Pressure VDD.Because performance regulator circuit 320 has the function of similar switch, therefore can't be by power supply electricity when it is not enabled
Pressure VDD is provided to flash memories 10.In other words, flash memories 10 can't be interior by supply voltage during power supply prepares
VDD is started.
After during power supply prepares, the enable performance regulator circuit 320 of test controller 310 so that characteristic adjustment electricity
Road 320 provides supply voltage VDD to flash memories 10, so as to start reset circuit 12 and react on supply voltage VDD and produce
Raw running voltage VCC, and memory circuitry 14 is initialized and is started according to this.In the present embodiment, due to power subsystem
312 power supplys before the startup of flash memories 10 are interior during preparing to adjust supply voltage VDD to stable state, therefore surveys
Examination controller 310 can immediately send reading instruction when flash memories 10 start or write instruction carrys out verification flash memory memorizer
10 read-write operation.
More specifically, referring to Fig. 2 and Fig. 3, because supply voltage VDD was before the startup of flash memories 10
It is adjusted to and stablizes, therefore multiple time points that test controller 310 can be during starting in TO send reading instruction, to verify
First time of the flash memories 10 during startup in TO reads the time point for passing through.Similarly, test controller 310 also can be
Multiple time points during startup in TO send write instruction, with first time of the verification flash memory memorizer 10 during startup in TO
The time point that write passes through.
For example, when the read operation that test device 300 carries out flash memories 10 is verified, test controller 310
Can be after the completion of initialization, time at regular intervals（Such as 1 μ s）Reading instruction is sent, and according to flash memories 10
Read result and carry out the time point that the first time reading of verification flash memory memorizer 10 passes through.Similarly, when checking device 300 is dodged
Deposit memorizer 10 write operation verify when, test controller 310 can after the completion of initialization, at regular intervals the time send
Write instruction, and according to the write result of flash memories 10 come the first time write of verification flash memory memorizer 10 pass through when
Between point.
In order to be illustrated more clearly that the embodiment of the present invention, Fig. 4 is the checking device according to the flash memories of Fig. 3 embodiments
Circuit diagram.Fig. 4 is refer to, checking device 400 includes test controller 310 and performance regulator circuit 420, wherein special
Property adjustment circuit 420 include power switch 422, resistance 424 and capacitor cell 426.
In the present embodiment, the first end of power switch 422 couples test controller 310 to receive the institute of power subsystem 312
The supply voltage VDD of generation, the second end of power switch 422 couples the power end PT of flash memories 10, and power switch
422 control end coupling test controller 310, to receive the first control signal CS1 that test controller 310 is provided.Wherein,
The meeting of power switch 422 on or off according to the first control signal CS1.The of one end coupling power switch 422 of resistance 424
Two ends and power end PT, and the other end coupling ground voltage GND of resistance 424.Capacitor cell 426 then couples power switch 422
The second end and power end PT.
In this, though power switch 422 is illustrated by taking BJT transistors as an example.But in other embodiments, described confession is established by cable
Close 422 also can realize that the present invention is not limited using MOS transistor.
According to the circuit framework of performance regulator circuit 420, test controller 310 can by the first control signal CS1 export to
The base stage of BJT transistors controls the conducting of BJT transistors or cuts to be utilized respectively enable with the first control signal CS1 of forbidden energy
Only.Furthermore, test controller 310 can be after the supply voltage VDD that power subsystem 312 can provide stable, and output is caused
Can the first control signal CS1 to turn on BJT transistors, and supply voltage VDD provided to flash memories 10 according to this, use
Realize the checking of the first time read/write of flash memories 10 described in above-described embodiment.
On the other hand, verify device 400 can further verification flash memory memorizer 10 initialization level actual value
And flash memories 10 are located at the read-write operation under different charge rates in running voltage VCC.First, just using checking device
The verification operation of the actual value of the initialization level of 400 verification flash memory memorizeies 10 is illustrating.
Referring to Fig. 4 and Fig. 5, wherein, Fig. 5 for one embodiment of the invention from different voltage levels start when electricity
Source starts the schematic diagram for resetting characteristic.In the initialization level of verification flash memory memorizer 10, first, the meeting of test controller 310
First provide supply voltage VDD according to aforesaid mode so that running voltage VCC of flash memories 10 is gradually promoted to work electricity
Flat VW.After running voltage VCC is promoted to operation level VW, test controller 310 output forbidden energy the first control signal CS1 with
Cut-off power switch 422 so that flash memories 10 discharge via resistance 424, and make running voltage VCC be gradually lowered.
In the present embodiment, user can be adjusted when flash memories 10 start by the length during control electric discharge
The initial level of running voltage VCC, so that what the checking verification flash memory memorizer 10 of device 400 started under different initial levels
Read-write operation state.More specifically, in checking device 400, the resistance 424 in performance regulator circuit 420 can provide flash memory
The path of the electric discharge of memorizer 10 so that flash memories 10 can linearly be discharged in a period of supply voltage VDD is closed,
Therefore user can control the initial level of running voltage VCC by the time length of decision control signal CS1 of forbidden energy first.
Thereby, whether user can extremely judge according to the read-write operation state that flash memories 10 start under different initial levels
The actual value of initialization level VI.
For example, test controller 310 can be set and during the electric discharge of mono- section first of the first control signal CS1 of forbidden energy
TD1, so that the level of running voltage VCC is gradually decreased to the first level V1 in TD1 during the first electric discharge from operation level VW, and
And during the first electric discharge control signal CS1 of enable first again after TD1.After TD1 during the first electric discharge, test controller
310 understand control signals CS1 of enable first and turn on power switch 422, use restarting flash memories 10, and send reading
Instruction fetch or write instruction with verification flash memory memorizer 10 from level V1 start when read-write operation.Now, because level V1 is low
In actual initialization level VI, therefore verify that device 400 can judge that flash memories 10 can normally enter under this test condition
The new read-write operation of row.
Similarly, test controller 310 can be set and control flash memories 10 using similar above-mentioned mode and exist
Discharged in TD2 during one section of second electric discharge, so that flash memories 10 restart under level V1 ', so that test control
Device processed 310 can send read instruction or write instruction with verification flash memory memorizer 10 from level V1 ' start when read-write operation.This
When, because level V1 ' is higher than actual initialization level VI, flash memories 10 can't carry out initialized action, therefore
Checking device 400 can judge that flash memories 10 cannot be normally carried out new read-write operation under this test condition.
Because the numerical value of level V1 and V1 ' all can be learnt by measurement, therefore user can be according to the knot of above-mentioned verification operation
The actual value for really judging initialization level VI is located between level V1 and V1 '.Wherein, though above-described embodiment is taking two not
Illustrate for example with initial level V1 and V1 ', but the present invention is not limited thereto.In actual application, checking behaviour
The sampling number of work and the numerical value of initial level all can have been adjusted according to the demand of user.
On the other hand, read-write operation just using the checking verification flash memory memorizer 10 of device 400 under different charge rates
For, referring to Fig. 4 and Fig. 6, wherein, Fig. 6 is the power initiation weight under the different charge rates of one embodiment of the invention
Put the schematic diagram of characteristic.In the present embodiment, capacitor cell 426 can be controlled and adjust the power end PT of flash memories 10
Equivalent capacity, uses the charge rate of control flash memories 10.Specifically, capacitor cell 426 can Jing user it is manual
Control, or automatically controlled by test controller 310 and adjust its capacitance.When the coupling of capacitor cell 426 with different capacitances
When being bonded to the power end PT of flash memories 10, running voltage VCC can react on the equivalent capacity of power end PT and have difference
Characteristic curve（Such as CUV1 and CUV2）.
For example, when capacitor cell 426 is adjusted to small capacitances value, running voltage VCC can correspond to characteristic curve
CUV1.Now, flash memories 10 can have TO1 during higher charge rate and shorter startup.On the contrary, working as electric capacity list
When unit 426 is adjusted to bulky capacitor value, running voltage VCC can then correspond to characteristic curve CUV2.Now, the meeting of flash memories 10
TO2 during with relatively low charge rate and longer startup.Therefore, test controller 310 can respectively to characteristic curve
The flash memories 10 of CUV1 and CUV2 send reading instruction or write instruction, use verification flash memory memorizer 10 and fill in different
Read-write operation under electric speed.
In the present embodiment, described capacitor cell 426 can be using each electricity of multiple electric capacity C1～Cn and multiple correspondences
Hold the circuit framework of switch SW1～SWn of C1～Cn realizing.Wherein, each electric capacity C1～Cn has respectively different electric capacity
Value, and the one end for switching SW1～SWn is respectively coupled to electric capacity C1～Cn, and switch the other end coupling flash memory storage of SW1～SWn
The power end PT of device 10.Under this circuit framework, user is manually controllable or automatically controls each using test controller 310
The on or off of switch SW1～SWn so that corresponding to each switch SW1～SWn electric capacity C1～Cn according to demand by coupling
The power end PT of flash memories 10 is bonded to, the equivalent capacity for changing power end PT is used.
In addition, capacitor cell 426 also can be realized by variable capacitance, and wherein the capacitance of variable capacitance can be by making
User manually adjusts, or is automatically adjusted by test controller 310, and the present invention is not limited.
Referring again to Fig. 1, in checking device 100, can be just like front except the read-write operation checking to flash memories 10
Outside the problem stated.Checking device 100 also cannot be to verify to the in the erase period interior erasing operation of flash memories 10.
Specifically, referring to Fig. 1 and Fig. 8, it is however generally that, when flash memories 10 carry out erasing operation, flash memories
Multiple different phases can be carried out in TE during an erasing（Such as ES1～ES4）Erasing move, to wipe a section
（sector）Or block（block）.Wherein, TE is generally needed about between 30ms to 300ms during a complete erasing.If
In the erase period in TE, the unexpected power-off of flash memories 10, then the memory element that correspondence is wiped free of in memory circuitry 14
Erasing operation may carry positive charge because discharging excessive electronics, that is, there occurs over-erasure（over-erase）Show
As, and flash memories 10 may be made to fail to the read-write operation of adjoining memory cell after restarting.Wherein, flash memory is deposited
The generation machine that may all affect over-erasure phenomenon is considered in design of technique, circuit design and erasing instruction of reservoir 10 etc.
Rate.
Furthermore, in actual applications, designer is still difficult to the no generation of the meeting of discovery in design and the stage simulated
The phenomenon of over-erasure, only can filter the flash memories for being susceptible to over-erasure using the checking action of rear end.
However, due to verifying device 100 and flash memories 10 cannot be verified in TE in the erase period therefore above-mentioned is excessive
The phenomenon of erasing simultaneously cannot be by detected by checking device 100.
In order to solve the above problems, the present embodiment more proposes a kind of framework of checking device, as shown in Figure 7.Fig. 7 is this
The schematic diagram of the checking device of the flash memories of bright another embodiment.Fig. 7 is refer to, checking device 700 includes testing and control
Device 710, performance regulator circuit 720 and discharge circuit 730.Test controller 710 provides supply voltage VDD, and to test
Demonstrate,prove reading, write and the erasing operation of flash memories 10.Performance regulator circuit 720 is coupled to test controller 710 and flash memory
Between memorizer 10, it is controlled by test controller 710 and decides whether enable, and provides supply voltage VDD when enable
To flash memories 10.Discharge circuit 730 couples performance regulator circuit 720 and flash memories 10, and wherein discharge circuit 730 is received
Control and decide whether enable in test controller 710, and the discharge path of flash memories 10 1 is provided when enable.
In the present embodiment, verify device 700 except storing come verification flash memory using the verification mode of above-described embodiment
Outside the read-write operation of device 10, verify that device 700 also may be used to the erasing operation of verification flash memory memorizer 10.Referring to Fig. 7
With Fig. 8, when verifying that device 700 carries out the checking of erasing operation to flash memories 10, test controller 710 can send erasing
Instruction is so that flash memories 10 carry out erasing operation.During flash memories 10 carry out the erasing of erasing operation in TE, survey
Examination controller 710 can be in particular point in time（Such as t0～tn）Lower disable feature adjustment circuit 720 and enable discharge circuit 730,
So that flash memories 10 are discharged via the discharge path that discharge circuit 730 is provided, with the spy in TE in the erase period
Under fixing time a little, running voltage VCC is rapidly down to low level to close flash memories 10.Then, test controller 710
Whether the signal that each memory element in memory circuitry 14 can be checked meets desired value, uses and verifies in TE in the erase period
The particular point in time under erasing operation whether there is the phenomenon of over-erasure.
Fig. 9 is the circuit diagram according to the checking device of the flash memories of Fig. 7 embodiments.Refer to Fig. 9, checking dress
Putting 900 includes test controller 710, performance regulator circuit 420 and discharge circuit 930.Wherein, performance regulator circuit 420 is wrapped
Include power switch 422, resistance 424 and capacitor cell 426.Discharge circuit includes discharge switch 932 and resistance 934.
In the present embodiment, the first end of power switch 422 couples test controller 710 to receive the institute of power subsystem 712
The supply voltage VDD of generation, the second end of power switch 422 couples the power end PT of flash memories 10, and power switch
422 control end coupling test controller 710, to receive the first control signal CS1 that test controller 710 is provided.Wherein,
The meeting of power switch 422 on or off according to the first control signal CS1.The of one end coupling power switch 422 of resistance 424
Two ends and power end PT, and the other end coupling ground voltage GND of resistance 424.Capacitor cell 426 then couples power switch 422
The second end and power end PT.
The first end coupling power end PT of discharge switch 932, and the control end of discharge switch 932 receives test controller
710 the second control signals CS2 for being exported, wherein discharge switch 932 on or off according to the second control signal CS2.Electricity
One end of resistance 934 couples the second end of discharge switch 932, and the other end coupling ground voltage GND of resistance 934.
In this, though discharge switch 932 is illustrated by taking BJT transistors as an example.But in other embodiments, described electric discharge is opened
Close 932 also can realize that the present invention is not limited using MOS transistor.Additionally, the performance regulator circuit 420 of the present embodiment
Circuit operation and related description refer to above-mentioned Fig. 4 embodiments, repeat no more in this.
In the present embodiment, according to the framework of discharge circuit 930, test controller 710 can be defeated by the second control signal CS2
Go out the base stage to discharge switch 932 to be utilized respectively enable with the second control signal CS2 of forbidden energy to control discharge switch 932
On or off.Furthermore, multiple time point t0～tn that test controller 710 can in order in the erase period in TE
Disable feature adjustment circuit 720 and discharge switch 932 is turned on respectively, so that test controller 710 is checked respectively in time point
Whether the phenomenon of over-erasure there is under t0～tn, and the wherein interval between Each point in time t0～tn is, for example, 1ms, this numerical value
Can set according to design requirement, the present invention is not limited.
Additionally, in another embodiment, test controller 710 also can randomly choose the several times during wiping in TE
Point and disable feature adjustment circuit 720 and turn on discharge switch 932 so that test controller 710 checks flash memories 10
Whether there is the phenomenon of meeting over-erasure under the selected time point got, use the situation that accuracy is verified in not significant impact
Under, it is effectively reduced the time expended needed for checking erasing operation.
In sum, the embodiment of the present invention proposes a kind of checking device of flash memories, and it is using characteristic adjustment electricity
Road resets characteristic come the power initiation for accordingly adjusting flash memories so that test controller can be for flash memories not
Same power initiation to reset and be written and read the checking of operation under characteristic, and then improves the accuracy of checking.Additionally, the present invention is real
Whether the checking device for applying example more may be used to the erasing operation of verification flash memory memorizer under in the erase period interior multiple time points
The phenomenon of over-erasure can be caused.
Although the present invention is disclosed as above with embodiment, so it is not limited to the present invention, any art
Middle technical staff, in the spirit and scope without departing from the claims in the present invention, when can make a little change with retouching, therefore this
Bright protection domain ought be defined depending on the appended right claimed range person of defining that applies for a patent.
Claims (11)
1. the checking device of a kind of flash memories, it is characterised in that include：
One test controller a, there is provided supply voltage, and to verify the read-write operation of the flash memories；And
One performance regulator circuit, is coupled between the test controller and the flash memories, be controlled by the test controller and
Decide whether enable, and the supply voltage provided to the flash memories when enable,
Wherein the test controller during power supply preparation after the enable performance regulator circuit, with using the power supply voltage start
The flash memories, the supply voltage is reacted on gradually after making a running voltage of the flash memories during the power supply prepares
Lifted,
Wherein the test controller is interior during the startup sends reading instruction or write instruction, and according to this to the flash memories
First time read the time point that passes through or write the time point for passing through for the first time and verified.
2. the checking device of flash memories as claimed in claim 1, it is characterised in that wherein work of the flash memories
Make that voltage is interior during the startup to be gradually promoted to an operation level from a low level, the test controller is interior during the startup
Multiple time points sequentially send reading instruction, to verify that it is logical that the flash memories interior first time during the startup reads
The time point crossed.
3. the checking device of flash memories as claimed in claim 1, it is characterised in that wherein work of the flash memories
Make that voltage is interior during the startup to be gradually promoted to an operation level from a low level, the test controller is interior during the startup
Multiple time points sequentially send the write instruction, it is logical to verify the interior first time write during the startup of the flash memories
The time point crossed.
4. the checking device of flash memories as claimed in claim 1, it is characterised in that wherein the flash memories have
Power end, and the performance regulator circuit includes：
One power switch, its first end couples the test controller to receive the supply voltage, and its second end couples the power end,
And its control end receives one first control signal of the test controller, wherein the power switch is according to first control signal
On or off；And
One first resistor, its one end couples the second end of the power switch and the power end, and its ground connection electricity of other end coupling one
Pressure.
5. the checking device of flash memories as claimed in claim 4, it is characterised in that wherein the test controller is in the sudden strain of a muscle
The running voltage for depositing memorizer is promoted to after an operation level and ends the power switch so that the running voltage is gradually lowered,
And when the running voltage is down to first level, the test controller turns on the power switch and deposits starting the flash memory again
Reservoir, and send reading instruction or a write instruction with verify the flash memories from different first level start when
Read-write operation.
6. the checking device of flash memories as claimed in claim 4, it is characterised in that wherein the performance regulator circuit is also wrapped
Include：
One capacitor cell, couples the second end and the power end of the power switch, and wherein capacitor cell Jing is controlled and adjusted and be somebody's turn to do
The equivalent capacity of power end, uses the charge rate for controlling the flash memories, and the test controller sends reading instruction
Or one write instruction verifying read-write operation of the flash memories under the different charge rates.
7. the checking device of flash memories as claimed in claim 6, it is characterised in that wherein the capacitor cell includes：
Multiple electric capacity, wherein the plurality of electric capacity has respectively different capacitances；And
Multiple switch, its one end is respectively coupled to the plurality of electric capacity, and its other end couples the flash memories, wherein the electric capacity list
First Jing is controlled and is turned on one of the plurality of switch, and corresponding electric capacity is coupled to into the flash memories.
8. the checking device of flash memories as claimed in claim 6, it is characterised in that wherein the capacitor cell includes：
One variable capacitance, wherein capacitor cell Jing are controlled and adjust the capacitance of the variable capacitance.
9. the checking device of flash memories as claimed in claim 1, it is characterised in that wherein the test controller more to
The erasing operation of the flash memories is verified, and the checking device also includes：
One discharge circuit, couples the performance regulator circuit and the flash memories, is controlled by the test controller and decides whether
Enable, and a discharge path is provided when enable,
Wherein the test controller sends an erasing instruction so that the flash memories carry out erasing operation, and deposit in the flash memory
The interior forbidden energy performance regulator circuit and the enable discharge circuit during the erasing that reservoir carries out erasing operation so that the flash memory is deposited
Reservoir fast break via the discharge path, uses checking whether the flash memories occur over-erasure.
10. the checking device of flash memories as claimed in claim 9, it is characterised in that wherein the flash memories have
One power end, the discharge circuit includes：
One discharge switch, its first end couples the power end, and its control end receives one second control letter of the test controller
Number, wherein the discharge switch according to second control signal on or off；And
One second resistance, its one end couples the second end of the discharge switch, and its other end couples a ground voltage.
The checking device of 11. flash memories as claimed in claim 10, it is characterised in that wherein the test controller is sequentially
The multiple time point forbidden energy performance regulator circuits interior during the erasing in ground and the discharge switch is turned on, to check respectively for
Whether there is over-erasure under the plurality of time point.
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| CN201310091311.9A CN104064223B (en) | 2013-03-20 | 2013-03-20 | Flash memory verification apparatus |
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| CN201310091311.9A CN104064223B (en) | 2013-03-20 | 2013-03-20 | Flash memory verification apparatus |
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| CN104064223B true CN104064223B (en) | 2017-04-26 |
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| CN106291300B (en) * | 2015-05-25 | 2019-03-12 | 中芯国际集成电路制造(上海)有限公司 | Chip pressure drop, the test method of structure and chip improved method |
| CN113961419B (en) * | 2021-09-24 | 2022-09-23 | 北京百度网讯科技有限公司 | Memory verification method and device, electronic equipment and storage medium |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1435845A (en) * | 2002-02-02 | 2003-08-13 | 三星电子株式会社 | Non-Volatile semiconductor memory with charging read mode |
| CN104064222A (en) * | 2013-03-20 | 2014-09-24 | 华邦电子股份有限公司 | Verification apparatus for flash memory |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5452251A (en) * | 1992-12-03 | 1995-09-19 | Fujitsu Limited | Semiconductor memory device for selecting and deselecting blocks of word lines |
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Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1435845A (en) * | 2002-02-02 | 2003-08-13 | 三星电子株式会社 | Non-Volatile semiconductor memory with charging read mode |
| CN104064222A (en) * | 2013-03-20 | 2014-09-24 | 华邦电子股份有限公司 | Verification apparatus for flash memory |
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