CN104022760B - A kind of data amplitude limiter for noise suppressed, receiver and data slicing method - Google Patents
A kind of data amplitude limiter for noise suppressed, receiver and data slicing method Download PDFInfo
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Abstract
The present invention relates to a kind of data amplitude limiter for noise suppressed, receiver and data slicing method, described data amplitude limiter includes a limiter comparator, and the signal input part of data amplitude limiter connects the inverting input of described limiter comparator by a RC integrating circuit, the signal output part of data amplitude limiter is the output of described limiter comparator, it is characterized in that, the signal input part of described data amplitude limiter connects the in-phase input end of described limiter comparator by a noise suppression circuit, and the in-phase input end level constant voltage values lower than the signal input part level of data amplitude limiter that described noise suppression circuit makes described limiter comparator.The present invention at communication receiver system when not having signal to input, it is suppressed that the output of the noise of data amplitude limiter, its circuit is simple, it is easy to accomplish, cost is relatively low, and noise suppression is effective.
Description
Technical field
The present invention relates to be applied to the data amplitude limiter field of communication control processor, particularly relate to a kind of for
Realize the data amplitude limiter of noise suppressed, receiver and data slicing method.
Background technology
In communication receiver system, the effect of data amplitude limiter (Data slicer) is to recover to connect
The data signal that receipts machine demodulates out.In digital communication systems, data signal to be transmitted carries through high frequency
After ripple modulation (mode such as ASM amplitude keying, FSM frequency keying) and transmitting, receiver receive also
After High frequency amplification, mixing, intermediate frequency (IF) amplify, then demodulated the numeral letter transmitted by demodulator
Number stream.In this process, unavoidably there will be deformation due to signal through the process of multi-level pmultistage circuit
And distortion, so that recover digital signal streams with data amplitude limiter after demodulator.Typical amplitude limit
Device circuit, as it is shown in figure 1, the in-phase input end of limiter comparator connects input signal, is simultaneously entered signal warp
The integrating circuit of resistance R, electric capacity C composition is connected on the inverting input of limiter comparator.When choosing integration
Between the constant i.e. appropriate value of product RC so that it is more than cycle during minimum message transmission rate, make RC
Play a part smooth input voltage.Therefore, the voltage VN of inverting input is approximately input signal
The mean value of voltage, this mean value is just as the threshold values of limiter comparator.When input is data signal " 1 "
Time (high level signal), applied signal voltage is greater than threshold values, makes comparator export high level；When defeated
When entering data signal " 0 " (low level signal), applied signal voltage is less than threshold values, comparator homophase
Input level VP is less than inverting input level, therefore comparator output low level.So comparator
Just amplitude is less, have wave distortion distortion supplied with digital signal recover and be shaped as rule numeral letter
Number output.This circuit is particularly suited for recovering with the data of Manchester's code, its " 1 " and " 0 "
Always interval is transmitted, thus its average potential can substantially remain in the 50% of signal amplitude.Additionally, work as
The received signal strength dc component making it demodulate that changes is when changing, comparator end of oppisite phase
Current potential VN is the most always about equal to the mean value of input signal.But this circuit there is a problem that,
When not having input signal, the noise of receiver also can make the output of comparator constantly overturn, such as Fig. 2 institute
Show, thus produce the output of insignificant interference data.For solving this problem, some receivers are for reducing
The impact of noise and before data amplitude limiter, add one-stage low-pass wave circuit, but also can only make noise amplitude
Reducing, when receiver does not has signal to input, limiter still suffers from the output of noise jamming data.Have connects
Receipts machine uses has the comparator of hysteresis trigger voltage transmission characteristic as data amplitude limiter, as it is shown on figure 3,
Make its high level upset threshold values+UT bigger, such as more than the crest voltage of noise, and low level roll-over valve
-UT is smaller for value, thus generally owing to noise amplitude is less than the high level upset threshold values of comparator
Output will not be produced.But when there is skew in the output of data amplitude limiter previous circuit so that comparator
The average level amplitude of inverting input also can change, so that level magnitudes total after superimposed noise
Likely more than the upset threshold values of comparator, thus still can produce the output of noise jamming data.
Summary of the invention
The technical problem to be solved be to provide a kind of data amplitude limiter realizing noise suppressed and
Data slicing method, for solving the numeral that available data limiter recovers and shaping receiver demodulates out
During signal, the problem that the output of noise jamming data can be produced when not having signal to input.
The technical scheme is that a kind of data for noise suppressed limit
Width device, including a limiter comparator, and the signal input part of data amplitude limiter is by a RC integration
Circuit connects the inverting input of described limiter comparator, and the signal output part of data amplitude limiter is described limit
The output of width comparator, the signal input part of described data amplitude limiter is by a noise suppression circuit even
Connect the in-phase input end of described limiter comparator, and described noise suppression circuit makes described limiter comparator
An in-phase input end level constant voltage values lower than the signal input part level of data amplitude limiter.
On the basis of technique scheme, the present invention can also do following improvement.
Further, described noise suppression circuit is a DC constant voltage source, and described direct current constant electricity
The positive pole of potential source connects the signal input part of described data amplitude limiter, the negative pole in described DC constant voltage source
Connect the in-phase input end of described limiter comparator.
Further, described noise suppression circuit includes a diode, a fixed value resistance and a dividing potential drop
Adjustable resistance, the positive pole of described diode connects the signal input part of described data amplitude limiter, described diode
Negative pole by described fixed value resistance ground connection, described dividing potential drop adjustable resistance is connected on the two ends of described diode,
And the sliding tap of described dividing potential drop adjustable resistance connects the in-phase input end of described limiter comparator.
Further, described diode is germanium tube.
Further, described constant voltage values is more than the noise letter inputted from the signal input part of data amplitude limiter
Number crest voltage.
Technical scheme also includes a kind of receiver for noise suppressed, including:
One receiver front end device, puts for successively the data signal received from channel being carried out high frequency
Greatly, it is mixed and intermediate frequency amplification, is converted to intermediate-freuqncy signal；
One demodulator, is demodulated for the intermediate-freuqncy signal being converted into receiver fore device；
One above-mentioned data amplitude limiter, after it is connected to described demodulator, for recovering with shaping through institute
The data signal exported after stating demodulator demodulation.
Technical scheme also includes a kind of data slicing method for noise suppressed, including following
Step:
Step 1, receives data signal from channel, and carries out High frequency amplification, mixing and intermediate frequency amplification successively,
The data signal of reception is converted to intermediate-freuqncy signal, then intermediate-freuqncy signal is demodulated；
Step 2, arranges a data amplitude limiter, and it includes a limiter comparator, the letter after demodulation
After a RC integrating circuit, number access the inverting input of limiter comparator；
Step 3, accesses the signal after demodulation the in-phase input end of limiter comparator, and arranges limit ratio
Compared with the low constant voltage values of signal level after the in-phase input end level ratio demodulation of device.
Further, the in-phase input end level arranging limiter comparator is lower one than the signal level after demodulation
Constant voltage values specifically includes: be connected between signal and the in-phase input end of limiter comparator after demodulation
One DC constant voltage source, the positive pole in this DC constant voltage source accesses the signal after demodulation, and negative pole is then
Connect the in-phase input end of limiter comparator.
Further, the in-phase input end level arranging limiter comparator is lower one than the signal level after demodulation
Constant voltage values specifically includes: configure a diode, a fixed value resistance and a dividing potential drop adjustable resistance,
The positive pole of diode accesses the signal after demodulation, and the negative pole of diode passes through described fixed value resistance ground connection, institute
State dividing potential drop adjustable resistance and be connected on the two ends of described diode, and the sliding tap of described dividing potential drop adjustable resistance is even
Connect the in-phase input end of described limiter comparator.
Further, described constant voltage values is more than the noise letter inputted from the signal input part of data amplitude limiter
Number crest voltage.
The invention has the beneficial effects as follows: the present invention, presses down when not having signal to input at communication receiver system
Having made the noise output of data amplitude limiter, its circuit is simple, it is easy to accomplish, cost is relatively low, noise suppression effect
Good.
Accompanying drawing explanation
Fig. 1 is the structural representation of the data amplitude limiter that prior art uses.
Fig. 2 be the data amplitude limiter shown in Fig. 1 when not having signal to input, the noise jamming data of output
Oscillogram.
Fig. 3 is to use the voltage transmission having hysteresis trigger comparator as data amplitude limiter in prior art
Performance plot.
Fig. 4 is the structural representation of the data amplitude limiter described in embodiment one.
Fig. 5 (a) is the input noise oscillogram of the data amplitude limiter shown in Fig. 4.
Fig. 5 (b) is that the in-phase input end level of the limiter comparator of the data amplitude limiter shown in Fig. 4 is with anti-
The oscillogram of phase input level.
Fig. 6 is the structural representation of the data amplitude limiter described in embodiment two.
Fig. 7 (a) be the data amplitude limiter shown in Fig. 6 when there being direct current offset, input signal and limit ratio
The relatively oscillogram of device inverting input level.
Fig. 7 (b) be the data amplitude limiter shown in Fig. 6 when there being direct current offset, input signal and limit ratio
The relatively oscillogram of device output level.
Detailed description of the invention
Being described principle and the feature of the present invention below in conjunction with accompanying drawing, example is served only for explaining this
Invention, is not intended to limit the scope of the present invention.
Embodiment one
As shown in Figure 4, embodiment one gives the data amplitude limiter for noise suppressed, including one
Limiter comparator, and the signal input part of data amplitude limiter is by a RC integrating circuit described limit of connection
The inverting input of width comparator, the signal output part of data amplitude limiter is the output of described limiter comparator
End, the signal input part of described data amplitude limiter connects described limit ratio relatively by a noise suppression circuit
The in-phase input end of device, and described noise suppression circuit makes the in-phase input end level of described limiter comparator
A constant voltage values lower than the signal input part level of data amplitude limiter.
In the present embodiment, described noise suppression circuit is a DC constant voltage source, and described direct current is permanent
The positive pole determining voltage source connects the signal input part of described data amplitude limiter, described DC constant voltage source
Negative pole connects the in-phase input end of described limiter comparator.If the voltage of this direct current constant value be one constant
Value VS, and make this steady state value VS slightly larger than noise peak voltage, therefore there is no input signal in system
Time owing to the level of in-phase input end of limiter comparator is always less than the inverting input of limiter comparator,
Thus inhibit the noise of data amplitude limiter to export, shown in its effect such as Fig. 5 (a) and Fig. 5 (b).It addition,
Due to an in-phase input end always low constant DC voltage value VS than input signal of limiter comparator,
Therefore the exchange useful signal inputted will not produce pressure drop on constant pressure source.This circuit also has another excellent
Point is that limiter comparator input can be followed input and be changed, and energy when input voltage occurs skew
A low this relation of constant voltage values is not than input signal to keep limiter comparator in-phase input end level
Become.
Embodiment two
As shown in Figure 6, the difference of the present embodiment and embodiment one is the design of noise suppression circuit, institute
State noise suppression circuit and include a diode D, a fixed value resistance R2 and a dividing potential drop adjustable resistance
The positive pole of R1, described diode D connects the signal input part of described data amplitude limiter, described diode D's
Negative pole passes through described fixed value resistance R2 ground connection, and described dividing potential drop adjustable resistance R1 is connected on described diode D's
Two ends, and the homophase input of the sliding tap described limiter comparator of connection of described dividing potential drop adjustable resistance R1
End.
Input signal is connected to the inverting input of limiter comparator through RC integrating circuit, smooth input signal
After mean value be end of oppisite phase provide trigger valve threshold voltage VN.Diode D uses germanium tube, its two ends pressure drop
VD is about about 0.1V.Dividing potential drop adjustable resistance R1 connects the two ends of diode D, and sliding tap is connected to ratio
The in-phase input end of relatively device, i.e. diode two ends pressure drop VD make limit ratio relatively after adjustable resistance R1 dividing potential drop
Device in-phase input end level VP is low constant voltage values VS than signal input part, by taking out of regulation R1
Head position, makes this constant voltage values VS slightly larger than input noise crest voltage (several millivolts), then limits
Width comparator is consistently less than anti-phase input terminal potential when not having signal to input due to in-phase end current potential, therefore limits
Width comparator will not overturn and output noise interference data, as shown in Figure 5.Signal is had to input at receiver
Time, owing to demodulator output signal voltage amplitude is relatively big (about tens of millivolts to the three ten-day period of hot season), thus VS
Impact the least, do not affect the output of limiter comparator.And owing to VS is a constant voltage values,
When the output of limiter comparator front end occurs direct current offset, in-phase end level also produces same skew and becomes
Change, thus limiter comparator remains to normally recover signal, as shown in Fig. 7 (a) and Fig. 7 (b).
Embodiment three
Embodiment three relates to a kind of communication control processor, and it uses receiver device commonly used in the prior art i.e.
Can, mainly it is improved by: be followed by the data slicing described in an embodiment one or embodiment two at demodulator
Device.The main composition of this communication sink is:
One receiver front end device, puts for successively the data signal received from channel being carried out high frequency
Greatly, it is mixed and intermediate frequency amplification, is converted to intermediate-freuqncy signal；
One demodulator, is demodulated for the intermediate-freuqncy signal being converted into receiver fore device；
One data amplitude limiter, after it is connected to described demodulator, for recovering with shaping through described demodulation
The data signal of output after device demodulation.This data amplitude limiter uses described in embodiment one or embodiment two
Data amplitude limiter, can recover the data signal demodulating out with shaping receiver, and not have signal to input
Time, also will not produce the output of noise jamming data.
Based on above three embodiment, the corresponding data slicing method for noise suppressed includes following step
Rapid:
Step 1, receives data signal from channel, and carries out High frequency amplification, mixing and intermediate frequency amplification successively,
The data signal of reception is converted to intermediate-freuqncy signal, then intermediate-freuqncy signal is demodulated；
Step 2, arranges a data amplitude limiter, and it includes a limiter comparator, the letter after demodulation
After a RC integrating circuit, number access the inverting input of limiter comparator；
Step 3, accesses the signal after demodulation the in-phase input end of limiter comparator, and arranges limit ratio
Compared with the low constant voltage values of signal level after the in-phase input end level ratio demodulation of device.
Reference example one, arranges the in-phase input end level of limiter comparator than the signal level after demodulation
A low constant voltage values specifically includes: the in-phase input end of signal after demodulation and limiter comparator it
Between connect a DC constant voltage source, the positive pole in this DC constant voltage source accesses the signal after demodulation,
Negative pole then connects the in-phase input end of limiter comparator.
Reference example two, arranges the in-phase input end level of limiter comparator than the signal level after demodulation
A low constant voltage values specifically includes: configuring a diode, a fixed value resistance and a dividing potential drop can
Adjusting resistance, the positive pole of diode accesses the signal after demodulation, and the negative pole of diode passes through described fixed value resistance
Ground connection, described dividing potential drop adjustable resistance is connected on the two ends of described diode, and the cunning of described dividing potential drop adjustable resistance
Dynamic tap connects the in-phase input end of described limiter comparator.
This is used for operation principle and the same embodiment of specific implementation process of data slicing method of noise suppressed
One and embodiment two, the most no longer state more.
The foregoing is only presently preferred embodiments of the present invention, not in order to limit the present invention, all in the present invention
Spirit and principle within, any modification, equivalent substitution and improvement etc. made, should be included in this
Within bright protection domain.
Claims (8)
1. for a data amplitude limiter for noise suppressed, including a limiter comparator, and data limit
The signal input part of width device connects the anti-phase input of described limiter comparator by a RC integrating circuit
End, the signal output part of data amplitude limiter is the output of described limiter comparator, it is characterised in that institute
The signal input part stating data amplitude limiter connects described limiter comparator also by a noise suppression circuit
In-phase input end, and described noise suppression circuit makes the in-phase input end level ratio of described limiter comparator
The low constant voltage values of signal input part level of data amplitude limiter；
Described constant voltage values is more than the peak of the noise signal inputted from the signal input part of data amplitude limiter
Threshold voltage.
Data amplitude limiter the most according to claim 1, it is characterised in that described noise suppressed electricity
Lu Weiyi DC constant voltage source, and the positive pole described data slicing of connection in described DC constant voltage source
The signal input part of device, the homophase that the negative pole in described DC constant voltage source connects described limiter comparator is defeated
Enter end.
Data amplitude limiter the most according to claim 1, it is characterised in that described noise suppressed electricity
Road includes a diode, a fixed value resistance and a dividing potential drop adjustable resistance, the positive pole of described diode
Connecing the signal input part of described data amplitude limiter, the negative pole of described diode is connect by described fixed value resistance
Ground, described dividing potential drop adjustable resistance is connected on the two ends of described diode, and the slip of described dividing potential drop adjustable resistance
Tap connects the in-phase input end of described limiter comparator.
Data amplitude limiter the most according to claim 3, it is characterised in that described diode is germanium
Pipe.
5. the receiver for noise suppressed, it is characterised in that including:
One receiver front end device, puts for successively the data signal received from channel being carried out high frequency
Greatly, it is mixed and intermediate frequency amplification, is converted to intermediate-freuqncy signal；
One demodulator, is demodulated for the intermediate-freuqncy signal being converted into receiver fore device；
One data amplitude limiter as described in arbitrary in Claims 1-4, it is connected to described demodulator
After, for recovering and shaping data signal of output after described demodulator demodulates.
6. the data slicing method for noise suppressed, it is characterised in that comprise the following steps:
Step 1, receives data signal from channel, and carries out High frequency amplification, mixing and intermediate frequency amplification successively,
The data signal of reception is converted to intermediate-freuqncy signal, then intermediate-freuqncy signal is demodulated；
Step 2, arranges a data amplitude limiter, and it includes a limiter comparator, the letter after demodulation
After a RC integrating circuit, number access the inverting input of limiter comparator；
Step 3, accesses the signal after demodulation the in-phase input end of limiter comparator, and arranges limit ratio
Compared with the low constant voltage values of signal level after the in-phase input end level ratio demodulation of device；
Described constant voltage values is more than the peak of the noise signal inputted from the signal input part of data amplitude limiter
Threshold voltage.
Data slicing method the most according to claim 6, it is characterised in that limit ratio is set relatively
The in-phase input end level of device specifically includes than the low constant voltage values of signal level after demodulation: solving
Being connected a DC constant voltage source between signal and the in-phase input end of limiter comparator after tune, this is straight
The positive pole of stream constant voltage source accesses the signal after demodulation, and negative pole then connects the homophase input of limiter comparator
End.
Data slicing method the most according to claim 6, it is characterised in that limit ratio is set relatively
The in-phase input end level of device specifically includes than the low constant voltage values of signal level after demodulation: configuration
One diode, a fixed value resistance and a dividing potential drop adjustable resistance, after the positive pole of diode accesses demodulation
Signal, the negative pole of diode passes through described fixed value resistance ground connection, and described dividing potential drop adjustable resistance is connected on described
The two ends of diode, and the homophase of the sliding tap described limiter comparator of connection of described dividing potential drop adjustable resistance
Input.
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| US9811135B2 (en) | 2015-06-19 | 2017-11-07 | Cypress Semiconductor Corporation | Low-power type-C receiver with high idle noise and DC-level rejection |
| CN112702291B (en) * | 2020-12-24 | 2022-08-19 | 成都振芯科技股份有限公司 | Adaptive equalizer and adjusting range expanding method thereof |
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| US5969547A (en) * | 1997-10-24 | 1999-10-19 | General Electronics Applications, Inc. | Analog signal processing circuit with noise immunity and reduced delay |
| EP1146706A2 (en) * | 2000-04-13 | 2001-10-17 | VTech Communications, Ltd. | Determination and storage of a decision threshold |
| CN1325215A (en) * | 2000-04-17 | 2001-12-05 | 德克萨斯仪器股份有限公司 | Self-adapting data amplitude limiter |
| CN1368797A (en) * | 2001-02-02 | 2002-09-11 | 三星电子株式会社 | Data amplitude limiter and radio frequency receiver using it |
| CN203827304U (en) * | 2014-05-28 | 2014-09-10 | 中国地震局地球物理研究所 | Data amplitude limiter used for noise suppression |
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| CN1214813A (en) * | 1996-03-29 | 1999-04-21 | 西门子公司 | Circuit arrangement for regenerating input signal containing digital data sequences |
| US5969547A (en) * | 1997-10-24 | 1999-10-19 | General Electronics Applications, Inc. | Analog signal processing circuit with noise immunity and reduced delay |
| EP1146706A2 (en) * | 2000-04-13 | 2001-10-17 | VTech Communications, Ltd. | Determination and storage of a decision threshold |
| CN1325215A (en) * | 2000-04-17 | 2001-12-05 | 德克萨斯仪器股份有限公司 | Self-adapting data amplitude limiter |
| CN1368797A (en) * | 2001-02-02 | 2002-09-11 | 三星电子株式会社 | Data amplitude limiter and radio frequency receiver using it |
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