CN104020981B - A kind of central processing unit and its command processing method - Google Patents
A kind of central processing unit and its command processing method Download PDFInfo
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- CN104020981B CN104020981B CN201410276522.4A CN201410276522A CN104020981B CN 104020981 B CN104020981 B CN 104020981B CN 201410276522 A CN201410276522 A CN 201410276522A CN 104020981 B CN104020981 B CN 104020981B
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Abstract
The present invention provides a kind of CPU and its command processing method, and the CPU includes：Instruction buffer selector；Two instruction buffer units；Decoding unit is used for according to the instruction generation instruction anticipation signal decoded；Instruction anticipation signal is used to indicate whether execution unit will to perform jump instruction next time；Instruction buffer selector is used for when execution unit will perform jump instruction to the instruction anticipation signal designation received next time, another buffered instructions unit is switched to from the instruction buffer unit currently selected, controls the buffered instructions unit being switched to be read since the position of the program storage pointed by the jump instruction and instructs and preserve；When redirecting, read instruction from the buffered instructions unit being switched to and be sent to decoding unit；When the implementing result of jump instruction is not redirect, switches back into selected buffered instructions unit before switching and continue to read instruction.The present invention can make former CPU CPU kernel speed is lifted 25% on the basis of not area increased.
Description
Technical field
The present invention relates to integrated circuit fields, more particularly to a kind of central processing unit and its command processing method.
Background technology
In recent years, developing rapidly with integrated circuit fields, tradition, small autonomous research and develop (the center processing of 16 bit CPUs
Device) application it is more and more extensive, its price also requires that more and more lower.But 16 of low cost with high arithmetic speed
Cpu chip kernel then turns into the active demand in market.Particularly in low, middle-end integrated circuit product, high-end chip is used
The price of kernel even can influence the profit size of whole product.For example：The product of the ARM companies in the U.S., its CPU is in performance
The two aspects are all dominant with face volume, but its is expensive.Especially for low, middle end product, production has been had a strong impact on
The profit of product and sale.At present, market is low, in middle-end integrated circuit product, is all to use that cheap, arithmetic speed
16 slow bit CPUs, this CPU also constrains the raising of product quality.It is a kind of with cheap, arithmetic speed it is fast new 16
Bit CPU design is a kind of expectation in the high speed development of future integrated circuits field.
16 bit CPU core design such as Fig. 1 of tradition, Fig. 1 inner core includes：Program bus interface unit, instruction buffer
Unit, decoding unit, execution unit and a series of auxiliary units.CPU operationally, is first read from program storage to be needed to perform
Programmed instruction；And this instruction is deposited into by instruction buffer unit by program bus interface；Instruction buffer unit is again this
The individual instruction for being currently needed for performing is sent to decoding unit；Decoding unit parses a series of control signals again, and is retransmited
Performed to execution unit.
The kernel calculating processes of traditional 16 bit CPUs as shown in Fig. 2 a series of control signals first obtained from decoding unit,
These control signals include：Arithmetic operation number A and B and arithmetic type；Execution unit is further according to different arithmetic types to computing
Arithmetic operations different from B progress operand A.Arithmetic type therein includes：The computing of data transfer class, arithmetical logic class fortune
Calculate, class computing is shifted in Boolean Class computing and control.
Result after arithmetic operation includes：Renewal to register, the renewal to relational storage, instruction are redirected and empty behaviour
Make.When generation instruction is redirected, execution unit is notified that instruction buffer unit carries out flush instructions caching；Empty completion
Afterwards, the position that instruction buffer unit can be according to indicated by instruction redirects result, re-request is from program storage reading program again
Instruction；When instruction is emptied and re-request is instructed from program storage reading program, CPU can at least consume 2 time lists
Member.It is above-mentioned empty, re-request and again during the work such as reading program, CPU does not do any operation, and this just makes holding for CPU
Line efficiency is low, and the arithmetic speed of kernel is relatively low；Although and the arithmetic speed of the bit CPU kernel of commercialization 16 of ripe manufacturer compared with
Height, but price is costly.
The content of the invention
The technical problem to be solved in the present invention is to provide a kind of central processing unit and its command processing method, passed with realizing
Unite 16 bit CPU kernels structural volume it is constant on the premise of, the arithmetic speed of the traditional 16 bit CPU kernel of raising by a relatively large margin,
It can keep new traditional 16 bit CPU that there is relatively low price again.
In order to solve the above-mentioned technical problem, the invention provides a kind of central processing unit, including：Decoding unit, perform list
Member, instruction buffer unit；Wherein, in addition to：
Instruction buffer selector；
The instruction buffer unit is two；
The decoding unit is used for according to the instruction generation instruction anticipation signal decoded；The instruction anticipation signal is used for
Indicate whether execution unit will perform jump instruction next time；
The instruction buffer selector is for when the instruction anticipation signal designation received, execution unit will next time
When performing jump instruction, another buffered instructions unit is switched to from the instruction buffer unit currently selected, what control was switched to
Buffered instructions unit is read since the position of the program storage pointed by the jump instruction to be instructed and preserves；When jumping
When turning, read instruction from the buffered instructions unit being switched to and be sent to the decoding unit；When the execution knot of the jump instruction
Fruit is when not redirecting, to switch back into selected buffered instructions unit before switching and continue to read instruction.
Further, above-mentioned central processing unit also has following feature：Also include：
One bit accumulator, the useful signal that redirects for performing the jump instruction to the execution unit is added up,
And accumulation result is sent to the instruction buffer selector；
The instruction buffer selector chooses different instruction buffer lists when redirecting according to the accumulation result
Member, reads instruction from the instruction buffer unit chosen and is sent to the decoding unit.
Further, above-mentioned central processing unit also has following feature：
When redirecting, the instruction buffer selector is additionally operable to the instruction buffer unit hair selected to before the switching
Unselected signal is sent,
The instruction buffer unit selected before the switching receives clear after the unselected signal of the instruction buffer selector
The instruction that sky is stored.
Further, above-mentioned central processing unit also has following feature：
When the implementing result of the jump instruction is not redirect, the instruction buffer selector is additionally operable to the switching
To buffered instructions unit send redirect invalid signals,
The buffered instructions unit being switched to is to receive redirecting for the instruction buffer selector clear after invalid signals
The instruction that sky is stored.
In order to solve the above problems, present invention also offers a kind of command processing method, apply in above-mentioned center processing
In device, including：
Decoding unit is according to the instruction generation instruction anticipation signal decoded, and the instruction anticipation signal is next for indicating
Whether secondary execution unit will perform jump instruction；
When the instruction anticipation signal designation that receive, execution unit will be performed and redirected instruction buffer selector next time
During instruction, another buffered instructions unit is switched to from the instruction buffer unit currently selected, the buffered instructions being switched to are controlled
Unit is read since the position of the program storage pointed by the jump instruction to be instructed and preserves；When redirecting, from
The buffered instructions unit being switched to reads instruction and is sent to the decoding unit；When the implementing result of the jump instruction is not jump
When turning, switch back into selected buffered instructions unit before switching and continue to read instruction.
Further, the above method also has following feature：Also include：
The useful signal that redirects that one bit accumulator performs the jump instruction to the execution unit is added up, and will be tired
Plus result is sent to the instruction buffer selector；
The instruction buffer selector chooses different instruction buffer lists when redirecting according to the accumulation result
Member, reads instruction from the instruction buffer unit chosen and is sent to the decoding unit.
Further, the above method also has following feature：
When redirecting, the instruction buffer selector is also sent not to the instruction buffer unit selected before the switching
Selected signal,
The instruction buffer unit selected before the switching receives clear after the unselected signal of the instruction buffer selector
The instruction that sky is stored.
Further, above-mentioned method also has following feature：
When the implementing result of the jump instruction is not redirect, the instruction buffer selector is also switched to described
Buffered instructions unit sends and redirects invalid signals,
The buffered instructions unit being switched to is to receive redirecting for the instruction buffer selector clear after invalid signals
The instruction that sky is stored.
To sum up, the present invention provides a kind of CPU and its command processing method, for traditional, the small-sized bit CPU of independent research 16
Inner core feature, based on result anticipation mechanism by its kernel increase an instruction cache unit, in advance to its result
It is compared, its kernel is transformed into pseudo- double-core.Because of this anticipation mechanism, make former CPU on the basis of not area increased
On, CPU kernel speed is lifted 25%.The CPU of the present invention can be before the structural volume of traditional 16 bit CPU kernel be constant
Put, the arithmetic speed of the traditional 16 bit CPU kernel of raising by a relatively large margin, but it is relatively low that new traditional 16 bit CPU can be kept to have
Price.
Brief description of the drawings
Fig. 1 16 bit CPU inner core figures of tradition；
The interior kernel operation block diagram of Fig. 2 16 bit CPUs of tradition；
Fig. 3 is the CPU overall construction drawings of the embodiment of the present invention；
Calculation mechanism and calculating process block diagram that Fig. 4 is the CPU of the embodiment of the present invention；
Specific controlling mechanism and control process block diagram that Fig. 5 is the CPU of the embodiment of the present invention.
Embodiment
For the object, technical solutions and advantages of the present invention are more clearly understood, below in conjunction with accompanying drawing to the present invention
Embodiment be described in detail.It should be noted that in the case where not conflicting, in the embodiment and embodiment in the application
Feature can mutually be combined.
As shown in figure 3, CPU provided in an embodiment of the present invention includes：Program bus interface, two instruction buffer unit (bags
Include instruction buffer unit A and instruction buffer unit B), instruction buffer selector, decoding unit, execution unit and a series of auxiliary
Unit.Wherein,
The decoding unit can be used for generation instruction anticipation signal, and the instruction anticipation signal is used to indicate to perform next time
Whether unit will perform jump instruction；
The instruction buffer selector can be used for working as the instruction anticipation signal designation received execution unit next time
When performing jump instruction, another buffered instructions unit is switched to from the instruction buffer unit currently selected, control is switched to
Buffered instructions unit read since the position of the program storage pointed by the jump instruction instruct and preserve；Work as generation
When redirecting, read instruction from the buffered instructions unit being switched to and be sent to the decoding unit；When the execution of the jump instruction
Result is when not redirecting, to switch back into selected buffered instructions unit before switching and continue to read instruction.
The specific implementation status of each unit in the CPU of the present embodiment is as follows：
The instruction buffer unit, for the reading signal-obtaining program according to the instruction buffer selector received
Instruct and store, and the programmed instruction read is sent to institute after the selected signal of the instruction buffer selector is received
State instruction buffer selector or receive the instruction buffer selector redirect invalid signals after empty stored instruction；
Or signal stopping reading program instruction is read according to the stopping of the instruction buffer selector received, and it is described receiving
Stored instruction is emptied after the unselected signal of instruction buffer selector or the jump of the instruction buffer selector is being received
Turn the follow-up program fetch instruction of resuming studies of invalid signals；
The instruction buffer selector, for giving the decoding unit by described program instruction；Receive the decoding single
After the instruction anticipation signal that member is sent, the instruction buffer unit instructed to current reading program sends the stopping and reads signal,
Sent to another instruction buffer unit and read signal；After the implementing result signal for receiving the execution unit, judge described
Execution unit performs whether jump instruction succeeds, and switches the selected signal of described two instruction buffer units if success, if not
It is successful then respectively to described two instruction buffer units send redirect invalid signals；
The decoding unit, is sent to for described program instruction to be resolved into a series of control signals and described performs list
Member, while parsing in described program instruction whether include jump instruction, refers to as sent including if to the instruction buffer selector
Make anticipation signal；
The execution unit, for being performed after receiving the control signal, such as goes to jump instruction, then by institute
The implementing result signal for stating jump instruction is sent to the instruction buffer selector.
The cpu instruction processing method of the present embodiment, calculation mechanism and calculating process are as shown in figure 4, the CPU of the present embodiment
Pseudo- double-core first reads the programmed instruction for needing to perform from program storage；Pass through program bus interface selectively deposit instruction buffer
Unit A or instruction buffer unit B, instruction buffer unit A and instruction buffer unit B give instruction buffer selector instruction；
The selection of instruction buffer selector is currently needed for the instruction performed and is sent to decoding unit；Decoding unit parses a series of control letters
Number being then forwarded to execution unit is performed, and this decoding unit parses instruction anticipation signal simultaneously, and the signal designation is next time
Whether execution unit will perform a jump instruction.When anticipation signal, effectively (i.e. execution unit redirects execution one next time
Instruction) when, instruction buffer unit can automatically switch to another, and the instruction buffer unit being switched to can be from this jump instruction
The position of pointed program storage starts reading program and is stored in the instruction buffer unit being switched to.
When generation instruction redirects (i.e. instruction is redirected effectively, the jump instruction of execution unit successful execution), instruction buffer choosing
Select device directly can read instruction to perform from the instruction buffer unit being switched to, and another instruction buffer unit is simultaneously clear
Sky, when waiting generation jump instruction next time, restarts work；If the implementing result of this jump instruction is not redirect
(i.e. instruction redirects invalid, execution unit execution jump instruction failure), then instruction buffer selector may proceed to from original instruction
Buffer cell reads instruction, and the instruction buffer unit being now switched to can be emptied automatically, and original instruction buffer unit continues
Read and instruct from program storage.
The controlling mechanism and specific control process of the bit CPU execute instruction of pseudo- double-core 16 of the present embodiment, as shown in figure 5, from
Believe it can be seen from the figure that, the position that instruction buffer unit A and B can send the program for wanting to read from program bus interface
Breath, it is possible to which the programmed instruction for obtaining the position from program bus interface is stored.Instruction buffer unit A and B can be need
Instruction buffer selector is given in the instruction to be performed, and needs to give the instruction of decoding unit by the selection of instruction buffer selector.Together
When, instruction buffer selector can send instruction buffer unit A control signals to instruction buffer unit A, and the signal can be indicated
Whether instruction buffer unit A needs to instruct from program bus interface reading program；Instruction buffer selector can also be slow to instruction
Rush device B and send instruction buffer unit B control signals, whether the signal can be needed from program bus with indicator buffer cell B
Interface reading program is instructed.
It is single that the instruction chosen is sent to decoding by instruction buffer unit A and B by instruction buffer selector as present instruction
In member.Instruction buffer selector is by instructing selected signal to be used as discrimination standard, and instruction selected signal is generated by a bit accumulator.
The initial value of the accumulator is 0, that is, acquiescence selection instruction buffer cell A instruction input, when instruction, to redirect signal effective
When (judging the jump instruction of execution unit successful execution), a bit accumulator Jia one automatically, instruction selection signal is changed into 1 from 0,
Choose instruction buffer unit B instruction input, when instruction redirect signal it is effective again when, instruction selection signal become 0 again by 1,
Instruction buffer unit A instruction input is now chosen again.
The selection of instruction buffer selector is by instructing anticipation signal control instruction buffer cell A and B from program bus interface
Instruction is read, under original state, instruction anticipation signal is 0, i.e. selection instruction buffer cell A from program bus interface reading program
Instruction, instruction buffer unit B is idle.When instructing anticipation signal effective, instruction buffer unit B control bits effectively, are now selected
Instruction buffer unit B from program bus interface reading program instruct, instruction buffer unit A instruction redirect signal it is effective when empty
Itself simultaneously waits enable next time.
Decoding unit is responsible for parsing present instruction, generates a series of control signals and gives execution unit execution；Decoding unit
Comprising one instruction anticipation device, the control signal that the instruction anticipation device is parsed according to decoding unit can anticipation go out feeding perform list
Whether member is a jump instruction, if being determined as a jump instruction, and instruction anticipation signal will effectively, then instruct pre-
Sentence signal and be sent to instruction buffer selector.A series of control signals are sent to execution unit, execution unit root by decoding unit
Different operations are carried out according to different instruction types, when performing a jump instruction, the consequential signal of jump instruction will be performed
It is sent to instruction buffer selector.Instruction buffer selector is received after the consequential signal for performing jump instruction, be will determine that and is performed list
Member whether successful execution jump instruction, such as successful execution, to redirect signal effective for instruction；Such as failed execution, then instruction buffer choosing
Invalid signals will be redirected to instruction buffer unit A and B transmission instruction respectively by selecting device.
Most significantly feature is exactly the pseudo- double-core technology of 16 bit CPUs of the embodiment of the present invention, possesses two instruction buffer lists
Member and an arithmetic element physically, in the case of an instruction is only carried out within the same time, improve CPU computing speed
Degree.But, two arithmetic elements physically in real double-core technology are within the same time while execution two is incoherent
Instruction, increases one times, and improve CPU price therefrom by the area of former CPU core.And the embodiment of the present invention is remained
Single 16 bit CPU is employed, by increasing an instruction cache unit and result anticipation mechanism, it is become " pseudo- double-core ",
The arithmetic speed of traditional 16 bit CPU " original " kernel is improved with this.Because of this anticipation mechanism, former CPU is set not increase
On the basis of area, CPU kernel speed is set to lift 25%.So, the CPU of the embodiment of the present invention can be in traditional 16 bit CPU
On the premise of the structural volume of kernel is constant, the arithmetic speed of the traditional 16 bit CPU kernel of raising by a relatively large margin, and can keep new
Type 16 bit CPUs of tradition have relatively low price.
One of ordinary skill in the art will appreciate that all or part of step in the above method can be instructed by program
Related hardware is completed, and described program can be stored in computer-readable recording medium, such as read-only storage, disk or CD
Deng.Alternatively, all or part of step of above-described embodiment can also use one or more integrated circuits to realize.Accordingly
Each module/unit in ground, above-described embodiment can be realized in the form of hardware, it would however also be possible to employ the shape of software function module
Formula is realized.The present invention is not restricted to the combination of the hardware and software of any particular form.
The preferred embodiments of the present invention are these are only, certainly, the present invention can also there are other various embodiments, without departing substantially from this
In the case of spirit and its essence, those skilled in the art work as can make various corresponding changes according to the present invention
And deformation, but these corresponding changes and deformation should all belong to the protection domain of appended claims of the invention.
Claims (4)
1. a kind of central processing unit, is specifically included：Traditional 16 bit CPUs, including：Decoding unit, execution unit, instruction buffer list
Member；Characterized in that, also including：
Instruction buffer selector；
The instruction buffer unit is two；
The decoding unit is used for according to the instruction generation instruction anticipation signal decoded；The instruction anticipation signal is used to indicate
Whether execution unit will perform jump instruction next time；
The instruction buffer selector is for when the instruction anticipation signal designation received, execution unit will to be performed next time
During jump instruction, another buffered instructions unit is switched to from the instruction buffer unit currently selected, the buffering being switched to is controlled
Command unit is read since the position of the program storage pointed by the jump instruction to be instructed and preserves；When redirecting
When, read instruction from the buffered instructions unit being switched to and be sent to the decoding unit；When the implementing result of the jump instruction
It is when not redirecting, to switch back into selected buffered instructions unit before switching and continue to read instruction；
When the implementing result of the jump instruction is not redirect, the instruction buffer selector is additionally operable to be switched to described
Buffered instructions unit sends and redirects invalid signals,
The buffered instructions unit being switched to receive the instruction buffer selector redirect invalid signals after empty institute
The instruction of storage；
Also include：
One bit accumulator, the useful signal that redirects for performing the jump instruction to the execution unit is added up, and will
Accumulation result is sent to the instruction buffer selector；
The instruction buffer selector chooses different instruction buffer units when redirecting according to the accumulation result, from
The instruction buffer unit chosen reads instruction and is sent to the decoding unit.
2. central processing unit as claimed in claim 1, it is characterised in that：
When redirecting, the instruction buffer unit that the instruction buffer selector is additionally operable to select to before the switching is sent not
Selected signal,
The instruction buffer unit selected before the switching empties institute after receiving the unselected signal of the instruction buffer selector
The instruction of storage.
3. a kind of command processing method, is applied in the central processing unit as described in claim any one of 1-2, including：
Decoding unit is used to indicate to hold next time according to the instruction generation instruction anticipation signal decoded, the instruction anticipation signal
Whether row unit will perform jump instruction；
When the instruction anticipation signal designation received, execution unit will perform jump instruction to instruction buffer selector next time
When, another buffered instructions unit is switched to from the instruction buffer unit currently selected, the buffered instructions unit being switched to is controlled
Read since the position of the program storage pointed by the jump instruction and instruct and preserve；When redirecting, from switching
To buffered instructions unit read instruction be sent to the decoding unit；When the implementing result of the jump instruction is not redirect
When, switch back into selected buffered instructions unit before switching and continue to read instruction；
When the implementing result of the jump instruction is not redirect, the instruction buffer selector is also to the buffering being switched to
Command unit sends and redirects invalid signals,
The buffered instructions unit being switched to receive the instruction buffer selector redirect invalid signals after empty institute
The instruction of storage；
Also include：
The useful signal that redirects that one bit accumulator performs the jump instruction to the execution unit is added up, and by cumulative knot
Fruit is sent to the instruction buffer selector；
The instruction buffer selector chooses different instruction buffer units when redirecting according to the accumulation result, from
The instruction buffer unit chosen reads instruction and is sent to the decoding unit.
4. method as claimed in claim 3, it is characterised in that：
When redirecting, the instruction buffer selector also sends unselected to the instruction buffer unit selected before the switching
Signal,
The instruction buffer unit selected before the switching empties institute after receiving the unselected signal of the instruction buffer selector
The instruction of storage.
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| CN201410276522.4A CN104020981B (en) | 2014-06-19 | 2014-06-19 | A kind of central processing unit and its command processing method |
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| CN107194246B (en) * | 2017-05-19 | 2020-10-02 | 中国人民解放军信息工程大学 | CPU for realizing dynamic instruction set randomization |
| CN112540792A (en) * | 2019-09-23 | 2021-03-23 | 阿里巴巴集团控股有限公司 | Instruction processing method and device |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US3614747A (en) * | 1968-10-31 | 1971-10-19 | Hitachi Ltd | Instruction buffer system |
| US4992932A (en) * | 1987-12-29 | 1991-02-12 | Fujitsu Limited | Data processing device with data buffer control |
| CN1675626A (en) * | 2002-08-12 | 2005-09-28 | 皇家飞利浦电子股份有限公司 | Instruction cache way prediction for jump targets |
-
2014
- 2014-06-19 CN CN201410276522.4A patent/CN104020981B/en active Active
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US3614747A (en) * | 1968-10-31 | 1971-10-19 | Hitachi Ltd | Instruction buffer system |
| US4992932A (en) * | 1987-12-29 | 1991-02-12 | Fujitsu Limited | Data processing device with data buffer control |
| CN1675626A (en) * | 2002-08-12 | 2005-09-28 | 皇家飞利浦电子股份有限公司 | Instruction cache way prediction for jump targets |
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