CN104011851B - 3D integrated antenna packages with window inserter - Google Patents

3D integrated antenna packages with window inserter Download PDF

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Publication number
CN104011851B
CN104011851B CN201180075817.XA CN201180075817A CN104011851B CN 104011851 B CN104011851 B CN 104011851B CN 201180075817 A CN201180075817 A CN 201180075817A CN 104011851 B CN104011851 B CN 104011851B
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China
Prior art keywords
tube core
inserter
semiconductor tube
semiconductor
substrate
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Active
Application number
CN201180075817.XA
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Chinese (zh)
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CN104011851A (en
Inventor
D·马利克
R·S·维斯瓦纳斯
S·斯里尼瓦桑
M·T·博尔
A·W·耶欧
S·阿格拉哈拉姆
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Intel Corp
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Intel Corp
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Publication of CN104011851A publication Critical patent/CN104011851A/en
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    • H01L23/13—Mountings, e.g. non-detachable insulating substrates characterised by the shape
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    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49838—Geometry or layout
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    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
    • H01L23/49816—Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Geometry (AREA)
  • Semiconductor Integrated Circuits (AREA)
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  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Structures For Mounting Electric Components On Printed Circuit Boards (AREA)

Abstract

Describe the 3D integrated antenna packages with window inserter and the method for forming this semiconductor packages.For example, semiconductor packages includes substrate.Top semiconductor tube core is arranged on substrate.Inserter with window is arranged between substrate and top semiconductor tube core and is mutually connected to substrate and top semiconductor tube core.Base semiconductor tube core is arranged in the window of inserter and is mutually connected to top semiconductor tube core.In another example, semiconductor packages includes substrate.Top semiconductor tube core is arranged on substrate.Inserter is arranged between substrate and top semiconductor tube core and is mutually connected to substrate and top semiconductor tube core.Base semiconductor tube core is arranged on and is connected in inserter identical plane and mutually top semiconductor tube core.

Description

3D integrated antenna packages with window inserter
Technical field
It, in field of semiconductor package, also, is with window inserter specifically that embodiments of the invention are (interposer) 3D integrated antenna packages and the method for forming this semiconductor packages.
Background technology
Consumption electronic product market of today often requires that the complicated function of the circuit for needing extremely complex.Zoom to more Carrying out smaller basic building block block (for example, transistor) can include more complicated with each progressive generation on singulated dies Circuit.Semiconductor packages is used to protect integrated circuit (IC) chip or tube core, and also for providing external electrical for tube core The electrical interface on road.With the growing demand to smaller electronic equipment, semiconductor packages be designed to it is more compact simultaneously And bigger current densities must be supported.Additionally, causing the demand of higher performance equipment to realizing processing simultaneous with subsequent components The thin encapsulation profile and the demand of the improved semiconductor packages of low overall warpage for holding.
The connection of C4 soldered balls is utilized many years, to provide the interconnection of the flip-chip between semiconductor devices and substrate. Flip-chip or controlled collapse chip connection (C4) be for semiconductor devices (such as, integrated circuit (IC) chip, MEMS or Part) installation type, the Setup Type replaces wire bond using solder bump.Solder bump is arranged in lining On the C4 pads of the top side of bottom package.In order to semiconductor devices is attached into substrate, semiconductor devices is by upside-down mounting --- and its is active Side is down on installation region.Solder bump is used to for semiconductor devices to be connected directly to substrate.However, the method is received The size of installation region limits and may be not easy to adapt to the tube core of stacking.
On the other hand, traditional lead connecting method may limit half can be reasonably included in single semiconductor packages The quantity of conductor tube core.Additionally, when attempting in substantial amounts of semiconductor die package to semiconductor packages, in fact it could happen that general Structure problem.
The method for packing (such as, silicon hole (TSV) and silicon inserter) of renewal obtains many concerns of designer to realize High performance multi-chip module (MCM) and system in package (SiP).However, being needed in the evolution of semiconductor packages additional Improve.
The content of the invention
Embodiments of the invention include the 3D integrated antenna packages with window inserter and are partly led as being formed The method of body encapsulation.
In embodiment, semiconductor packages includes substrate.Top semiconductor tube core is arranged on substrate.With window Inserter is arranged between substrate and top semiconductor tube core and is mutually connected to substrate and top semiconductor tube core.Base semiconductor pipe Core is arranged in the window of inserter and is mutually connected to top semiconductor tube core.
In another embodiment, semiconductor packages includes substrate.Top semiconductor tube core is arranged on substrate.Inserter It is arranged between substrate and top semiconductor tube core and is mutually connected to substrate and top semiconductor tube core.Base semiconductor tube core is set It is connected in inserter identical plane and mutually top semiconductor tube core.
In another embodiment, semiconductor element is to including top semiconductor tube core.Inserter is arranged on top semiconductor Tube core lower section is simultaneously mutually connected to top semiconductor tube core.Base semiconductor tube core be arranged on in inserter identical plane, and mutually It is connected to top semiconductor tube core.
Brief description of the drawings
Figure 1A shows the plan of the 3D integrated antenna packages with window inserter according to an embodiment of the invention.
Figure 1B shows 3D integrated antenna packages with window inserter of Figure 1A according to an embodiment of the invention Sectional view.
Fig. 2 shows another 3D integrated antenna packages with window inserter according to another embodiment of the present invention Sectional view.
Fig. 3 A and 3B respectively illustrate the plan and sectional view of the semiconductor element pair according to inventive embodiment.
Fig. 4 A and 4B respectively illustrate the plan of another semiconductor element pair of another embodiment according to invention and cut Face figure.
Fig. 5 A and 5B respectively illustrate the plan of another semiconductor element pair of another embodiment according to invention and cut Face figure.
Fig. 6 A and 6B respectively illustrate the plan of another semiconductor element pair of another embodiment according to invention and cut Face figure.
Fig. 7 A and 7B respectively illustrate the plan of another semiconductor element pair of another embodiment according to invention and cut Face figure.
Fig. 8 A and 8B respectively illustrate the plan of another semiconductor element pair of another embodiment according to invention and cut Face figure.
Fig. 9 shows is used for 3D integrated antenna package of the manufacture with window inserter according to an embodiment of the invention The flow chart of method.
Figure 10 shows the 3D integrated circuits for manufacturing with window inserter according to another embodiment of the present invention The flow chart of the other method of encapsulation.
Figure 11 is the schematic diagram of computer system according to an embodiment of the invention.
Describe in detail
Describe the 3D integrated circuits with window inserter and the method for forming this semiconductor packages.Following In description, substantial amounts of detail is set forth, architecture and material ranges are such as encapsulated, to provide to implementation of the invention Example be fully understood by.However, will be apparent to one skilled in the art being, there is no these specific details to implement this yet Inventive embodiment.In other instances, the known feature of such as IC design layout etc is not described in, with Just embodiments of the invention will not unnecessarily be obscured.Further, it will be appreciated that the multiple embodiments shown in figure are exemplary expressions And it is not drawn necessarily to scale.
One or more embodiment purposes described herein are to introduce for three-dimensional (3D) integrated circuit (IC) envelope The window inserter of dress.For example, silicon inserter can be used for CPU and memory and the 3D stackings of other devices.One or more Embodiment is to 10 nanometer nodes and the above and surmounts product and is particularly useful.Some embodiments introduce for high density interconnection (for example, Reroute and be fanned out to) formed silicon inserter.Can according to the streamline for the interconnection layer on semiconductor IC die at The rear end of reason similar mode processes silicon inserter.
Conventional silicon inserter generally takes up the flood under active die.And, the IC of conventional 3D stackings is usual Need through one or more silicon holes (TSV) of formation in active die.TSV through active die is expensive 's.And, in the IC structures of 3D stackings, it is often necessary to the redistribution layer (RDL) on the back side of this bottom active die To manage TSV and tube core to the layout of tube core interconnection (for example, LMI pads).RDL interconnection lines long can influence High Speed I/O performances.Cause This, one or more embodiments described herein realizes 3D IC heaps in the case of not having TSV in any one of active die It is folded.And, in embodiment, including at least one of silicon inserter and active die layer hang down with the shared identical of inserter Straight plane, so as to save Z height.
In embodiment, silicon inserter is included under top active die (T) and provides under top die Window so that bottom active die (B) can be directly stacked upon below top die.Bottom active die and inserter are resident In same vertical level in 3D stepped constructions.In one such embodiment, can not need active die any one In TSV in the case of realize the 3D IC stackings of two active dies.Inserter is attached to encapsulation by middle rank interconnection (MLI) Substrate.Inserter includes that TSV, the TSV provide the vertical circuit footpath between package substrate to active die.In embodiment, MLI raised pads are further included on the active die of bottom.Silicon inserter benefit (such as, raised pad spacing conversion, it is passive Device is integrated, ILD protection etc.) can be maintained in new architecture described herein.In embodiment, inserter material is Silicon.However, alternative use or also usable glass, organic matter or ceramics.
Described herein and about one or more embodiments features include, but not limited to (a) to provide at top Window under active die is designed to the mode of top active die and assembles silicon for directly stacking bottom active die Inserter, (b) inserter and bottom active die are resided in the same vertical level in 3D stackings, and (c) is need not be active Realized in the case of TSV in any one in tube core 3D IC stack, the TSV of (d) in bottom die be it is optional, with And the displacement and combination of (e) (a)-(d).
Used as the example of universal covered herein, Figure 1A shows has window according to an embodiment of the invention The plan of the 3D integrated antenna packages of inserter.Figure 1B shows being inserted with window for Figure 1A according to an embodiment of the invention Enter the sectional view of the 3D integrated antenna packages of device.
Reference picture 1A and 1B, semiconductor packages 100 (or part of semiconductor packages) include the top semiconductor of substrate 102. Tube core 104 is set on the substrate 102.Inserter 106 with window 108 is arranged on substrate 102 and top semiconductor tube core 104 Between and be mutually connected to substrate 102 (for example, by middle rank interconnection (MLI) 110) and top semiconductor tube core 104 (for example, passing through The first order interconnects (FLI) 112).Base semiconductor tube core 114 is arranged in the window 108 of inserter 106 and is mutually connected to top Semiconductor element 104 (for example, by interconnection 116).Base semiconductor tube core 114 is not without silicon hole (TSV) and directly mutual It is connected to substrate 102.Alternatively, active side of the active side 118 of base semiconductor tube core 114 in face of top semiconductor tube core 104 120, and away from substrate 102.Embodiments in accordance with the present invention, base semiconductor tube core 114 is arranged on the closure of inserter 106 Window 108 in, as shown in Figure 1A, wherein window 106 surrounds bottom die 114 completely.In embodiment, also show in such as Figure 1A Go out, top semiconductor tube core 104 covered base semiconductor tube core 114 completely.Therefore, in embodiment, 3D encapsulation does not include TSV in active die and comprising the top and bottom tube core of face-to-face layout.
In embodiment, window inserter 106 is made up of silicon.However, other embodiment is included by such as, but it is not limited to, The window inserter of the material composition of glass, ceramics or organic material etc.In embodiment, window inserter 106 can with or Active device can not be included.In embodiment, window inserter 106 has high density interconnection, silicon hole (TSV) and between fin Away from micro- raised pad.
In embodiment, bottom active die 114 represents non-stacking (one single chip) or (multiple chips) cloth for stacking Office.In embodiment, bottom die 114 is simulation or storage component part.In embodiment, top active die 104 represents single Individual chip or side by side (for example, multi-chip package (MCP)) layout, side-by-side configuration is more fully described below in relation to Fig. 6 A and 6B. In embodiment, top active die 104 is through thickness or is thinned (or the tube core including stacking).In embodiment, bottom Tube core 104 is CPU or storage component part.
The IC frameworks of conventional 3D stackings generally need the TSV through at least one of active die.Through there is source capsule The TSV of core is expensive, at least partially due to the cost being associated in itself with generation TSV.And, expensive die area can Consumed plus TSV exclusionary zones by TSV.Therefore, at least some offers in embodiment herein be used for 3D encapsulation without TSV Method.
In embodiment, top semiconductor tube core 104 is configured to be powered to base semiconductor tube core 114.In embodiment In, top semiconductor tube core 104 is configured to promote the communication between base semiconductor tube core 114 and substrate 102, for example, logical The wiring crossed in substrate 102.In embodiment, base semiconductor tube core 104 does not have silicon hole (TSV).Therefore, can be by top Interconnection line and inserter 106 on portion's tube core 104 realize the connection between bottom die 114 and substrate 102 indirectly.Cause This, reference picture 1A, for 3D IC, bottom and top active die are stacked face-to-face.It is to be appreciated, however, that in alternative embodiment In, such as relevant Fig. 2 in greater detail, can be directly connected to bottom die by using the TSV in bottom die.
One or two in semiconductor element 104 or 114 can be formed by Semiconductor substrate, such as monocrystalline substrate.Also It is contemplated that such as, but be not limited to, the other materials of III-V material and germanium or silicon germanium material substrate etc.Semiconductor element 104 Or 114 active side (being respectively 120 or 118) can be the side for being formed on semiconductor devices.In embodiment, semiconductor The active side 120 or 118 of tube core 104 or 114 includes multiple semiconductor devices respectively, such as, but is not limited to transistor, capacitor And resistor, the transistor, capacitor and resistor are interconnected in functional circuit so as to be formed together by tube core interconnection structure Integrated circuit.As skilled in the art will appreciate, the device-side of semiconductor element includes thering is integrated circuit and interconnection Active part.According to some different embodiments, semiconductor element can be including but not limited to microprocessor (monokaryon is more Core), memory device, chipset, graphics device, any suitable IC-components of application specific integrated circuit etc.
The die arrangement 100 of stacking can be particularly suitable for encapsulating memory dice and logic dice.For example, in embodiment In, one in tube core 104 or 114 is memory dice.Another tube core is logic dice.In an embodiment of the present invention, deposit Memory die is memory device, such as, but is not limited to, static RAM (SRAM), dynamic ram (DRAM), nonvolatile memory (NVM), and logic dice is logical device, such as, but is not limited to, microprocessor sum Word signal processor.
Embodiments in accordance with the present invention, tube core interconnection structure 112 or 116 or inserter 106 arrive the interconnection structure of substrate 102 One or more in 110 are made up of the array of metal bump pad.In one embodiment, each metal bump pad is by all Such as, but it is not limited to, the metal composition of copper, gold or nickel etc.Substrate 102 can be flexible substrate or rigidity according to concrete application Substrate.In embodiment, substrate 102 has multiple electric traces being disposed therein.In embodiment, external contact can be also formed Layer.In one embodiment, outer contact layer includes BGA (BGA).In other embodiments, outer contact layer includes all Such as, but it is not limited to, the array of array (PGA) of plane grid array (LGA) or pin etc.In embodiment, using soldered ball, And soldered ball is made up of or without wire, such as, the alloy of gold and tin solder or silver and tin solder wire.
Used as another example of universal covered herein, Fig. 2 shows according to another embodiment of the present invention The sectional view of another 3D integrated antenna packages with window inserter.
Reference picture 2, semiconductor packages 200 (or part of semiconductor packages) includes substrate 202.Top semiconductor tube core 204 are set on the substrate 202.Inserter 206 with window 208 is arranged between substrate 202 and top semiconductor tube core 204 And substrate 202 (for example, by middle rank interconnection (MLI) 210) and top semiconductor tube core 204 are mutually connected to (for example, by first Level interconnection (FLI) 212).Base semiconductor tube core 214 is arranged in the window 208 of inserter 206 and is mutually connected to top and partly leads Body tube core 204 (for example, by interconnection 216).Base semiconductor tube core 214 has silicon hole (TSV) 250 and for example, passes through Interconnect 252 direct interconnections to substrate 202.Equally, the active side 218 of base semiconductor tube core 214 is back to top semiconductor tube core 204 active side 220, and towards substrate 202.Embodiments in accordance with the present invention, base semiconductor tube core 214 is arranged on insertion In the window 208 of the closure of device 206, wherein window 206 surrounds bottom die 214 completely.In embodiment, top semiconductor pipe Core 204 covered base semiconductor tube core 214 completely.Therefore, in embodiment, 3D encapsulation is including with TSV and MLI and relatively In top die face facing away to bottom die.Encapsulated tube core and the characteristic of the material of encapsulation 200 and configuration can be It is same or similar described by 100 with above in relation to encapsulating.
Generally speaking, in embodiment, the IC package stacked referring again to Figure 1A, 1B and 2,3D includes window-insertion Device.Inserter provides the window under the active die of top for the 3D encapsulation of top and bottom active die.Fig. 3 A/3B, 4A/ B, 5A/B, 6A/B, 7A/B and 8A/B show that the multiple of the IC top and bottom tube core pair of the stacking with window inserter is real Apply example.Such as on Fig. 9 in greater detail, these are to can finally be encapsulated on substrate.
In the first example, including the window with single closure (for example, the window for surrounding completely) inserter.Fig. 3 A With the plan and sectional view that 3B respectively illustrates the semiconductor element pair according to inventive embodiment.
Reference picture 3A and 3B, semiconductor element include top semiconductor tube core 304 to 300.Inserter 306 is arranged on top It is connected under semiconductor element 304 and mutually top semiconductor tube core 304 (for example, (FLI) 312 is interconnected by the first order).Bottom Portion's semiconductor element 314 be arranged on in the identical plane of inserter 306 and be mutually connected to top semiconductor tube core 304 (for example, By interconnection 316).Base semiconductor tube core 314 is arranged in the window 308 of the closure of inserter 306.In embodiment, such as Shown in Fig. 3 A, top semiconductor tube core 304 covered base semiconductor tube core 314 completely.Tube core and tube core to 300 material spy Property and configuration can be to described same or similar with the tube core above in relation to encapsulation 100 or 200.
In the second example, including the inserter with multiple windows (for example, the window for surrounding completely) for closing.Fig. 4 A With the plan and sectional view of another semiconductor element pair that 4B respectively illustrates another embodiment according to invention.
Reference picture 4A and 4B, semiconductor element include top semiconductor tube core 404 to 400.Inserter 406 is arranged on top It is connected under semiconductor element 404 and mutually top semiconductor tube core 404 (for example, (FLI) 412 is interconnected by the first order).Four Individual base semiconductor tube core 414,460,462 and 464 is arranged on and is connected in the identical plane of inserter 406 and mutually top half Conductor tube core 404 (for example, by interconnection 416).Base semiconductor tube core 414,460,462 and 464 each be arranged on inserter In the window (408,470,472 and 474) of 406 respective closure.In embodiment, as shown in Figure 4 A, top semiconductor pipe Core 404 covered base semiconductor tube core 414,460,462 and 464 completely.Tube core and tube core to 400 material characteristic and configuration Can be to described same or similar with the tube core above in relation to encapsulation 100 or 200.
In the 3rd example, including the inserter with multiple windows (for example, window that only part surrounds) opened.Figure 5A and 5B respectively illustrate the plan and sectional view of another semiconductor element pair of another embodiment according to invention.
Reference picture 5A and 5B, semiconductor element include top semiconductor tube core 504 to 500.Inserter 506 is arranged on top It is connected under semiconductor element 504 and mutually top semiconductor tube core 504 (for example, (FLI) 512 is interconnected by the first order).Bottom Portion's semiconductor element 514 is arranged on the identical plane of inserter 506, and is mutually connected to the (example of top semiconductor tube core 504 Such as, by interconnection 516).Base semiconductor tube core 514 is arranged in the window 508 of the opening of inserter 506.In embodiment, As shown in Figure 5A, top semiconductor tube core 504 only partially covered base semiconductor tube core 514.The (not shown) in embodiment, Bottom die is bigger than top die.Tube core and tube core to 500 material characteristic and configuration can be with above in relation to encapsulation 100 Or 200 tube core to described same or similar.
In the 4th example, multiple top dies are included in the centering with window inserter in couples.Fig. 6 A and 6B point The plan and sectional view of another semiconductor element pair according to another embodiment invented are not shown.
Reference picture 6A and 6B, semiconductor element include top semiconductor tube core 604 to 600.Inserter 606 is arranged on top It is connected under semiconductor element 604 and mutually top semiconductor tube core 604 (for example, (FLI) 612 is interconnected by the first order).Bottom Portion's semiconductor element 614 is arranged on the identical plane of inserter 606, and is mutually connected to the (example of top semiconductor tube core 604 Such as, by interconnection 616).Base semiconductor tube core 614 is arranged in the window 606 of the closure of inserter 606.Including one or The additional top semiconductor tube cores 680 of multiple, and one or more additional top semiconductor tube cores 680 are arranged on and top In the identical plane of semiconductor element 604, and mutually it is connected to inserter (for example, (FLI) 613 is interconnected by the first order).In reality Apply in example, as shown in Figure 6A, top semiconductor tube core 604 covered base semiconductor tube core 614 completely.Tube core and tube core are to 600 Material characteristic and configuration can be to described same or similar with the tube core above in relation to encapsulation 100 or 200.
In the 5th example, including the multi-part inserter with the window (for example, the window for surrounding completely) for closing.Figure 7A and 7B respectively illustrate the plan and sectional view of another semiconductor element pair of another embodiment according to invention.
Reference picture 7A and 7B, semiconductor element include top semiconductor tube core 704 to 700.Inserter 706 is arranged on top It is connected under semiconductor element 704 and mutually top semiconductor tube core 704 (for example, (FLI) 712 is interconnected by the first order).Insert Enter device 706 by two or more separate units (in this case, four separate units 706A, 706B, 706C and 707D) group Into.Base semiconductor tube core 714 is arranged on the identical plane of inserter 706, and is mutually connected to top semiconductor tube core 704 (for example, by interconnection 716).Base semiconductor tube core 714 is arranged in the window 708 of the closure of inserter 706.It is specific and Speech, base semiconductor tube core 714 be arranged on inserter 706 two or more separate units (in this case, four it is discrete Unit 706A, 706B, 706C and 707D) closure window 708 in.In embodiment, as shown in Figure 7 A, top semiconductor pipe Core 704 covered base semiconductor tube core 714 completely.Tube core and tube core to 700 material characteristic and configuration can be and the above For encapsulation 100 or 200 tube core to described same or similar.
In the 6th example, bottom die is abreast included in inserter identical plane.Fig. 8 A and 8B show respectively The plan and sectional view of another semiconductor element pair according to another embodiment invented are gone out.
Reference picture 8A and 8B, semiconductor element include top semiconductor tube core 804 to 800.Inserter 806 is arranged on top It is connected under semiconductor element 804 and mutually top semiconductor tube core 804 (for example, (FLI) 812 is interconnected by the first order).Bottom Portion's semiconductor element 814 is arranged on the identical plane of inserter 806, and is mutually connected to the (example of top semiconductor tube core 804 Such as, by interconnection 816).Base semiconductor tube core 814 adjoins inserter 806 and sets, but not in inserter 806.In embodiment In, as shown in figs. 8 a and 8b, top semiconductor tube core 804 only partially covered base semiconductor tube core 814.Tube core and tube core pair The characteristic of 800 material and configuration can be to described same or similar with the tube core above in relation to encapsulation 100 or 200.
Referring again to Fig. 3 A/3B, 4A/B, 5A/B, 6A/B, 7A/B and 8A/B, in embodiment, each to respective bottom Portion's semiconductor element does not have silicon hole (TSV).In embodiment, the active side of base semiconductor tube core is to top semiconductor The active side of tube core.In another embodiment, each to respective base semiconductor tube core there is silicon hole (TSV).In reality In applying example, the active side of the active side of base semiconductor tube core back to top semiconductor tube core.It will be understood that, it is also contemplated that on figure Multiple arrangements and combination of the tube core pair of 3A/3B, 4A/B, 5A/B, 6A/B, 7A/B and 8A/B description.For example, in embodiment, Can manufacture tube core to 400 and 500 or 400 and 600 or 400,500 and 600 or 800 and 400 feature combination or other Such combination.
On the other hand, a kind of side for manufacturing the 3D integrated antenna packages with window inserter provided herein Method.In the first example, Fig. 9 shows and be used for according to an embodiment of the invention 3D integrated electricity of the manufacture with window inserter The flow chart 900 of the method for road encapsulation.
The process flow 900 of reference picture 9, the part of top die 902 of flow includes providing with adhesive tape (tape) and spool (reel) top die of form 910.The part of bottom die 904 of flow includes providing with adhesive tape and spool form 912 Bottom die.Hot compression is subsequently used for stacking bottom die in top die 914 with reference to (TCB).The window inserter of flow 906 parts may include to provide to be had window and may have TSV, middle rank to interconnect (MLI) raised pad and first order interconnection (FLI) inserter of pad.In 916, make the inserter (such as, silicon inserter) with TSV and redistribution layer (RDL) from The chip of reason is separated and on dicing tape.Laser and/or water jet cutting can be used to provide window.In 918, Engaged with inserter from 914 stacking (for example, passing through TCB).The part of package substrate 908 of flow include provide for example, The package substrate on pallet in such as 920.In 922, the middle rank on inserter window interconnects CAM and/or the copper bottom of (MLI) Filling (CUF) is used to couple tube core pair with the window inserter in package substrate.Therefore, it is first referring again to process flow 900 First pass through bottom die, top die and window inserter 3D stacking be initially formed FLI, then MLI be used for will be to being attached to Package substrate.It will be understood that, bottom die may or may not have MLI raised pads.Additionally, window inserter can be by multiple zero Part is constituted.And, centering may include additional tube core.
Including the tube core pair of inserter can be manufactured as a part for encapsulation process therefore,.As described by Fig. 9, Then any one of various multiple tube core centerings including inserter can be coupled to package substrate.Therefore, in embodiment, half Conductor encapsulation includes substrate.Top semiconductor tube core is arranged on substrate.Inserter with window is arranged on substrate and top It is connected between semiconductor element and mutually substrate and top semiconductor tube core.Base semiconductor tube core is arranged on the window of inserter In and be mutually connected to top semiconductor tube core.
In such embodiment, as described by Fig. 3 A, base semiconductor tube core is arranged on closing for inserter In the window of conjunction.In specific such embodiment, as described by also on Fig. 3 A and 3B, top semiconductor tube core was covered completely Base semiconductor tube core.
In another such embodiment, including one or more additional base semiconductor tube cores.Such as on Fig. 4 A and 4B Described, one or more additional base semiconductor tube cores are arranged on the window of one or more additional closures of inserter In mouthful.In specific such embodiment, as described by also on Fig. 4 A and 4B, top semiconductor tube core covered bottom half completely Conductor tube core and one or more additional base semiconductor tube cores.
In another such embodiment, as described by Fig. 5 A and 5B, base semiconductor tube core is arranged on inserter Opening window in.In specific such embodiment, as described by also on Fig. 5 A and 5B, top semiconductor tube core only portion Covered base semiconductor tube core with dividing.
In another such embodiment, including one or more additional top semiconductor tube cores.Such as on Fig. 6 A and 6B Described, one or more additional top semiconductor tube cores are arranged on lining in top semiconductor tube core identical plane It is connected on bottom and mutually inserter.In specific such embodiment, as described by also on Fig. 6 A and 6B, top semiconductor pipe Core covered base semiconductor tube core completely.
In another such embodiment, inserter is made up of two or more separative elements.As retouched on Fig. 7 A and 7B State, base semiconductor tube core is arranged in the window of the closure of two or more separate units of inserter.Specific such In embodiment, as described by also on Fig. 7 A and 7B, top semiconductor tube core covered base semiconductor tube core completely.
In another embodiment, semiconductor packages includes substrate.Top semiconductor tube core is arranged on substrate.Inserter sets Put between substrate and top semiconductor tube core and be mutually connected to substrate and top semiconductor tube core.Base semiconductor tube core is set It is connected in inserter identical plane and mutually top semiconductor tube core.In such embodiment, such as on Fig. 8 A With described by 8B, base semiconductor tube core adjoins inserter setting, but not in inserter.In specific such embodiment, As described by also on Fig. 8 A and 8B, top semiconductor tube core closely partly covered base semiconductor tube core.
The various tube cores pair referring again to more than, in embodiment, base semiconductor tube core without silicon hole (TSV) and Direct interconnection is not to substrate.In embodiment, the active side of base semiconductor tube core to the active side of top semiconductor tube core, And away from substrate.In another embodiment, base semiconductor tube core has silicon hole (TSV) and direct interconnection is to substrate. In embodiment, the active side of base semiconductor tube core back to top semiconductor tube core active side, and towards substrate.
In the second example, Figure 10 shows and be used for according to an embodiment of the invention 3D of the manufacture with window inserter The flow chart 1000 of the method for integrated antenna package.
The process flow 1000 of reference picture 10, the part of top die 1002 of flow includes providing with adhesive tape and spool form 1010 top die.The part of bottom die 1004 of flow includes providing with adhesive tape and the bottom die of spool form 1012. Hot compression is subsequently used for stacking bottom die in top die 1014 with reference to (TCB).The part of window inserter 1006 of flow May include to provide has window and may have TSV, middle rank to interconnect (MLI) raised pad and first order interconnection (FLI) pad Inserter.In 1016, make the inserter (such as, silicon inserter) with TSV and redistribution layer (RDL) from the chip for the treatment of Separate and on dicing tape.Laser and/or water jet cutting can be used to provide window.The package substrate of flow 1008 parts include providing the package substrate for example, on pallet in such as 1018.In 1020, from the insertion of 1016 window Device (for example, passing through TCB or CAM/CUF) is engaged with substrate.In 1022, from 1014 stacking for example, passing through TCB or CAM And/or CUF is engaged with inserter/substrate combination (coming from 1020).Therefore, referring again to process flow 1000, it is initially formed MLI.It will be understood that, bottom die may or may not have MLI raised pads.Additionally, window inserter can be by multiple part groups Into.And, centering may include additional tube core.
Many other options can be used for assembling and WIP tube cores pair with window inserter for encapsulation.Optimal option can Used depending on required size characteristic (the related die-size such as being laminated) size of overhanging, process huge profit etc..
At least some in for embodiment described herein, top die heat management includes using such as, but does not limit In being directly attached to the feature of heat sink or integrated heat dissipation area (HIS) at the back side of top die etc.Implementation described herein Example can realize 3D IC packages in the case of the TSV in not needing active die.And, it may include silicon inserter it is traditional excellent Gesture.
In embodiment, go to first order interconnection (FLI) spacing conversion of loose middle rank interconnection (MLI) spacing for More inexpensive encapsulation and package technique.In embodiment, passive component (for example, capacitor, resistor or inductor) is set In counting inserter.In embodiment, the stress that active die layer dielectric (ILD) drives with encapsulation (for example, MLI) is realized Decoupling.However, in alternate embodiments, another active die with TSV and MLI raised pads is used to replace inserter.
In embodiment, the FLI raised pad spacing for bottom die and window inserter is different, for example, more Fine spacing is used for bottom die/top die FLI (for example, about 40 microns of spacing) to realize high bandwidth, and loosely Spacing be used to window inserter/top die FLI (for example, be more than 90 microns of spacing) realize bigger face expected from FLI Product.In such embodiment, the method produces the bimodulus raised pad in top die to be highly distributed.However, due to Bottom die and window inserter are independently attached to corresponding top die, and it is probably easily to manage that bimodulus raised pad is highly distributed Reason.In specific such embodiment, the weldering on the tube core for top die or bottom die/window inserter layer is used Material.In embodiment, FLI underfill options include, but not limited to WLUF, (b) window inserter in (a) top die With bottom die EF-TCB, (c) copper bottom filling (CUF) or (d) MUF.
One or more embodiments described herein can realize multiple memory (such as, the JEDEC I/ wide in broadband high of stacking Memory), multiple other gadgets (or in terms of this, any other logic dice) under CPU.And, implementing In example, contribute to reduce die-size and packaging cost using silicon inserter.In embodiment, the introducing on silicon inserter, Allow that there is I/O to count the logic chip for increasing due to bandwidth of memory and/or due to the new feature such as in SoC.Such as Fruit logic dice keeps smaller to realize lower cost, it may be necessary to I/O raised pad density higher, so as to need in encapsulation Finer raised pad spacing and finer feature (for example, line/space/through hole etc.) on substrate, so as to cause more Packaging cost high.In embodiment, by using silicon inserter, by realizing that tube core reduces the coarse features with lower cost Substrate realizes relatively low product cost.
One or more embodiments of the invention provides 3D IC stackings (such as, inexpensive CPU and storage stack) to meet High product performance under low-power.In embodiment, on active die without TSV in the case of realize CPU's and eDREAM Stack and contribute to realize low cost.In embodiment, silicon inserter is used to manage the I/O density high in logic dice.Class As, embodiment may be directed to 3D IC piling operations to increase the memory on CPU/GPU.In embodiment, inserter with into This effective manner is combined with 3D IC and realized using silicon inserter in the case of not having TSV in active die active The 3D stackings of tube core.
Figure 11 is the schematic diagram of computer system 1100 according to an embodiment of the invention.The computer system described 1100 (also referred to as electronic systems 1100) can embody in some the disclosed embodiments any one and in the disclosure The 3D integrated antenna packages with window inserter of their equivalence stated.Computer system 1100 can be all Such as the mobile device of netbook computer.Computer system 1100 can be the mobile device of such as intelligent wireless phone.Calculate Machine system 1100 can be desktop computer.Computer system 1100 can be handheld reader.
In embodiment, electronic system 1100 is computer system, and the computer system includes being used to be electrically coupled Department of Electronics The system bus 1120 of multiple parts of system 1100.System bus 1120 is single bus or the bus according to each embodiment Any combinations.Electronic system 1100 includes the voltage source 1130 powered to integrated circuit 1110.In certain embodiments, voltage source 1130 are provided to integrated circuit 1110 electric current by system bus 1120.
Integrated circuit 1110 is electrically coupled to system bus 1120 and including any circuit, or according to the circuit of embodiment Combination.In embodiment, it can be any kind of processor 1112 that integrated circuit 1110 includes.As it is used herein, place Reason device 1112 can refer to any kind of circuit, such as, but be not limited to, microprocessor, microcontroller, graphic process unit, numeral Signal processor or other processors.In embodiment, processor 1112 is the 3D with window inserter disclosed herein Integrated antenna package.In embodiment, SRAM embodiments find in the memory cache of processor.May include integrated Other kinds of circuit in circuit 1110 is custom circuit or application specific integrated circuit (ASIC), for example, such as cell phone, The wireless device of smart phone, pager, portable computer, two-way radios and similar electronic system etc The middle telecommunication circuit 1114 for using.In embodiment, processor 1110 include such as static RAM (SRAM) it Memory 1116 on the tube core of class.In embodiment, processor 1110 includes such as embedded type dynamic random access memory Etc (eDRAM) memory 1116 on embedded tube core.
In embodiment, integrated circuit 1110 is complementary with later integrated circuit 1111.Useful embodiment is included at double Memory 1117 (such as SRAM) on reason device 1113 and dual communication circuit 1115 and dual-die.In embodiment, double integrated circuit Memory 1117 on the 1110 embedded tube cores for including such as eDRAM etc.
In embodiment, electronic system 1100 also include external memory storage 1140, one or more hard disk drives 1144, And/or treatment removable medium 646 (such as floppy disk, CD (CD), digital variable disk (DVD), flash drive and ability Other removable mediums known to domain) one or more drivers, its external memory 1140 may include to be suitable for spy again One or more memory components of fixed application (such as with the main storage 1142 of RAM forms).External memory storage 1140 may be used also Being such as with the in-line memory 1148 of the 3D integrated antenna packages with window inserter according to embodiment.
In embodiment, electronic system 1100 also includes display device 1150, audio output 1160.In embodiment, electricity Subsystem 1100 includes input unit, and such as controller 1170, the controller 1170 can be keyboard, mouse, touch pad, small key Disk, trace ball, game console, microphone, speech recognition equipment or enter information into electronic system 1100 any other is defeated Enter device.In embodiment, input unit 1170 is camera.In embodiment, input unit 1170 is digital audio tape.In reality Apply in example, input unit 1170 is camera and digital audio tape.
It is as shown here, can such as include any in some the disclosed embodiments and their equivalents Individual 3D integrated antenna packages with window inserter, electronic system, computer system, one or many of manufacture integrated circuit Integrated circuit is realized in the multiple different embodiment of one or more method of individual method and manufacture electronic building brick etc 1110, the electronic building brick includes being illustrated in multiple embodiments and their art-recognized equivalence according to herein Some the disclosed embodiments in the 3D integrated antenna packages with window inserter of any one.The unit of operation can be changed , to be adapted to specific I/O couplings needs, I/O couplings need to include according to some for part, material, geometry, size and order Any one array in disclosed 3D integrated antenna packages embodiment and their equivalents with window inserter Contact counting, the array contact configuration that the microelectronic core in substrate is installed for being embedded in processor.
Therefore, the 3D integrated circuits with window inserter and the side for forming this semiconductor packages are had been disclosed for Method.In embodiment, semiconductor packages includes substrate.Top semiconductor tube core is arranged on substrate.Inserter with window It is arranged between substrate and top semiconductor tube core and is mutually connected to substrate and top semiconductor tube core.Base semiconductor tube core sets Put in the window of inserter and be mutually connected to top semiconductor tube core.In another embodiment, semiconductor packages includes substrate. Top semiconductor tube core is arranged on substrate.Inserter is arranged between substrate and top semiconductor tube core and is mutually connected to substrate With top semiconductor tube core.Base semiconductor tube core is arranged on and is connected in inserter identical plane and mutually top semiconductor Tube core.

Claims (18)

1. a kind of semiconductor packages, including：
Substrate；
Top semiconductor tube core, the top semiconductor tube core is arranged on substrate；
Inserter with window, the inserter be arranged between substrate and top semiconductor tube core and be mutually connected to substrate and Top semiconductor tube core；And
Base semiconductor tube core, the base semiconductor tube core is arranged in the window of inserter, and is mutually connected to the top Semiconductor element, wherein, from top-down angle, the top semiconductor tube core only partially covered the base semiconductor Tube core, the top semiconductor tube core is arranged on the base semiconductor tube core top, and the base semiconductor tube core sets Put above the External conductive contact of the inserter.
2. semiconductor packages as claimed in claim 1, it is characterised in that the base semiconductor tube core does not include silicon hole (TSV) and not direct interconnection is not to the substrate.
3. semiconductor packages as claimed in claim 1, it is characterised in that the active side of the base semiconductor tube core is to institute State the active side of top semiconductor tube core, and back to the substrate.
4. semiconductor packages as claimed in claim 1, it is characterised in that the base semiconductor tube core includes silicon hole And direct interconnection is to the substrate (TSV).
5. semiconductor packages as claimed in claim 1, it is characterised in that the active side of the base semiconductor tube core is back to institute State the active side of top semiconductor tube core, and towards the substrate.
6. semiconductor packages as claimed in claim 1, it is characterised in that the base semiconductor tube core is arranged on the insertion In the window of the opening of device.
7. semiconductor packages as claimed in claim 1, it is characterised in that further include one or more additional tops half Conductor tube core, one or more of additional top semiconductor tube cores are in the top semiconductor tube core identical plane Set over the substrate and be mutually connected to the inserter.
8. a kind of semiconductor packages, including：
Substrate；
Top semiconductor tube core, the top semiconductor tube core is arranged on substrate；
Inserter, the inserter is arranged between substrate and top semiconductor tube core and is mutually connected to substrate and top semiconductor Tube core；And
Base semiconductor tube core, the base semiconductor tube core is arranged on inserter identical plane, and is mutually connected to institute Top semiconductor tube core is stated, wherein, from top-down angle, the top semiconductor tube core only partially covered the bottom Semiconductor element, the top semiconductor tube core is arranged on the base semiconductor tube core top, and the base semiconductor Tube core is arranged on the External conductive contact top of the inserter.
9. semiconductor packages as claimed in claim 8, it is characterised in that the base semiconductor tube core adjoins the inserter Set, and not in the inserter.
10. semiconductor packages as claimed in claim 8, it is characterised in that the base semiconductor tube core does not include silicon hole (TSV) and not direct interconnection is not to the substrate.
11. semiconductor packages as claimed in claim 8, it is characterised in that the active side pair of the base semiconductor tube core The active side of the top semiconductor tube core, and back to the substrate.
12. semiconductor packages as claimed in claim 8, it is characterised in that the base semiconductor tube core includes silicon hole And direct interconnection is to the substrate (TSV).
13. semiconductor packages as claimed in claim 8, it is characterised in that the active side of the base semiconductor tube core back to The active side of the top semiconductor tube core, and towards the substrate.
A kind of 14. semiconductor elements pair, including：
Top semiconductor tube core；
Inserter, the inserter is arranged under top semiconductor tube core and is mutually connected to top semiconductor tube core；And
Base semiconductor tube core, the base semiconductor tube core is arranged on inserter identical plane, and is mutually connected to institute Top semiconductor tube core is stated, wherein, from top-down angle, the top semiconductor tube core only partially covered the bottom Semiconductor element, the top semiconductor tube core is arranged on the base semiconductor tube core top, and the base semiconductor Tube core is arranged on the External conductive contact top of the inserter.
15. semiconductor elements pair as claimed in claim 14, it is characterised in that the base semiconductor tube core is arranged on described In the window of the opening of inserter.
16. semiconductor elements pair as claimed in claim 14, it is characterised in that further include one or more additional tops Portion's semiconductor element, one or more of additional top semiconductor tube cores are arranged on identical with the top semiconductor tube core Plane in and be mutually connected to the inserter.
17. semiconductor elements pair as claimed in claim 14, it is characterised in that the base semiconductor tube core adjoins described inserting Enter device setting, but not in the inserter.
18. semiconductor elements pair as claimed in claim 14, it is characterised in that the base semiconductor tube core is not logical including silicon Hole (TSV), and wherein described base semiconductor tube core active side to the active side of the top semiconductor tube core.
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US20150332994A1 (en) 2015-11-19
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