CN104003348A - Method for mems structure with dual-level structural layer and acoustic port - Google Patents
Method for mems structure with dual-level structural layer and acoustic port Download PDFInfo
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- CN104003348A CN104003348A CN201410068355.4A CN201410068355A CN104003348A CN 104003348 A CN104003348 A CN 104003348A CN 201410068355 A CN201410068355 A CN 201410068355A CN 104003348 A CN104003348 A CN 104003348A
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Abstract
A method for fabricating a MEMS device includes depositing and patterning a first sacrificial layer onto a silicon substrate, the first sacrificial layer being partially removed leaving a first remaining oxide. Further, the method includes depositing a conductive structure layer onto the silicon substrate, the conductive structure layer making physical contact with at least a portion of the silicon substrate. Further, a second sacrificial layer is formed on top of the conductive structure layer. Patterning and etching of the silicon substrate is performed stopping at the second sacrificial layer. Additionally, the MEMS substrate is bonded to a CMOS wafer, the CMOS wafer having formed thereupon a metal layer. An electrical connection is formed between the MEMS substrate and the metal layer.
Description
The cross reference of related application
The application requires the people such as Daneman in U.S. Provisional Application No. 61/770 submission on February 27th, 2013, that title is " METHODS FOR MEMS STRUCTURE WITH DUAL-LEVEL STRUCTURAL LAYER AND ACOUSTIC PORT ", 214 priority, the open of this provisional application is incorporated to herein by reference as complete elaboration.
Background technology
Various embodiment of the present invention generally relates to MEMS device, and relates to particularly the method for the manufacture of it.
Be in the chip of two separation, to make MEMS substrate and CMOS substrate for the manufacture of the exemplary means of MEMS acoustical device, these two forms MEMS device.This cause MEMS device large and have that MEMS to CMOS interconnection causes do not expect high parasitic capacitance.
Desired is a kind of compact CMOS-MEMS Integrated Acoustic device and a kind of manufacturing process reliably of the MEMS structural thickness tolerance with strict control.
Summary of the invention
Briefly, a kind of method for the manufacture of MEMS device comprises that by the first sacrifice layer deposition and patterning the first sacrifice layer is partly removed to stay the first residual oxide to silicon substrate.In addition, the method comprises conductive structure is deposited upon on silicon substrate, and at least a portion of conductive structure layer and silicon substrate is carried out physical contact.In addition, on the top of conductive structure layer, form the second sacrifice layer.Carry out patterning and the etching of silicon substrate, thereby stop at the second sacrifice layer place.In addition, MEMS substrate is attached to CMOS wafer, CMOS wafer has formation metal level thereon.Between MEMS substrate and metal level, form and be electrically connected.
By the remainder with reference to description and accompanying drawing, can recognize characteristic to specific embodiment disclosed herein and the further understanding of advantage.
Brief description of the drawings
Figure 1A-1S shows the process of the manufacture MEMS device of the method according to this invention.
Fig. 2 A-2L shows according to the process of the manufacture MEMS device of other method of the present invention.
Fig. 3 A-3O shows according to the process of the manufacture MEMS device of other method more of the present invention.
Fig. 4 A-4I shows according to the process of the manufacture MEMS device of other method again of the present invention.
Fig. 5 A-5H shows according to the process of the manufacture MEMS device of other method of the present invention.
Fig. 6 A-6J shows according to the process of the manufacture MEMS device of other method of the present invention.
Fig. 7 A-7K shows according to the process of the manufacture MEMS device of other method of the present invention.
Detailed description of the invention
In described embodiment, microelectromechanical-systems (MEMS) refers to a class formation or device, and it is used technique as semiconductor to manufacture and represents the mechanical property such as mobile or deformability.MEMS often but not mutual with the signal of telecommunication all the time.MEMS device includes but not limited to actuator, gyroscope, accelerometer, magnetometer, pressure sensor, microphone and radio-frequency unit.The silicon wafer that comprises MEMS structure is called as MEMS wafer.
In described embodiment, MEMS device can refer to the semiconductor devices that is embodied as microelectromechanical-systems.MEMS structure can refer to any feature of the part that can be used as larger MEMS device.Through engineering approaches silicon-on-insulator (engineered silicon-on-insulator) (ESOI) wafer can refer to the SOI wafer below silicon device layer or substrate with cavity.Bearing wafer (handle wafer) is typically referred to as thicker substrate of generation, and it is used as in SOI wafer compared with the carrier of thin silicon device substrate.Carrier substrate (handle substrate) and bearing wafer can exchange.
In described embodiment, cavity can refer to opening or the recess in substrate wafer, and shell can refer to totally enclosed space.Column can be the vertical stratification for mechanical support in the cavity of MEMS device.Bearing (standoff) can be to provide the vertical stratification electrically contacting.
In described embodiment, back of the body cavity can refer to partially enclosed cavity, makes it equal environmental pressure via isostasy passage (PEC).In certain embodiments, back of the body cavity is also referred to as back of the body chamber.The back of the body cavity being formed in CMOS-MEMS device can be called integrated back of the body cavity.For carrying on the back cavity to the low frequency of environmental pressure or the acoustical passage of static pressure equilibrium also referred to as the isostasy passage in leakage path/path.
In described embodiment, the rigid structure that MEMS device moves when inherent stressed can be called plate.Backboard can be the perforated plate as electrode.
In described embodiment, perforation refers to the air-damped acoustics opening for reducing mobile plate.Acoustical ports can be the opening for sensing acoustic stress.Acoustics barrier can be the structure that prevents or postpone the specific part of acoustic stress arrival device.Hinge is to be provided to by anchor the structure that complying with of substrate adhered to.Can by the step-etching of column and on PEC creating section divide column the overlapping acoustics gap that creates extension.In face, protuberance block (bump stop) is the extension of plate, and it contacts with the moving range in the plane of confinement plate with device sealing part.Rotation protuberance block is the extension for restricting rotation scope of plate.
Referring now to Figure 1A-1S, show the process of the manufacture MEMS device of the method according to this invention.In Figure 1A, MEMS device 10 is shown as and comprises and bearing 13 is shown silicon wafer 12 on its top.Bearing 13 is partially etched in silicon wafer 12.In Figure 1B, carry out oxide deposition and be etched with the mask 14 that is formed for thin part film.This mask is made and is formed on by oxide on the top of the silicon wafer 12 between bearing 13.In Fig. 1 C, polysilicon 16 is deposited on the top of silicon wafer 12, bearing 13 and mask 14.In described embodiment, polycrystalline silicon is called as polysilicon.The thickness of polysilicon 16 defines in fact the thickness in the thin region of MEMS device 10.
In Fig. 1 D, silica 18 is depicted as and is deposited, and carries out the surface of chemically mechanical polishing (CMP) with smooth silica 18.As will be about Fig. 1 E and clearly, silica 18 helps to be attached to interim bearing wafer.
In Fig. 1 E, interim bearing wafer 20 is attached to silica 18.In illustrative methods of the present invention, silica molten adhere is for being attached to silica 18 by interim bearing wafer 20.In another embodiment, use interim polymer combination.In Fig. 1 F, the basal surface of silicon wafer 12 is polished with polishing to form the structure shown in Fig. 1 G.Therefore, at Fig. 1 G place, silicon wafer 12 than it in Fig. 1 F or grind before thinner.The thickness of the silicon wafer in Fig. 1 G defines in fact the thickness of the thick structure of MEMS device 10.As shown in Fig. 1 G, patterning photoresist 22 in the selection region of the basal surface of silicon wafer 12.This type of patterning protection silicon wafer 12 as desired in fact of photoresist is in order to avoid etched in next step.
In Fig. 1 H, on photoresist 22, carry out dry etching, as shown in the arrow in Fig. 1 H.In illustrative methods of the present invention, deep reactive ion etch (DRIE) is selected as for etching method, and with compared with silica, there is higher etch-rate for silicon and polysilicon.Come the selection region of etching silicon wafer 12 by resting on the polysilicon 16 at silica 18 places, form thus silicon wafer 12' and polysilicon 16'.After etching, silica does not exist therein in the region of photoresist and/or in the time that oxidated thing mask 14 is protected, is connected to polysilicon 16'.The MEMS substrate 24 that Fig. 1 H is illustrated in this etching step after completing.
Fig. 1 I shows bearing wafer 30, and silicon is partially etched in this bearing wafer 30 and is and then oxidized to limit cavity 33.Bearing wafer 30 is shown as and comprises silicon (or " cap ") layer 32 that forms silicon dioxide layer 34 thereon, forms cavity 33 in silicon dioxide layer 34.In Fig. 1 J, MEMS substrate 24 is illustrated and is attached to bearing wafer 30.In illustrative methods, molten adhere is for this process.
In Fig. 1 K, combine to remove interim bearing wafer 20 by mechanical lapping, etching or its.Interim in conjunction with adhering in the alternate embodiment of interim bearing wafer 20 with polymer therein, combine to remove interim bearing wafer 20 with polymer solvent, heating or its.Before being removed, the attenuation process that interim bearing wafer 20 supports is above protected silicon wafer 12' simultaneously during processing.
In Fig. 1 L, by photoetching process, partially-etched silica 18 is to expose polysilicon 16' to the open air.Together with the directly part under it of the polysilicon 16'' exposing to the open air and silicon wafer 12', form bearing.Note, silica 18' is by complete etching, be wherein formed on the top of film 14 and partly the part on the top of polysilicon 16' after the etching step of Fig. 1 L, remain.
In Fig. 1 M, conductive layer 36 is illustrated on the top that is deposited on the polysilicon 16' exposing to the open air.In the exemplary embodiment, conductive layer 36 is made up of germanium, but can adopt other suitable materials, such as, but not limited to gold, aluminium and tin.Carry out vapour phase or liquid phase hydrofluoric acid (HF) etching of silica 18', and the MEMS substrate 60 of release graphics 1N.
Fig. 1 O shows the CMOS wafer 40 that comprises CMOS substrate 42, on CMOS substrate 42, alternatively on CMOS oxide 44 etched pattern to form protuberance block 46.In other embodiments, can use any semiconductor wafer.Metal level 48 is dispersed in CMOS oxide 44 with CMOS wafer electric the most at last and is connected to MEMS substrate.Protuberance block 46 minimizes contacting between MEMS film and CMOS wafer, in minimization neutralization operation static friction the two.
In Fig. 1 P, port 52 is etched in CMOS substrate 42 by CMOS oxide 44 to form respectively CMOS substrate 42' and CMOS oxide 44'.Create alternatively the bearing wafer 32' of port 58 with formation at the CMOS wafer 54 of the bearing wafer 32 further etch figures(s) 1P in place.Each in port 52 and 58 is independent cavity or acoustical ports being to use in the embodiment of microphone at MEMS device 10.Alternately, not etching or establishment port 58, on the contrary, only form port 52, as shown in Fig. 1 R.The embodiment of Fig. 1 R is integrated into back of the body cavity in device and is therefore compacter, and compared with the device of Fig. 1 Q the less device of generation.But the acoustical behavior of the embodiment of 1R typically reduces with respect to the acoustical behavior of the embodiment of Fig. 1 Q, because the back of the body cavity of the embodiment of the former back of the body cavity ratio Fig. 1 Q is less.In the embodiment of Fig. 1 Q, device with respect to the embodiment of Fig. 1 R is larger but performance is better because the encapsulation of device is as back of the body cavity in Fig. 1 R.
In Fig. 1 S, MEMS device 64 is shown as use and for example carries out anti-stiction coating such as the hydrophobicity low surface energy coat of the long-chain fluorocarbon of perfluor decyltrichlorosilane (FDTS).This coating is typically deposited as self assembled monolayer (SAM) or uses ald (ALD) to deposit.A kind of this type of ALD layer is aluminium oxide Al 2O3.Except other benefits, this coating is used for falling low-surface-energy and repels water, prevents that thus the surface of CMOS wafer and MEMS film is inter-adhesive.This coating can also prevent corrosion.
Fig. 2 A-2L shows according to the process of the manufacture MEMS device of other method of the present invention.This process is similar with the process of Figure 1A-1S of the step by Fig. 1 H.In formation bearing wafer, in Fig. 2 a, in the bearing wafer 200 of Fig. 2 A, etching does not have cavity.Bearing wafer 200 is shown as and comprises silicon wafer 202, and it is not by partially-etched and have on the contrary an oxide 204 of patterning on the top of silicon wafer 202.In other words, oxide 204 is deposited on silicon wafer 202 and optionally and removes from silicon wafer 202.
In Fig. 2 B, MEMS substrate 206 is illustrated in oxide skin(coating) 204 places and bearing wafer 200 combinations.Molten adhere is the exemplary combination method in Fig. 2 B.Similar with Fig. 1 J and 1K, in Fig. 2 C, remove temporary wafer carrying 20.In Fig. 2 D, carry out patterning.That is, carry out blanket type oxide etching (blanket oxide etching) to form oxide 210', it is as the supporting construction of MEMS device.
In Fig. 2 E, conductive layer 214 is formed on the top of polysilicon 16' that does not wherein have oxide 210'.Except other suitable materials, the example of this conductive layer comprises germanium, tin, gold and aluminium.Then, as shown in Fig. 2 F, oxide etching is performed by polysilicon and silicon wafer, and at oxide, place stops.In illustrative methods, reactive ion etching (RIE) is as etch process.
Fig. 2 G shows CMOS wafer 54.In Fig. 2 H, MEMS substrate 260 uses suitable combination technology to be attached to CMOS wafer 54.The same with all methods of imagination as disclosed herein, exemplary combination technology comprises molten adhere or congruent melting combination.The structure of Fig. 2 H is polished, and in Fig. 2 I, bearing wafer is patterned and etching, and at oxide, 204 places stop forming port 212.In Fig. 2 J, carry out to be etched with removing silica 14 and form MEMS device 270.Exemplary etch process comprises RIE or HF.
In Fig. 2 K, in the time of the two sides (top and bottom) with adhesive tape protection MEMS device, carry out label cutting (tab dicing).Similar with the MEMS device of Fig. 1 S, in Fig. 2 L, apply coating to MEMS device 272.
Fig. 3 A-3O shows according to the process of the manufacture MEMS device of other method more of the present invention.In this process, do not need to adopt temporary wafer carrying, and CMOS wafer is directly attached to MEMS substrate.
Fig. 3 A shows the silicon wafer 300 with silicon wafer 312, and silicon wafer 312 has etched bearing 311 therein.In Fig. 3 B, oxide deposits and as shown like that by partly etching.In Fig. 3 C, polysilicon 316 is deposited on bearing 311 and oxide 314 and silicon wafer 312.Then,, in Fig. 3 D, conductive layer 336 is formed on the top of the polysilicon 316 in the region on bearing 311.This is and the deviation of the process above illustrating and describe, because do not form interim bearing wafer.In Fig. 3 E, patterned polysilicon 316 and leaving space region 302.Correspondingly form MEMS substrate 306.
Fig. 3 C shows the similar CMOS wafer 340 of CMOS wafer with Fig. 1 O, and it has the protuberance block 346 being depicted as from CMOS dielectric 344 projections.In certain embodiments, the protuberance block of various embodiment of the present invention is made up of silicon nitride, silica or the combination of the two.Such as other CMOS compatible materials of titanium nitride and aluminium also can be independently with or use together with silicon nitride and silica.CMOS wafer 340 is also shown as to be had CMOS substrate 342 and is deposited on the metal level 348 in CMOS dielectric 344.
In Fig. 3 G, CMOS wafer 340 is illustrated and is attached to MEMS substrate 306, and MEMS substrate 306 is polished and polishing.In illustrative methods, adopt congruent melting aluminium-germanium junction to close.Correspondingly, MEMS substrate is attached to CMOS wafer, and CMOS wafer serves as supporting layer., CMOS wafer is back support layer.
In Fig. 3 H, add photoresist layer 352 by photoetching process, and at Fig. 3 I place, carry out etching, and etching is by silicon wafer 312 and stop at oxide 314 places, as previously discussed about other figure.Etched illustrative methods is DRIE.In Fig. 3 J, at the direction etching photoresist 352 shown in arrow and polysilicon 316 to form MEMS substrate 317.In illustrative methods, adopt RIE as etching method.From this step in the time applying SAM coating, can form MEMS device with two kinds of selections.Selection is to form the open cavity or the port that are suitable for microphone applications, and another kind of selection is to set up enclosed cavity MEMS device.Fig. 3 K and 3L show open cavity and select, and Fig. 3 M-3O shows enclosed cavity selection.
In Fig. 3 K, grind the port 388 of CMOS wafer etching such as acoustical ports, and in Fig. 3 L, apply SAM coating.Alternately, before the integrating step of Fig. 3 G, perform step 3K.
In Fig. 3 M, cap layer 354 is shown, it is in this article also referred to as bearing wafer.In Fig. 3 N, bearing wafer 354 is attached to MEMS substrate 317.In illustrative methods, titanium is deposited on bearing wafer 354 to form titanium silicon in conjunction with 334.
In Fig. 3 O, grind CMOS wafer, etched port 377, and carry out label cutting and SAM coating, as above discussed about previous figure.
Fig. 4 A-4I shows according to the process of the manufacture MEMS device of other method again of the present invention.In Fig. 4 A, bearing wafer 400 is shown as the silicon wafer 402 that is included in cvd silicon oxide 404 on its top, etching cavity 406 partly in oxide 404.Fig. 4 B shows the device wafer (or MEMS substrate) 401 with silicon wafer 408, etching cavity 410 partly in silicon wafer 408.In Fig. 4 C, silicon wafer 400 aligns with device wafer 401 and combination, and cavity 406 and 410 is flushed.In illustrative methods, adopt molten adhere or congruent melting combination.
In Fig. 4 D, thereby carry out attenuation so that silicon wafer 408 attenuation form silicon wafer 408' by grinding and polished wafer 408.In Fig. 4 E, bearing 412 is etched in silicon wafer 408'.Then,, as shown in Fig. 4 F, be deposited on bearing 412 tops, be patterned and etching such as, but not limited to the conductive layer 414 of germanium.In Fig. 4 G, carry out patterning MEMS structure to form MEMS structure 408'' and the MEMS substrate 452 of patterning by the structure shown in etch figures(s) 4G.Can adopt exemplary etching technique discussed above.
In Fig. 4 H, MEMS substrate 452 is attached to CMOS wafer 450, as discussed about previous figure.In an embodiment, CMOS wafer 450 is similar to CMOS wafer 340.In Fig. 4 L, for microphone applications, port 454 etchings are passed through to CMOS wafer 450.
Fig. 5 A-5H shows according to the process of the manufacture MEMS device of other method of the present invention.In Fig. 5 A, silicon-on-insulator (SOI) wafer 500 is shown as and comprises monocrystalline silicon 506, silica 504 and silicon substrate 502.Silicon substrate 502 and silica 504 are in fact bearing wafers.In Fig. 5 B, cavity 508 is etched in monocrystalline silicon 506 to form monocrystalline silicon 506'.Then, in Fig. 5 C, wafer 500 is attached to the MEMS substrate that comprises silica 510 and silicon substrate 512, and silicon substrate 512 has cavity 509.According to illustrative methods of the present invention, adopt molten adhere.
Then,, in Fig. 5 D, remove bearing wafer with grinding, etching or any combination of separating combination, thereby leave monocrystalline silicon 506'.In Fig. 5 E, it is upper that bearing 514 edge in office is formed on monocrystalline silicon 506', and as shown in Fig. 5 F, be deposited on bearing 514 such as the conductive layer 516 of germanium.In Fig. 5 G, the CMOS wafer 518 that is similar to the CMOS wafer 40 of Fig. 1 O is attached to the structure 500F of Fig. 5 F, thereby produces structure 500G.Port 520 is illustrated and is etched in CMOS wafer 518 for acoustic applications.The advantage of the method for Fig. 5 A to 5H is that monocrystalline silicon 506 has the thickness of good restriction, and wherein varied in thickness is low and is controlled well.
Fig. 6 A-6J shows according to the process of the manufacture MEMS device of other method of the present invention.Except not creating cavity in the monocrystalline silicon 602 of SOI wafer 600, the process of the process of Fig. 6 A and 6B and Fig. 5 A-5C is similar.With the same in the method for Fig. 5 A-5H, the thickness of monocrystalline silicon 602 is advantageously well limited.As shown in Fig. 6 B, bearing wafer 600 is combined with the MEMS substrate that comprises silica 610 and silicon substrate 612, is formed with cavity XXX in silicon substrate 612.In Fig. 6 C, silicon substrate 606 is shown as and is removed, and in Fig. 6 D, carrys out etching oxidation silicon 604 by photoetching process, thereby creates silica 614.In Fig. 6 E, epitaxial silicon (epi-silicon) or polysilicon 616 are illustrated on the top that is deposited on oxide 614 and monocrystalline silicon 602.In Fig. 6 F, carry out CMP, at oxide, 614 places stop forming polysilicon 616'.In Fig. 6 G, etching oxide 614.In Fig. 6 H, be illustrated on the top that is formed on polysilicon 616' such as the conductive layer 618 of germanium.In Fig. 6 I, CMOS wafer 620 is illustrated with the structure 600H shown in Fig. 6 H and is combined, and in Fig. 6 J, port 622 is illustrated and is formed in CMOS wafer 620 and by CMOS wafer 620.
Fig. 7 A-7K shows according to the process of the manufacture MEMS device of other method of the present invention.Fig. 7 A shows the MEMS substrate 700 that comprises the soi structure with thin buffer oxide.MEMS substrate 700 is shown as and is included in the monocrystalline silicon 702 that forms silica 704 on its top, forms the second monocrystalline silicon 706 on the top of silica 704, forms thin oxide layer 708 on the top of the second monocrystalline silicon 706.Oxide skin(coating) 708 is as thin buffer oxide.In an embodiment of the present invention, layer 708 is approximately 100 nanometers (nm).
In Fig. 7 B, oxide 708 is patterned and is etched with formation oxide 708'.In Fig. 7 C, polysilicon layer 705 is deposited on oxide skin(coating) 708'.Conductive layer 710 is formed on the top of polysilicon 705.In an embodiment of the present invention, conductive layer 710 is made by germanium or about the indicated other materials of the embodiment of Figure 1A-1S.
In Fig. 7 D, bearing 712 is patterned, and structure etched by silica 704 to form the second monocrystalline silicon 706' of patterning and the conductive layer 710' of patterning.In Fig. 7 E, operating part oxide etching is with etching oxide 708'.Correspondingly, form MEMS substrate 714.In Fig. 7 F, be attached to MEMS substrate 714 with the similar CMOS wafer 716 of CMOS wafer 340.In illustrative methods, carry out congruent melting combination.
In 7G, carry out grinding and polishing to make monocrystalline silicon 702 thinner to form monocrystalline silicon 702'.In Fig. 7 H, etching monocrystalline silicon 702' is to form the isostasy passage and the protuberance block 718 that extend.In Fig. 7 I, silica 704 by partially-etched with form through etched silica 704'.In illustrative methods, carry out operating part etching by vapour phase hydrofluoric acid etch.Alternatively, the step of Fig. 7 I can be carried out after etched port.In Fig. 7 J, be similar to 354 bearing wafer 720 and be attached to the structure of Fig. 7 I or 7H, depend on the circumstances.Provided two kinds of selections, a kind of selection is to be attached to the bearing wafer with cavity, and another kind of selection is to be attached to non-patterned interim carrying to use together with the back of the body cavity of outside.In Fig. 7 K, carry out grinding and the polishing of CMOS substrate 716.In addition, etched port 722, and in the situation of the back of the body cavity extending, remove temporary wafer carrying.
The various embodiment that illustrate herein and describe and the application of method include but not limited to microphone, pressure sensor, resonator, switch and other applicable devices.
Although this description is described about its specific embodiment, these specific embodiments are only illustrative and nonrestrictive.
Use as run through claims in the neutralization of this paper description, " one ", " one " and " described " comprise plural object of reference, unless context clearly refers else.In addition, use as run through claims in this paper description neutralization, and " ... in " implication comprise " ... in " and " ... on ", unless context clearly refers else.
Therefore, although described specific embodiment herein, but intention has amendment, various change and the alternative room for maneuver in foregoing disclosure, and will recognize, in some instances, to in the case of the correspondence that there is no other features is used, adopt some features of specific embodiment, and do not depart from set forth scope and spirit.Therefore, can make many amendments so that concrete situation or material are adapted to essential scope and spirit.
Claims (54)
1. for the manufacture of a method for MEMS device, comprising:
By the first sacrifice layer deposition and patterning, to silicon substrate, the first sacrifice layer is partly removed to stay the first residual oxide;
Conductive structure is deposited upon on silicon substrate, and at least a portion of conductive structure layer and silicon substrate is carried out physical contact;
On the top of conductive structure layer, form the second sacrifice layer;
Patterning and etched silicon substrate also stop at the second sacrifice layer place;
MEMS substrate is attached to CMOS wafer, and CMOS wafer has formation metal level thereon; And
Between MEMS substrate and metal level, form and be electrically connected.
2. the method for the manufacture of MEMS device as claimed in claim 1, also comprises and forming by the first port of CMOS wafer.
3. the method for the manufacture of MEMS device as claimed in claim 1, being also included in and forming the second sacrifice layer is the thickness of expecting afterwards by silicon substrate attenuation.
4. the method for the manufacture of MEMS device as claimed in claim 3, wherein comprises silicon substrate attenuation MEMS substrate is attached to interim bearing wafer.
5. the method for the manufacture of MEMS device as claimed in claim 4, is wherein attached to interim bearing wafer by MEMS substrate and comprises the step that makes the second sacrifice layer complanation.
6. the method for the manufacture of MEMS device as claimed in claim 3, wherein attenuation step comprises the combination of grinding or polishing or etching step.
7. the method for the manufacture of MEMS device as claimed in claim 1, also comprises:
Patterning the second sacrifice layer is to allow to approach conductive structure layer; And
In connection with being deposited upon on conductive structure layer.
8. the method for the manufacture of MEMS device as claimed in claim 7, wherein the step of patterning the second sacrifice layer is carried out with dry etching method.
9. the method for the manufacture of MEMS device as claimed in claim 7, wherein the step of patterning the second sacrifice layer is carried out by wet etch process.
10. the method for the manufacture of MEMS device as claimed in claim 1, also comprises by carry out complanation the second sacrifice layer with chemically mechanical polishing.
11. methods for the manufacture of MEMS device as claimed in claim 1, also comprise silicon substrate and silicon bearing wafer are carried out to another combination to form MEMS substrate.
12. methods for the manufacture of MEMS device as claimed in claim 11, are also included in silicon bearing wafer and form cavity.
13. methods for the manufacture of MEMS device as claimed in claim 11, also comprise and forming by the second port of silicon bearing wafer.
14. methods for the manufacture of MEMS device as claimed in claim 1, wherein integrating step is included between CMOS wafer and MEMS substrate and uses molten adhere, and electrical connection is by forming by the conductive path of silicon bearing wafer.
15. methods for the manufacture of MEMS device as claimed in claim 1, wherein patterning and etched silicon substrate are carried out after MEMS substrate is attached to CMOS wafer.
16. methods for the manufacture of MEMS device as claimed in claim 1, wherein patterning and etched silicon substrate were carried out before MEMS substrate is attached to CMOS wafer.
17. methods for the manufacture of MEMS device as claimed in claim 1, wherein integrating step comprises silica molten adhere.
18. methods for the manufacture of MEMS device as claimed in claim 1, wherein integrating step is included in and between CMOS wafer and MEMS substrate, forms congruent melting and be combined, and electrical connection is contacted to form by congruent melting.
19. methods for the manufacture of MEMS device as claimed in claim 1, wherein integrating step comprises polymer combination.
20. methods for the manufacture of MEMS device as claimed in claim 1, wherein integrating step comprises anode combination.
21. methods for the manufacture of MEMS device as claimed in claim 1, wherein the patterning of silicon substrate and etched etching step comprise deep reactive ion etch (DRIE), standard reaction ion(ic) etching (RIE), wet chemical etch or ion milling.
22. methods for the manufacture of MEMS device as claimed in claim 1, are wherein ground with etched combination or etching and are removed silicon bearing wafer by step.
23. methods for the manufacture of MEMS device as claimed in claim 1, wherein the combination of MEMS substrate and CMOS wafer comprises: solder bond, molten adhere, glass dust combination, hot compression combination or anode combination.
24. methods for the manufacture of MEMS device as claimed in claim 1, wherein integrating step and formation electrical connection comprise that use has the congruent melting solder bond of aluminium-germanium system.
25. methods for the manufacture of MEMS device as claimed in claim 1, also comprise and remove the first sacrifice layer and the second sacrifice layer.
26. methods for the manufacture of MEMS device as claimed in claim 1, wherein the first and second each that remove in step comprise the hydrofluoric acid or the plasma etching that use isotropic oxide etching agent, liquid or gas form.
27. methods for the manufacture of MEMS device as claimed in claim 1, wherein before integrating step, CMOS wafer is patterned as has protuberance to reduce and the contacting and static friction of MEMS device in its surface.
28. methods for the manufacture of MEMS device as claimed in claim 1, also comprise that patterning and partially-etched silicon substrate are to limit bearing.
29. methods for the manufacture of MEMS device as claimed in claim 28, wherein bearing formed before deposition the first sacrifice layer.
30. methods for the manufacture of MEMS device as claimed in claim 28, wherein the second sacrifice layer has the thickness that is greater than height of support.
31. methods for the manufacture of MEMS device as claimed in claim 1, also comprise that deposition and patterning the second conductive layer are to form bearing.
32. methods for the manufacture of MEMS device as claimed in claim 1, wherein conductive structure layer is polycrystal silicon layer.
33. methods for the manufacture of MEMS device as claimed in claim 1, wherein the first sacrifice layer is made up of silica.
34. methods for the manufacture of MEMS device as claimed in claim 1, wherein the second sacrifice layer is made up of silica.
35. methods for the manufacture of MEMS device as claimed in claim 1, wherein integrating step comprises MEMS substrate and CMOS wafer alignment.
36. 1 kinds of MEMS devices, comprising:
Polycrystalline silicon (polysilicon) layer, is formed on the silicon substrate with the region forming by removing of oxide, and polysilicon layer carries out physical contact with silicon substrate in described region, and silicon substrate is desirably thin;
MEMS substrate, is formed on the top of polysilicon layer;
CMOS wafer, is combined with MEMS substrate, and CMOS wafer has formation metal level thereon, the metal level that the combination of MEMS substrate and CMOS wafer makes between the polysilicon on MEMS substrate to form electrical connection and allows to expose to the open air CMOS wafer; And
Germanium layer, is formed on the top of polysilicon,
Wherein CMOS wafer aligns with MEMS substrate.
37. MEMS devices as claimed in claim 36, wherein MEMS device is microphone, pressure sensor, resonator or switch.
38. 1 kinds of methods for the manufacture of MEMS device, comprising:
Formation has the first silicon wafer of the first cavity;
Formation has the second silicon wafer of the second cavity;
In conjunction with the first and second silicon wafers, make the first and second cavity face to each other;
Between the first and second wafers, form oxide skin(coating);
Carry out the first combination of the first and second silicon wafers;
Be the thickness of expecting by the second silicon wafer attenuation, the region wherein with the second cavity has the part of attenuation;
The part of the silicon by the second wafer removes to form bearing; And
Proceed to the second combination of the first silicon layer, form thus electrical connection.
39. methods for the manufacture of MEMS device as claimed in claim 38, wherein the second wafer comprises bearing bed, device layer and oxide skin(coating), and wherein oxide skin(coating) is arranged between bearing bed and device layer, and further wherein the second cavity is formed in device layer.
40. methods for the manufacture of MEMS device as claimed in claim 39, wherein the attenuation of the second wafer comprises and removes bearing bed.
41. methods for the manufacture of MEMS device as claimed in claim 38, wherein first in conjunction with comprising molten adhere.
42. methods for the manufacture of MEMS device as claimed in claim 38, also comprise patterning and etching the second silicon layer, and wherein the etching in the step of patterning and etching the second silicon layer is by the second silicon wafer.
43. methods for the manufacture of MEMS device as claimed in claim 38, are also included in depositing conducting layer on bearing.
44. methods for the manufacture of MEMS device as claimed in claim 38, are also included in the first silicon wafer and form port.
45. methods for the manufacture of MEMS device as claimed in claim 38, wherein the part of silicon removes by etching and carries out.
46. 1 kinds of methods for the manufacture of MEMS device, comprising:
Formation has the first silicon wafer of the first cavity;
Form the second silicon wafer, the second silicon wafer comprises bearing wafer, device wafer and is arranged on the oxide between the second silicon wafer and bearing wafer;
The first silicon wafer is attached to the second silicon wafer;
Remove the bearing wafer of the second silicon wafer, thereby leave oxide skin(coating) on the second silicon wafer;
Patterned oxide layer;
Deposit spathic silicon layer on the oxide skin(coating) of patterning;
Complanation polysilicon layer also stops this complanation at oxide skin(coating) place;
Remove oxide skin(coating);
Deposition and patterned conductive layer; And
In conjunction with the second silicon wafer be electrically connected.
47. methods for the manufacture of MEMS device as claimed in claim 46, are also included in the second silicon wafer and open port.
48. methods for the manufacture of MEMS device as claimed in claim 46, are also included in the first silicon wafer and open port.
49. methods for the manufacture of MEMS device as claimed in claim 46, wherein the second silicon layer comprises dielectric layer and in dielectric layer, forms cavity.
50. methods for the manufacture of MEMS device as claimed in claim 46, wherein the second silicon wafer is cmos layer.
51. 1 kinds of methods for the manufacture of MEMS device, comprising:
Form silicon-on-insulator (SOI) wafer, SOI wafer comprises bearing bed, device layer and the oxide forming between bearing bed and device layer;
The oxide skin(coating) of deposited oxide layer patterned deposition on SOI wafer;
Deposit spathic silicon on the oxide skin(coating) of patterning;
Depositing conducting layer on polysilicon;
Patterning and etching polysilicon and conductive layer;
Further etch device layer;
Remove the oxide skin(coating) of patterning, form thus MEMS substrate;
MEMS substrate is attached to CMOS wafer, and CMOS wafer has at least one metal level;
Between MEMS substrate and described at least one metal level, form and be electrically connected;
By bearing bed attenuation;
Patterning bearing bed;
Remove the oxide skin(coating) being deposited on SOI wafer.
52. methods for the manufacture of MEMS device as claimed in claim 51, also comprise MEMS substrate are attached to the silicon cap wafer with cavity.
53. methods for the manufacture of MEMS device as claimed in claim 52, are also included in the port of opening in silicon cap wafer.
54. methods for the manufacture of MEMS device as claimed in claim 51, are also included in CMOS wafer and open port.
Applications Claiming Priority (4)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US201361770214P | 2013-02-27 | 2013-02-27 | |
| US61/770214 | 2013-02-27 | ||
| US14/084,569 US9227842B2 (en) | 2013-02-27 | 2013-11-19 | Method for MEMS structure with dual-level structural layer and acoustic port |
| US14/084569 | 2013-11-19 |
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| CN104003348A true CN104003348A (en) | 2014-08-27 |
| CN104003348B CN104003348B (en) | 2018-02-02 |
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| CN201410068355.4A Active CN104003348B (en) | 2013-02-27 | 2014-02-27 | For the method with dual-layer face structure sheaf and the MEMS structure of acoustical ports |
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Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105990123A (en) * | 2015-02-27 | 2016-10-05 | 中芯国际集成电路制造(上海)有限公司 | Wafer thinning method |
| CN109000830A (en) * | 2018-06-26 | 2018-12-14 | 常州元晶电子科技有限公司 | A kind of double Wheatstone bridge temperature-compensating differential pressure pressure sensors and preparation method thereof |
| TWI675444B (en) * | 2017-09-27 | 2019-10-21 | 台灣積體電路製造股份有限公司 | Mems device and method for packaging mems |
| CN111453694A (en) * | 2020-03-06 | 2020-07-28 | 深迪半导体(上海)有限公司 | MEMS device and method of manufacturing the same |
| CN112047295A (en) * | 2019-06-07 | 2020-12-08 | 英飞凌科技股份有限公司 | Producing MEMS devices with glass covers and MEMS devices |
| WO2021134688A1 (en) * | 2019-12-31 | 2021-07-08 | 瑞声声学科技(深圳)有限公司 | Method for producing mems drive |
| US11279615B2 (en) | 2017-09-27 | 2022-03-22 | Taiwan Semiconductor Manufacturing Company, Ltd. | Method for manufacturing a MEMS device by first hybrid bonding a CMOS wafer to a MEMS wafer |
Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1949477A (en) * | 2006-11-10 | 2007-04-18 | 北京大学 | Body silicon MEMS and CMOS circuit integrating method capable of removing residual silicon |
| CN101427593A (en) * | 2006-03-30 | 2009-05-06 | 普尔斯门斯公司 | Single die MEMS acoustic transducer and manufacturing method |
| US20100052082A1 (en) * | 2008-09-03 | 2010-03-04 | Solid State System Co., Ltd. | Micro-electro-mechanical systems (mems) package and method for forming the mems package |
| CN101927977A (en) * | 2009-06-24 | 2010-12-29 | 鑫创科技股份有限公司 | Fabrication method of cmos microelectromechanical system (mems) device |
| US20120001276A1 (en) * | 2010-06-30 | 2012-01-05 | Industrial Technology Research Institute | Apparatus integrating microelectromechanical system device with circuit chip and methods for fabricating the same |
| US20120061776A1 (en) * | 2010-09-10 | 2012-03-15 | Taiwan Semiconductor Manufacturing Company, Ltd. | Wafer level packaging |
| US20130001710A1 (en) * | 2011-06-29 | 2013-01-03 | Invensense, Inc. | Process for a sealed mems device with a portion exposed to the environment |
-
2014
- 2014-02-27 CN CN201410068355.4A patent/CN104003348B/en active Active
Patent Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101427593A (en) * | 2006-03-30 | 2009-05-06 | 普尔斯门斯公司 | Single die MEMS acoustic transducer and manufacturing method |
| CN1949477A (en) * | 2006-11-10 | 2007-04-18 | 北京大学 | Body silicon MEMS and CMOS circuit integrating method capable of removing residual silicon |
| US20100052082A1 (en) * | 2008-09-03 | 2010-03-04 | Solid State System Co., Ltd. | Micro-electro-mechanical systems (mems) package and method for forming the mems package |
| CN101927977A (en) * | 2009-06-24 | 2010-12-29 | 鑫创科技股份有限公司 | Fabrication method of cmos microelectromechanical system (mems) device |
| US20120001276A1 (en) * | 2010-06-30 | 2012-01-05 | Industrial Technology Research Institute | Apparatus integrating microelectromechanical system device with circuit chip and methods for fabricating the same |
| US20120061776A1 (en) * | 2010-09-10 | 2012-03-15 | Taiwan Semiconductor Manufacturing Company, Ltd. | Wafer level packaging |
| US20130001710A1 (en) * | 2011-06-29 | 2013-01-03 | Invensense, Inc. | Process for a sealed mems device with a portion exposed to the environment |
Cited By (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105990123A (en) * | 2015-02-27 | 2016-10-05 | 中芯国际集成电路制造(上海)有限公司 | Wafer thinning method |
| CN105990123B (en) * | 2015-02-27 | 2019-05-28 | 中芯国际集成电路制造(上海)有限公司 | Wafer thining method |
| TWI675444B (en) * | 2017-09-27 | 2019-10-21 | 台灣積體電路製造股份有限公司 | Mems device and method for packaging mems |
| US11279615B2 (en) | 2017-09-27 | 2022-03-22 | Taiwan Semiconductor Manufacturing Company, Ltd. | Method for manufacturing a MEMS device by first hybrid bonding a CMOS wafer to a MEMS wafer |
| US11932534B2 (en) | 2017-09-27 | 2024-03-19 | Taiwan Semiconductor Manufacturing Company, Ltd. | MEMS device having a metallization structure embedded in a dielectric structure with laterally offset sidewalls of a first portion and a second portion |
| CN109000830A (en) * | 2018-06-26 | 2018-12-14 | 常州元晶电子科技有限公司 | A kind of double Wheatstone bridge temperature-compensating differential pressure pressure sensors and preparation method thereof |
| CN112047295A (en) * | 2019-06-07 | 2020-12-08 | 英飞凌科技股份有限公司 | Producing MEMS devices with glass covers and MEMS devices |
| WO2021134688A1 (en) * | 2019-12-31 | 2021-07-08 | 瑞声声学科技(深圳)有限公司 | Method for producing mems drive |
| CN111453694A (en) * | 2020-03-06 | 2020-07-28 | 深迪半导体(上海)有限公司 | MEMS device and method of manufacturing the same |
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|---|---|
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