CN103995381A - Pixel structure, liquid crystal display panel and technique thereof - Google Patents
Pixel structure, liquid crystal display panel and technique thereof Download PDFInfo
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- CN103995381A CN103995381A CN201410155566.1A CN201410155566A CN103995381A CN 103995381 A CN103995381 A CN 103995381A CN 201410155566 A CN201410155566 A CN 201410155566A CN 103995381 A CN103995381 A CN 103995381A
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Abstract
The invention relates to a pixel structure, a liquid crystal display panel and a technique of the liquid crystal display panel. The pixel structure comprises a substrate, a thin film transistor, at least one protrusion, a passive film, a common electrode, an upper insulation film, a via hole and a pixel electrode. The thin film transistor is arranged on the upper portion of the substrate and comprises a grid electrode, a grid electrode insulation layer, an active layer, a source electrode and a drain electrode. The protrusion is made of the same material of any layer of the thin film transistor and is arranged on the lower portion of the drain electrode. The passive layer covers the upper portion of the thin film transistor. The common electrode is arranged on the upper portion of the passive layer. The upper insulation film is arranged on the upper portion of the common electrode. The via hole penetrates through the upper insulation film and the passive film. The pixel electrode is arranged on the upper portion of the upper insulation film and is electrically connected with the drain electrode of the thin film transistor through the via hole. The pixel structure can reduce the size of the via hole enabling the pixel electrode and the drain electrode of the TFT to be connected, and thus the phenomena of light leakage and the like caused by abnormal deflection of liquid crystals on the upper portion of the via hole can be avoided effectively. Meanwhile, the TFT and the protrusion can be simultaneously manufactured through the further technique, additional technique steps are not needed, and cost is saved.
Description
Technical field
The present invention relates to demonstration field, relate in particular to a kind of dot structure, the liquid crystal panel that comprises this dot structure, and the process of manufacturing this dot structure.
Background technology
Current dot structure as shown in Figure 1, on substrate 100, is provided with grid 101, is provided with gate insulator 102 above grid, and active layer 103 is arranged at gate insulator 102 tops, and is positioned at grid 101 tops.Source electrode 104 and drain electrode 105 are set to insulation above active layer 103, and source electrode 104, drain electrode 105 tops are formed with inorganic passivating film 106 and the organic passivation film 107 that covers whole substrate successively.On organic passivation film 107, form public electrode 108, public electrode 108 tops form upper portion insulating film 109, form pixel electrode 110 on upper portion insulating film 109.Drain electrode 105 has drain electrode extension 105a, and drain electrode extension 105a is connected with pixel electrode 110 by running through the via hole 111 of upper portion insulating film 109, organic passivation film 107 and inorganic passivating film 107.
In this structure, because drain electrode is connected with via hole with pixel electrode, the normally deflection of via hole top liquid crystal, orientation confusion, cause light leak.As countermeasure, generally all above via hole, adopt at present black matrix (BM) to block, this can cause the reduction of light transmission rate.Along with the increase of liquid crystal display pixel (PPI) in recent years, via size is more and more obvious on the impact of transmitance.
Summary of the invention
The present invention aims to provide a kind of dot structure, can reduce the via size that in dot structure, drain electrode is connected with pixel electrode.
A dot structure, comprises: substrate; Thin film transistor (TFT), is arranged at described substrate top, and described thin film transistor (TFT) comprises grid, gate insulator, active layer, source electrode, drain electrode; At least one projection, described projection adopts arbitrary layer of same material of thin film transistor (TFT) to make, and described projection is positioned at described drain electrode below; Passivating film, is covered in described thin film transistor (TFT) top; Public electrode, is arranged at described passivating film top; Upper portion insulating film, is arranged at described public electrode top; Via hole, runs through described upper portion insulating film and described passivating film; Pixel electrode, is arranged at described upper portion insulating film top, and described pixel electrode is electrically connected to the drain electrode of described thin film transistor (TFT) by described via hole.
A liquid crystal panel, comprises above-mentioned dot structure.
A process of manufacturing dot structure, comprises: a substrate is provided; Above substrate, form grid, the side at described grid is formed with bulge-structure simultaneously; Above described grid, form gate insulator; The position of the corresponding grid in gate insulator top forms active layer; At active layer upper surface, insulate source electrode and drain electrode are set, described drain electrode covers described projection; Above source electrode and drain electrode layer, form passivating film; Above passivating film, form public electrode; Above described public electrode, form upper portion insulating film; Formation runs through the via hole of described upper portion insulating film and described passivating film; Above described upper portion insulating film, form pixel electrode, described pixel electrode is electrically connected to drain electrode by described via hole.
A process of manufacturing dot structure, comprises: a substrate is provided; Above substrate, form grid; Above described grid, form gate insulator, in the position of corresponding grid one side, form bulge-structure simultaneously; Above gate insulator, the position of corresponding grid forms active layer; , at active layer upper surface, to insulate source electrode and drain electrode are set, described drain electrode covers described projection; Above source electrode and drain electrode layer, form passivating film; Above passivating film, form public electrode; Above described public electrode, form upper portion insulating film; Formation runs through the via hole of described upper portion insulating film and described passivating film; Above described upper portion insulating film, form pixel electrode, described pixel electrode is electrically connected to drain electrode by described via hole.
A process of manufacturing dot structure, comprises: a substrate is provided; Above substrate, form grid; Above described grid, form gate insulator; Above described gate insulator, the position of corresponding grid forms active layer, and the side at described active layer forms bulge-structure simultaneously; At described active layer upper surface, source electrode and drain electrode are set discretely, described drain electrode covers described projection; Above source electrode and drain electrode layer, form passivating film; Above passivating film, form public electrode; Above described public electrode, form upper portion insulating film; Formation runs through the via hole of described upper portion insulating film and described passivating film; Above described upper portion insulating film, form pixel electrode, described pixel electrode is electrically connected to drain electrode by described via hole.
A process of manufacturing dot structure, comprises: a substrate is provided; Above substrate, form grid, the side at described grid forms the first bulge-structure simultaneously; Above described grid, form gate insulator; Above described gate insulator, the position of corresponding grid forms active layer, forms the second bulge-structure in the position of corresponding the first projection of active layer simultaneously; At described active layer upper surface, source electrode and drain electrode are set discretely, described drain electrode covers described the first projection and the second projection; Above source electrode and drain electrode layer, form passivating film; Above passivating film, form public electrode; Above described public electrode, form upper portion insulating film; Formation runs through the via hole of described upper portion insulating film and described passivating film; Above described upper portion insulating film, form pixel electrode, described pixel electrode is electrically connected to drain electrode by described via hole.
The present invention has one or more technique effect as follows:
1, can reduce the via size that pixel electrode drains and is connected with thin film transistor (TFT) (TFT), thereby effectively prevent the undesired phenomenons such as light leak that cause of via hole top liquid crystal deflection.
2, can reduce the size of the via hole black matrix in top (BM), thereby improve transmittance.
3, can form TFT and projection by a step process simultaneously, without additional technical steps, save cost.
Accompanying drawing explanation
Fig. 1 is the dot structure schematic diagram of prior art;
The dot structure vertical view schematic diagram that Fig. 2 provides for first embodiment of the invention;
Fig. 3 is the cut-open view of A-A ' in Fig. 2;
Fig. 4 is dot structure abstract geometry figure schematic diagram provided by the invention;
The dot structure schematic diagram that Fig. 5 provides for second embodiment of the invention;
The dot structure schematic diagram that Fig. 6 provides for third embodiment of the invention;
The dot structure schematic diagram that Fig. 7 provides for fourth embodiment of the invention;
The dot structure schematic diagram that Fig. 8 provides for fifth embodiment of the invention;
Fig. 9 is dot structure abstract geometry schematic diagram provided by the invention.
Embodiment
In order to be illustrated more clearly in the embodiment of the present invention or technical scheme of the prior art; below in conjunction with the accompanying drawing in the embodiment of the present invention; technical scheme in the embodiment of the present invention is clearly and completely described; apparently; accompanying drawing in the following describes is only several embodiment of the present invention; and not all embodiments; embodiment based in the present invention; those of ordinary skills, not making the every other embodiment obtaining under creative work prerequisite, belong to the scope of protection of the invention.
Embodiment mono-
Please refer to Fig. 2, is the first embodiment schematic diagram of dot structure of the present invention, in the present embodiment, comprises sweep trace 201 and data line 211 on substrate, and the two insulation intersects to form pixel cell region.
Please refer to Fig. 3, is the cut-open view of A-A ' in Fig. 2 edge.In conjunction with Fig. 2 and Fig. 3, can find out, this dot structure comprises a substrate, substrate top is provided with grid 201, and a side of grid 201 is also formed with the first projection 212, alternatively, the thickness of the first projection 212 is identical with the thickness of grid 201, and the two adopts same material to make, because the two adopts same material, has same thickness, the first projection 212 can adopt same mask plate with grid 201, in a step operation, make, save the protruding additional process of preparation.Grid top is provided with gate insulator 202, active layer 203 is arranged at gate insulator 202 tops, and be positioned at grid 201 tops, active layer 203 is formed with the second projection 213 with the upper position corresponding to the first projection of layer, alternatively, second thickness of projection 213 is identical with the thickness of active layer, and the two adopts same material to make because the two adopts same material, has same thickness, therefore the first projection 213 can adopt same mask plate with active layer 203, in a step operation, make, save the protruding additional process of preparation.Source electrode 204 and drain electrode 205 are set discretely above active layer 203, drain electrode 205 has drain electrode extension 205a, drain electrode extension 205a covers first projection the 212 and second projection 213, and source electrode 204, drain electrode 205 tops are formed with inorganic passivating film 206 and the organic passivation film 207 that covers whole substrate successively.On organic passivation film 207, form public electrode 208, public electrode 208 tops form upper portion insulating film 209, form pixel electrode 210 on upper portion insulating film 209.Pixel electrode 210 is connected with drain electrode extension 205a by running through the via hole 211 of upper portion insulating film 209, organic passivation film 207 and inorganic passivating film 207.
Please refer to Fig. 4, Fig. 4 is dot structure abstract geometry figure of the present invention, wherein, and d
1for prior art via hole top width, d
2for via hole top width of the present invention, d
3for prior art via bottom width, Δ d is the size that the present invention reduces than prior art via hole top width, h
1for prior art is crossed hole depth, h
2for the present invention crosses hole depth, Δ h is the size that the present invention reduces than the prior art via hole degree of depth, and θ is the angle of via sidewall and vertical direction.As shown in Figure 4:
△d=d
1-d
2=(d
3+2*h
1tanθ)-(d
3+2*h
2tanθ)=2*tanθ(h
1-h
2)=2*tanθ△h...........................................................（1）
Wherein, θ value is relevant to technique, and △ h is relevant to the thickness of protrusions of the present invention, and from formula (1), known △ h is larger, and the effect that reduces via size is more obvious.In the present embodiment, get tan θ=0.15,
?
therefore in the present embodiment, the size of via hole has reduced 15% than prior art.
Because via hole top liquid crystal deflection orientation is chaotic, via hole top adopts black matrix (BM) to block conventionally at present, and this can cause the reduction of light transmission rate, and the present invention can effectively reduce via size, thereby reduces BM size, improves the transmitance of light.
Alternatively, first projection the 212 and second projection 213 is positioned under via hole 211 or pixel electrode 210 and drain electrode 205 surface of contact, therefore can more effectively play and reduce to drain 205 and the vertical range of pixel electrode 210, thereby reduce the size of via hole 211.
Alternatively, first projection the 212 and second projection 213 can be comprised of a projection respectively, also can be formed by stacking by a plurality of projections, the shape of projection can be cylindrical, conical, prismatic etc., as long as can play the projection of raising the effect of drain electrode extension 205a thickness, all within thought of the present invention.
Alternatively, public electrode 208 is sheet, and pixel electrode 210 is strip.
The present invention also comprises a kind of process of manufacturing dot structure, comprises: a substrate is provided; Above substrate, form grid, the side at described grid is formed with bulge-structure simultaneously; Above described grid, form gate insulator; The position of the corresponding grid in gate insulator top forms active layer; At active layer upper surface, insulate source electrode and drain electrode are set, described drain electrode covers described projection; Above source electrode and drain electrode layer, form passivating film; Above passivating film, form public electrode; Above described public electrode, form upper portion insulating film; Formation runs through the via hole of described upper portion insulating film and described passivating film; Above described upper portion insulating film, form pixel electrode, described pixel electrode is electrically connected to drain electrode by described via hole.
In the present embodiment, first projection the 212 and second projection 213 all adopts the TFT material of its place layer, adopts same mask plate with the TFT of its place layer, same step etching technics is made, and without additional step, can simplify production technology, improving production efficiency, saves cost.Due to what adopt in the present embodiment, be normal masks plate, cheaper compared to gray scale mask plate price, therefore can save cost.In addition, adopt two methods that projection combines, can, not increasing additional step, without when using complicated mask plate, increase protruding gross thickness, thereby more effectively reduce protruding size.
Embodiment bis-
Please refer to Fig. 5, is the schematic diagram of second embodiment of the invention.The difference part of the present embodiment and the first embodiment is, the projection 312 of the present embodiment is formed on gate insulator 302.Alternatively, adopt gray scale mask plate, in same step etching technics, etch and have protruding gate insulator, the advantage of the present embodiment is to adopt with gate insulator same material, in same step process, make, save etching technics one, simplified technique, saved cost.In addition, gate insulator material cost is comparatively cheap, and employing gate insulator, can reduce costs than additive method as projection.
According to formula (1), when tan θ=0.15,
?
therefore in the present embodiment, the size of via hole has reduced 46.5% than prior art.
The present invention also comprises a kind of process of manufacturing dot structure, comprises:: a substrate is provided; Above substrate, form grid; Above described grid, form gate insulator, in the position of corresponding grid one side, form bulge-structure simultaneously; Above gate insulator, the position of corresponding grid forms active layer; , at active layer upper surface, to insulate source electrode and drain electrode are set, described drain electrode covers described projection; Above source electrode and drain electrode layer, form passivating film; Above passivating film, form public electrode; Above described public electrode, form upper portion insulating film; Formation runs through the via hole of described upper portion insulating film and described passivating film; Above described upper portion insulating film, form pixel electrode, described pixel electrode is electrically connected to drain electrode by described via hole.
Embodiment tri-
Please refer to Fig. 6, is the schematic diagram of third embodiment of the invention.The difference part of the present embodiment and the first embodiment is, 412 of the projections of the present embodiment are formed at grid 401 with on layer.The thickness of projection 412 can equal the thickness of grid 401, also can be greater than the thickness of grid 401, when protruding thickness is greater than the thickness of grid 401, adopts gray scale mask plate in a step process, to etch the grid layer with different-thickness.The advantage of the present embodiment is that 401 layers of same material of employing and grid are made projection, in same step process, made, and have saved etching technics one, simplify technique, saving cost.Thickness when protruding 412 equals the thickness of grid 401, and pattern and the grid 401 of projection 412 can adopt same normal masks plate etching, simple and convenient, because normal masks plate is cheaper compared to gray scale mask plate price, therefore can save cost.When the thickness of projection 412 is greater than the thickness of grid 401, the effect that reduces via hole is more excellent.
According to formula (1), when protruding thickness equals gate, get tan θ=0.15,
?
the size of via hole has reduced 8.1% than prior art; When protruding thickness is greater than gate, get tan θ=0.15,
?
therefore in the present embodiment, the size of via hole has reduced 46.5% than prior art.
The present invention also comprises a kind of process of manufacturing dot structure, comprises: a substrate is provided; Above substrate, form grid, the side at described grid forms the first bulge-structure simultaneously; Above described grid, form gate insulator; Above described gate insulator, the position of corresponding grid forms active layer, forms the second bulge-structure in the position of corresponding the first projection of active layer simultaneously; At described active layer upper surface, source electrode and drain electrode are set discretely, described drain electrode covers described the first projection and the second projection; Above source electrode and drain electrode layer, form passivating film; Above passivating film, form public electrode; Above described public electrode, form upper portion insulating film; Formation runs through the via hole of described upper portion insulating film and described passivating film; Above described upper portion insulating film, form pixel electrode, described pixel electrode is electrically connected to drain electrode by described via hole.
Embodiment tetra-
Please refer to Fig. 7, is the schematic diagram of fourth embodiment of the invention.The difference part of the present embodiment and the first embodiment is, 512 of the projections of the present embodiment are formed at active layer with on layer.The thickness of projection can equal the thickness of TFT active layer 503, also can be greater than the thickness of TFT active layer 503, when protruding thickness is greater than the thickness of TFT active layer 503, adopt gray scale mask plate in a step process, to etch the active layer 503 with different-thickness.The advantage of the present embodiment is that employing is made projection, in same step process, made with active layer same material, has saved etching technics one, simplifies technique, saving cost.Thickness when protruding 512 equals the thickness of active layer, and pattern and the TFT active layer 503 of projection 512 can adopt a normal masks plate etching, simple and convenient, because normal masks plate is cheaper compared to gray scale mask plate price, therefore can save cost.When the thickness of projection 512 is greater than the thickness of TFT active layer 503, the effect that reduces via hole is more excellent.
According to formula (1), when protruding thickness equals TFT active layer thickness, get tan θ=0.15,
?
the size of via hole has reduced 2.4% than prior art; When protruding thickness is greater than TFT active layer thickness, get tan θ=0.15,
?
therefore in the present embodiment, the size of via hole has reduced 46.5% than prior art.
The present invention also comprises a kind of process of manufacturing dot structure, comprises: a substrate is provided; Above substrate, form grid; Above described grid, form gate insulator; Above described gate insulator, the position of corresponding grid forms active layer, and the side at described active layer forms bulge-structure simultaneously; At described active layer upper surface, source electrode and drain electrode are set discretely, described drain electrode covers described projection; Above source electrode and drain electrode layer, form passivating film; Above passivating film, form public electrode; Above described public electrode, form upper portion insulating film; Formation runs through the via hole of described upper portion insulating film and described passivating film; Above described upper portion insulating film, form pixel electrode, described pixel electrode is electrically connected to drain electrode by described via hole.
Embodiment five
Please refer to Fig. 8, is the schematic diagram of fifth embodiment of the invention.The present embodiment is the application of the present invention in the grid dot structure of top.As can be seen from Figure 8, substrate 600 tops are provided with light shield layer 603(LSM), light shield layer 603 tops are provided with active layer 603, active layer 603 tops are equipped with the gate insulator 602 that covers whole substrate, gate insulator 602 tops are provided with grid 601, grid top is provided with the first insulation course 620, be provided with to the first insulation course 620 top insulation source electrode 604 and drain electrode 605, wherein, the first insulation course 620 comprises projection 612, the material of projection 612 is identical with the first insulation course 620, the two forms in same step process by gray scale mask plate, therefore technique is simple, can reduce via hole again.Be positioned at drain electrode 605 belows.Source electrode 604, drain electrode 605 tops cover one or more layers passivating film, and are provided with the via hole that runs through passivating film, and passivating film top is provided with pixel electrode 610, and pixel electrode 610 is electrically connected to drain electrode 605 by via hole.
Alternatively, in dot structure of the present invention, can also comprise etching barrier layer (ESL).
In the present invention, after convexing to form, its top can form some layers of overlayer, because protruding side and horizontal direction have certain angle, therefore and each overlayer all has certain thickness, having spread the ledge width that overlayer forms after this layer material increases to some extent than the width of former projection.In order to make better drain electrode contact with pixel electrode, alternatively, the overlayer ledge width contacting with pixel electrode is more than or equal to pixel electrode width.Please refer to Fig. 9, is the former projection of the present invention and top overlayer abstract geometry figure thereof, wherein, supposes the tectal thickness homogeneous in top, S
1for former projection thickness, S
2for top overlayer ledge width, L
1for former projection thickness, L
2for top cover thickness, β is the angle of former protruding side and vertical direction, by technological level and technological parameter, is determined, △ S is the size that overlayer convexity former ledge width in top increases.By how much, derive and can obtain:
S
2=△S+S
1=2*(L
2/cosβ-L
2tanβ)+S
1...................................................（2）
If former projection top is provided with n layer overlayer, the rest may be inferred, can calculate the overlayer ledge width S of n layer
n.In the present invention, more fully reliable for drain electrode is electrically connected to pixel electrode, S
n(being the width of drain electrode layer projection) should be more than or equal to pixel electrode bottom width.
Alternatively, projection of the present invention and/or drain electrode adopt transparent material to make, and are conducive to like this increase the transmitance of light.
Drain electrode of the present invention can be source electrode, and source electrode can be drain electrode, and the two can exchange.
The present invention also comprises a kind of liquid crystal panel, by dot structure of the present invention, by array way, is rearranged.
In addition,, although present specification embodiment be take IPS as example, the present invention is equally applicable to other display modes, as organic light emitting display.
Except following five embodiment, the present invention can also expand to the combination of one or more layers protrusions arbitrarily of TFT layer, although in specific embodiment, do not list one by one, within being included in equally thought of the present invention.
Claims (17)
1. a dot structure, is characterized in that, comprises:
Substrate;
Thin film transistor (TFT), is arranged at described substrate top, and described thin film transistor (TFT) comprises grid, gate insulator, active layer, source electrode, drain electrode;
At least one projection, described projection adopts arbitrary layer of same material of thin film transistor (TFT) to make, and described projection is positioned at described drain electrode below;
Passivating film, is covered in described thin film transistor (TFT) top;
Public electrode, is arranged at described passivating film top;
Upper portion insulating film, is arranged at described public electrode top;
Via hole, runs through described upper portion insulating film and described passivating film;
Pixel electrode, is arranged at described upper portion insulating film top, and described pixel electrode is electrically connected to the drain electrode of described thin film transistor (TFT) by described via hole.
2. dot structure according to claim 1, is characterized in that, described in convex to form in described grid with layer.
3. dot structure according to claim 1, is characterized in that, described in convex to form in described gate insulator with layer.
4. dot structure according to claim 1, is characterized in that, described in convex to form in described active layer with layer.
5. dot structure according to claim 1, is characterized in that, described projection comprises first protruding the second projection with being formed at described the first projection top, and described the first projection and the described second protruding dividing are formed at the difference two-layer of thin film transistor (TFT).
6. dot structure according to claim 5, is characterized in that, described first convexes to form in the same layer of grid, and described second convexes to form in active layer with layer.
7. according to the dot structure described in claim 5 or 6, it is characterized in that, the thickness of described the first projection is identical with described grid, and the thickness of described the second projection is identical with described active layer.
8. dot structure according to claim 1, is characterized in that, the thickness of described projection is more than or equal to the thickness of layer identical with described raised material in thin film transistor (TFT).
9. dot structure according to claim 1, is characterized in that, described projection is positioned at corresponding under described via hole.
10. dot structure according to claim 1, is characterized in that, the drain width that covers described projection top is more than or equal to the pixel electrode width contacting with described drain electrode.
11. dot structures according to claim 1, is characterized in that, described projection and/or described drain electrode adopt transparent material to make.
12. dot structures according to claim 1, is characterized in that, described passivating film comprises organic passivation film and/or inorganic passivating film.
13. 1 kinds of liquid crystal panels, is characterized in that, comprise the dot structure described in claim 1-11.
14. 1 kinds of processes of manufacturing dot structure, is characterized in that, comprise: a substrate is provided; Above substrate, form grid, the side at described grid is formed with bulge-structure simultaneously; Above described grid, form gate insulator; The position of the corresponding grid in gate insulator top forms active layer; At active layer upper surface, insulate source electrode and drain electrode are set, described drain electrode covers described projection; Above source electrode and drain electrode layer, form passivating film; Above passivating film, form public electrode; Above described public electrode, form upper portion insulating film; Formation runs through the via hole of described upper portion insulating film and described passivating film; Above described upper portion insulating film, form pixel electrode, described pixel electrode is electrically connected to drain electrode by described via hole.
15. 1 kinds of processes of manufacturing dot structure, is characterized in that, comprise: a substrate is provided; Above substrate, form grid; Above described grid, form gate insulator, in the position of corresponding grid one side, form bulge-structure simultaneously; Above gate insulator, the position of corresponding grid forms active layer; , at active layer upper surface, to insulate source electrode and drain electrode are set, described drain electrode covers described projection; Above source electrode and drain electrode layer, form passivating film; Above passivating film, form public electrode; Above described public electrode, form upper portion insulating film; Formation runs through the via hole of described upper portion insulating film and described passivating film; Above described upper portion insulating film, form pixel electrode, described pixel electrode is electrically connected to drain electrode by described via hole.
16. 1 kinds of processes of manufacturing dot structure, is characterized in that, comprise: a substrate is provided; Above substrate, form grid; Above described grid, form gate insulator; Above described gate insulator, the position of corresponding grid forms active layer, and the side at described active layer forms bulge-structure simultaneously; At described active layer upper surface, source electrode and drain electrode are set discretely, described drain electrode covers described projection; Above source electrode and drain electrode layer, form passivating film; Above passivating film, form public electrode; Above described public electrode, form upper portion insulating film; Formation runs through the via hole of described upper portion insulating film and described passivating film; Above described upper portion insulating film, form pixel electrode, described pixel electrode is electrically connected to drain electrode by described via hole.
17. 1 kinds of processes of manufacturing dot structure, is characterized in that, comprise: a substrate is provided; Above substrate, form grid, the side at described grid forms the first bulge-structure simultaneously; Above described grid, form gate insulator; Above described gate insulator, the position of corresponding grid forms active layer, forms the second bulge-structure in the position of corresponding the first projection of active layer simultaneously; At described active layer upper surface, source electrode and drain electrode are set discretely, described drain electrode covers described the first projection and the second projection; Above source electrode and drain electrode layer, form passivating film; Above passivating film, form public electrode; Above described public electrode, form upper portion insulating film; Formation runs through the via hole of described upper portion insulating film and described passivating film; Above described upper portion insulating film, form pixel electrode, described pixel electrode is electrically connected to drain electrode by described via hole.
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| CN109599419A (en) * | 2018-10-23 | 2019-04-09 | 武汉华星光电半导体显示技术有限公司 | A kind of array substrate and its manufacturing method |
| US10916609B2 (en) | 2018-10-23 | 2021-02-09 | Wuhan China Star Optoelectronics Semiconductor Display Technology Co., Ltd. | Array substrate and method for manufacturing array substrate |
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