CN103984586A - Interface drive method for EMIF (external memory interface) and FPGA (field programmable gate array) under embedded type Linux system - Google Patents
Interface drive method for EMIF (external memory interface) and FPGA (field programmable gate array) under embedded type Linux system Download PDFInfo
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Abstract
The invention discloses an interface drive method for an EMIF (external memory interface) and an FPGA (field programmable gate array) under an embedded type Linux system, belongs to the field of data transmission and solves a problem that existing EMIF and FPGA interfaces of a DSP (data signal processor) under the Linux system cannot realize image data transmission. The drive interface method comprises the following steps: firstly, realizing loading of an EMIF drive module on a drive equipment loading function and unloading on an unloading function; secondly, by virtue of the EMIF drive module, carrying out writing operation onto FIFO (first in, first out) in the FPGA in a sending device by an EMIF end port of the DSP in the sending device; thirdly, performing an interrupt processing process and awaking a reading process after the DSP in the receiving device receives an interrupt signal; and finally, by virtue of the EMIF drive module, carrying out reading operation onto FIFO in the FPGA in a receiving device by the EMIF port of the DSP in the receiving device. The interface drive method disclosed by the invention is used for realizing data communication between the EMIF port and the FPGA interface.
Description
Technical field
The invention belongs to field of data transmission.
Background technology
Along with the development of growth in the living standard and scientific and technological level, people are more and more higher to the requirement of image processing, as video conference, video monitoring, video calling etc.But before Leonardo da Vinci (Davinci) technology occurs, for different needs, developer needs to be grasped the development knowledge of different picture processing chip and software, this has increased difficulty and the construction cycle of new product development greatly.For above-mentioned situation, TI company is on the basis of DSP technology, and in conjunction with ARM, image coding and decoding standard, TI programming specification etc. has proposed Davinci technology framework.Davinci Technical Architecture greatly reduces the complexity of image processing, has shortened the R&D cycle of product, and can also enhance product performance.
Along with DSP processing speed improves and developing instrument perfect, its range of application is more and more extensive.Because the internal RAM of DSP is limited, so will realize the acquisition and processing of mass data, need to expand the RAM of DSP.
In addition, in the process of radio communication, the serial data often of transmission, but due to the hardware principle of DSP own and instruction, make DSP not carry out seamless link with Wireless Telecom Equipment.
EMIF interface by DSP is connected with FPGA, can make DSP obtain larger external memory space.Meanwhile, because FPGA has flexible in programming, make DSP to carry out seamless link with numerous module devices, so just greatly expanded the range of application of DSP.
Summary of the invention
The present invention is the problem that EMIF in order to solve existing DSP under linux system and FPGA interface cannot be realized image data transmission, the invention provides EMIF under a kind of embedded Linux system and the interface driver method of FPGA.
The interface driver method of EMIF under embedded Linux system and FPGA, it is realized based on following dispensing device and receiving trap, and the data-signal output terminal of dispensing device is connected with the data-signal input end of receiving trap,
Dispensing device comprises a DSP and a FPGA, wherein, the writing of described DSP enables control signal output terminal and is connected with the enable signal input end of writing of FPGA, the write clock signal output terminal of DSP is connected with the write clock signal input end of FPGA, the data-signal output terminal of DSP is connected with the data-signal input end of FPGA, and in dispensing device, the data-signal output terminal of FPGA is as the data-signal output terminal of dispensing device;
Receiving trap comprises a DSP and a FPGA, wherein, the reading of described FPGA enables control signal input end and is connected with the enable signal output terminal of reading of DSP, the read clock signal input end of FPGA is connected with the read clock signal output terminal of DSP, the interrupt trigger signal output terminal of FPGA is connected with the look-at-me input end of DSP, the data-signal output terminal of FPGA is connected with the data-signal input end of DSP, and in receiving trap, the data-signal input end of FPGA is as the data-signal input end of receiving trap;
DSP in DSP and receiving trap in dispensing device is the DSP that contains EMIF port,
DSP in DSP and receiving trap in dispensing device has all embedded (SuSE) Linux OS and EMIF driver module, and under (SuSE) Linux OS, EMIF driver module is for realizing communicating by letter of DSP and FPGA,
Be embedded in the DSP inside in dispensing device EMIF driver module realize to the method for FPGA interface driver be,
Step 1: realize the loading of EMIF driver module to driving arrangement loading function and the unloading of this driving arrangement unloading function,
Step 2: by EMIF driver module, the FIFO of FPGA is mapped as to a memory address of DSP, to the write operation of FIFO be mapped as to the write operation to described memory address, the EMIF port of realizing the DSP in dispensing device carries out write operation to FIFO in the FPGA in dispensing device
Step 3: the DSP in receiving trap receives after interrupt trigger signal, carry out interrupt handling program, in the FIFO of the FPGA of the EMIF port that makes the DSP in receiving trap from receiving trap, read the byte specifying number, and store in the buffer area of (SuSE) Linux OS kernel, wake the process of reading up;
Step 4: by EMIF driver module, the FIFO of FPGA is mapped as to a memory address of DSP, to the read operation of FIFO be mapped as to the read operation to described memory address, the EMIF port of realizing the DSP in receiving trap carries out read operation to FIFO in the FPGA in receiving trap, completes the data communication between EMIF port and the interface of FPGA.
Described loading and this driving arrangement of EMIF driver module to driving arrangement loading function of realizing unloads in the unloading of function, and EMIF driver module to the loading procedure of driving arrangement loading function is:
In process driving arrangement being driven at EMIF driver module, first, device number is applied for, and EMIF driver module is registered in (SuSE) Linux OS, (SuSE) Linux OS determines by device number the EMIF driver module that this equipment is corresponding, complete the loading of EMIF driver module to driving arrangement loading function
EMIF driver module to the uninstall process of driving arrangement unloading function is:
Device number is discharged, and internal memory shared EMIF driver module corresponding driving arrangement is discharged, and return to I/O resource to system, complete the unloading of EMIF driver module to driving arrangement unloading function.
The detailed process that the described EMIF port of realizing the DSP in dispensing device carries out write operation to FIFO in the FPGA in dispensing device is,
By write operation read () function, data are copied in the DSP from dispensing device in the FIFO of the FPGA in dispensing device.
The detailed process that the described EMIF port of realizing the DSP in receiving trap carries out read operation to FIFO in the FPGA in receiving trap is,
By read operation write () function by the data Replica of the kernel buffer area of DSP in receiving trap to user's space.
DSP in described receiving trap receives after interrupt trigger signal, carries out the detailed process of interrupt handling program to be,
Step 4-1: remove interrupt identification, execution step 4-2,
Step 4-2: employing I/O handling function is the buffer area to the kernel spacing of the DSP of receiving trap by the data Replica of FIFO in the FPGA of receiving trap, execution step 4-3,
Step 4-3: judge the buffer area half of kernel spacing whether completely, result is yes, execution step 4-4, result is no, execution step 4-5,
Step 4-4: wake the process of reading of the user's space of obstruction up, execution step 4-5;
Step 4-5: interrupt returning.
Described read operation the write () function that passes through by the data Replica of the kernel buffer area of DSP in receiving trap to the detailed process of user's space is:
Step 5-1: whether the kernel buffer area that judges DSP in receiving trap is empty, and result is yes, execution step 5-2, result is no, execution step 5-3,
Step 5-2: read process dormancy, until buffer area is not while being empty, execution step 5-3,
Step 5-3: wake the process of reading up, execution step 5-4,
Step 5-4: by read operation write () function by the data Replica of the kernel buffer area of DSP in receiving trap to user's space, execution step 5-5,
Step 5-5: release semaphore.
The described detailed process of passing through in write operation read () function copies to data the FPGA in dispensing device FIFO in the DSP from dispensing device is:
Step 3-1: in dispensing device, after the kernel spacing application buffer area of DSP, perform step 3-2,
Step 3-2: the buffer area by the data Replica of user's space to kernel spacing, execution step 3-3,
Step 3-3: by write operation read () function by kernel spacing buffer area content replication in the FIFO of the FPGA in dispensing device, execution step 3-4;
Step 3-4: release semaphore.
It is the chip realization of TMS320DM365 that DSP in DSP and receiving trap in described dispensing device all adopts model.In whole system, 3 test point A, B, C are set, test, test point A, B, the C position in system as shown in Figure 4.
In test process, first in dispensing device, TMS320DM365 sends data to FPGA in this device, then in dispensing device, FPGA sends the data to FPGA in receiving trap, and in last receiving trap, FPGA sends the data to TMS320DM365 in receiving trap again.Wherein the FPGA waveform of A, B and tri-test points of C, respectively as shown in Fig. 6,7 and 8, by comparing the data of TMS320DM365 send and receive, proves that the Interface design between TMS320DM365 and FPGA is correct.
The beneficial effect that the present invention brings is to have realized EMIF and the FPGA Interface realization image data transmission of the DSP under linux system.
Brief description of the drawings
Fig. 1 is dispensing device described in embodiment one and the principle schematic of receiving trap;
Fig. 2 is in embodiment six, by read operation write () function by the data Replica of the kernel buffer area of DSP in receiving trap the process flow diagram to user's space;
Fig. 3 is in embodiment seven, by write operation read () function, data is copied to the process flow diagram in the FIFO of the FPGA in dispensing device in the DSP from dispensing device;
Fig. 4 is in embodiment eight, test point A, B, the C position relationship schematic diagram in dispensing device and receiving trap;
Fig. 5 is in embodiment five, and the DSP in described receiving trap receives after interrupt trigger signal, carries out the process flow diagram of interrupt handling program;
Fig. 6 is the waveform schematic diagram of test point A;
Fig. 7 is the waveform schematic diagram of test point B;
Fig. 8 is the waveform schematic diagram of test point C.
Embodiment
Embodiment one: present embodiment is described referring to Fig. 1, the interface driver method of EMIF under embedded Linux system described in present embodiment and FPGA, it is realized based on following dispensing device and receiving trap, the data-signal output terminal of dispensing device is connected with the data-signal input end of receiving trap
Dispensing device comprises a DSP and a FPGA, wherein, the writing of described DSP enables control signal output terminal and is connected with the enable signal input end of writing of FPGA, the write clock signal output terminal of DSP is connected with the write clock signal input end of FPGA, the data-signal output terminal of DSP is connected with the data-signal input end of FPGA, and in dispensing device, the data-signal output terminal of FPGA is as the data-signal output terminal of dispensing device;
Receiving trap comprises a DSP and a FPGA, wherein, the reading of described FPGA enables control signal input end and is connected with the enable signal output terminal of reading of DSP, the read clock signal input end of FPGA is connected with the read clock signal output terminal of DSP, the interrupt trigger signal output terminal of FPGA is connected with the look-at-me input end of DSP, the data-signal output terminal of FPGA is connected with the data-signal input end of DSP, and in receiving trap, the data-signal input end of FPGA is as the data-signal input end of receiving trap;
DSP in DSP and receiving trap in dispensing device is the DSP that contains EMIF port,
DSP in DSP and receiving trap in dispensing device has all embedded (SuSE) Linux OS and EMIF driver module, and under (SuSE) Linux OS, EMIF driver module is for realizing communicating by letter of DSP and FPGA,
Be embedded in the DSP inside in dispensing device EMIF driver module realize to the method for FPGA interface driver be,
Step 1: realize the loading of EMIF driver module to driving arrangement loading function and the unloading of this driving arrangement unloading function,
Step 2: by EMIF driver module, the FIFO of FPGA is mapped as to a memory address of DSP, to the write operation of FIFO be mapped as to the write operation to described memory address, the EMIF port of realizing the DSP in dispensing device carries out write operation to FIFO in the FPGA in dispensing device
Step 3: the DSP in receiving trap receives after interrupt trigger signal, carry out interrupt handling program, in the FIFO of the FPGA of the EMIF port that makes the DSP in receiving trap from receiving trap, read the byte specifying number, and store in the buffer area of (SuSE) Linux OS kernel, wake the process of reading up;
Step 4: by EMIF driver module, the FIFO of FPGA is mapped as to a memory address of DSP, to the read operation of FIFO be mapped as to the read operation to described memory address, the EMIF port of realizing the DSP in receiving trap carries out read operation to FIFO in the FPGA in receiving trap, completes the data communication between EMIF port and the interface of FPGA.
Embodiment two: the difference of the EMIF under the embedded Linux system described in present embodiment and embodiment one and the interface driver method of FPGA is, described loading and this driving arrangement of EMIF driver module to driving arrangement loading function of realizing unloads in the unloading of function
EMIF driver module to the loading procedure of driving arrangement loading function is:
In process driving arrangement being driven at EMIF driver module, first, device number is applied for, and EMIF driver module is registered in (SuSE) Linux OS, (SuSE) Linux OS determines by device number the EMIF driver module that this equipment is corresponding, complete the loading of EMIF driver module to driving arrangement loading function
EMIF driver module to the uninstall process of driving arrangement unloading function is:
Device number is discharged, and internal memory shared EMIF driver module corresponding driving arrangement is discharged, and return to I/O resource to system, complete the unloading of EMIF driver module to driving arrangement unloading function.Embodiment three: the difference of the interface driver method of the EMIF under the embedded Linux system described in present embodiment and embodiment one or two and FPGA is, the detailed process that the described EMIF port of realizing the DSP in dispensing device carries out write operation to FIFO in the FPGA in dispensing device is
By write operation read () function, data are copied in the DSP from dispensing device in the FIFO of the FPGA in dispensing device.
Embodiment four: the difference of the EMIF under the embedded Linux system described in present embodiment and embodiment three and the interface driver method of FPGA is, the detailed process that the described EMIF port of realizing the DSP in receiving trap carries out read operation to FIFO in the FPGA in receiving trap is
By read operation write () function by the data Replica of the kernel buffer area of DSP in receiving trap to user's space.
Embodiment five: present embodiment is described referring to Fig. 5, the difference of the EMIF under the embedded Linux system described in present embodiment and embodiment one, two or four and the interface driver method of FPGA is, DSP in described receiving trap receives after interrupt trigger signal, the detailed process of carrying out interrupt handling program is
Step 4-1: remove interrupt identification, execution step 4-2,
Step 4-2: employing I/O handling function is the buffer area to the kernel spacing of the DSP of receiving trap by the data Replica of FIFO in the FPGA of receiving trap, execution step 4-3,
Step 4-3: judge the buffer area half of kernel spacing whether completely, result is yes, execution step 4-4, result is no, execution step 4-5,
Step 4-4: wake the process of reading of the user's space of obstruction up, execution step 4-5;
Step 4-5: interrupt returning.
Embodiment six: present embodiment is described referring to Fig. 2, the difference of the EMIF under the embedded Linux system described in present embodiment and embodiment four and the interface driver method of FPGA is, described read operation the write () function that passes through by the data Replica of the kernel buffer area of DSP in receiving trap to the detailed process of user's space is:
Step 5-1: whether the kernel buffer area that judges DSP in receiving trap is empty, and result is yes, execution step 5-2, result is no, execution step 5-3,
Step 5-2: read process dormancy, until buffer area is not while being empty, execution step 5-3,
Step 5-3: wake the process of reading up, execution step 5-4,
Step 5-4: by read operation write () function by the data Replica of the kernel buffer area of DSP in receiving trap to user's space, execution step 5-5,
Step 5-5: release semaphore.
Embodiment seven: present embodiment is described referring to Fig. 3, the difference of the EMIF under the embedded Linux system described in present embodiment and embodiment three and the interface driver method of FPGA is, the described detailed process of passing through in write operation read () function copies to data the FPGA in dispensing device FIFO in the DSP from dispensing device is:
Step 3-1: in dispensing device, after the kernel spacing application buffer area of DSP, perform step 3-2,
Step 3-2: the buffer area by the data Replica of user's space to kernel spacing, execution step 3-3,
Step 3-3: by write operation read () function by kernel spacing buffer area content replication in the FIFO of the FPGA in dispensing device, execution step 3-4;
Step 3-4: release semaphore.
Embodiment eight: the difference of the EMIF under the embedded Linux system described in present embodiment and embodiment one, two, four, six or seven and the interface driver method of FPGA is, it is that the chip of TMS320DM365 is realized that the DSP in DSP and receiving trap in described dispensing device all adopts model.
In present embodiment, during the TMS320DM365 of dispensing device is connected with the hardware of FPGA,
be the chip selection signal of TMS320DM365 output, enable as writing of FIFO in FPGA, and Low level effective; EM_D is the bidirectional data line of TMS320DM365, is data-out bus under this pattern, and FIFO is connected with FPGA input;
for the enable signal of writing of TMS320DM365 output, as the clock of writing of FIFO in FPGA, from the sequential of writing of EMIF interface, data can be
rising edge be stored in the FIFO of FPGA of dispensing device;
During the TMS320DM365 of receiving trap is connected with the hardware of FPGA,
the chip selection signal of TMS320DM365 output, as FIFO in FPGA read enable, and Low level effective; EM_D is the bidirectional data line of TMS320DM365, is data input bus (DIB) under this pattern, and FIFO is connected with FPGA output;
for the enable signal of reading of TMS320DM365 output, as the clock of reading of FIFO in FPGA.From the sequential of reading of EMIF interface,
rising edge video data is write in TMS320DM365 by the FIFO of FPGA by EMIF interface.
In present embodiment, in whole system, 3 test point A, B, C are set, test, test point A, B, the C position in system as shown in Figure 4.
In test process, first in dispensing device, TMS320DM365 sends data to FPGA in this device, then in dispensing device, FPGA sends the data to FPGA in receiving trap, and in last receiving trap, FPGA sends the data to TMS320DM365 in receiving trap again.Wherein the FPGA waveform of A, B and tri-test points of C, respectively as shown in Fig. 6,7 and 8, by comparing the data of TMS320DM365 send and receive, proves that the Interface design between TMS320DM365 and FPGA is correct.
Claims (8)
1. the interface driver method of the EMIF under embedded Linux system and FPGA, is characterized in that, it is realized based on following dispensing device and receiving trap, and the data-signal output terminal of dispensing device is connected with the data-signal input end of receiving trap,
Dispensing device comprises a DSP and a FPGA, wherein, the writing of described DSP enables control signal output terminal and is connected with the enable signal input end of writing of FPGA, the write clock signal output terminal of DSP is connected with the write clock signal input end of FPGA, the data-signal output terminal of DSP is connected with the data-signal input end of FPGA, and in dispensing device, the data-signal output terminal of FPGA is as the data-signal output terminal of dispensing device;
Receiving trap comprises a DSP and a FPGA, wherein, the reading of described FPGA enables control signal input end and is connected with the enable signal output terminal of reading of DSP, the read clock signal input end of FPGA is connected with the read clock signal output terminal of DSP, the interrupt trigger signal output terminal of FPGA is connected with the look-at-me input end of DSP, the data-signal output terminal of FPGA is connected with the data-signal input end of DSP, and in receiving trap, the data-signal input end of FPGA is as the data-signal input end of receiving trap;
DSP in DSP and receiving trap in dispensing device is the DSP that contains EMIF port,
DSP in DSP and receiving trap in dispensing device has all embedded (SuSE) Linux OS and EMIF driver module, and under (SuSE) Linux OS, EMIF driver module is for realizing communicating by letter of DSP and FPGA,
Be embedded in the DSP inside in dispensing device EMIF driver module realize to the method for FPGA interface driver be,
Step 1: realize the loading of EMIF driver module to driving arrangement loading function and the unloading of this driving arrangement unloading function,
Step 2: by EMIF driver module, the FIFO of FPGA is mapped as to a memory address of DSP, to the write operation of FIFO be mapped as to the write operation to described memory address, the EMIF port of realizing the DSP in dispensing device carries out write operation to FIFO in the FPGA in dispensing device
Step 3: the DSP in receiving trap receives after interrupt trigger signal, carry out interrupt handling program, in the FIFO of the FPGA of the EMIF port that makes the DSP in receiving trap from receiving trap, read the byte specifying number, and store in the buffer area of (SuSE) Linux OS kernel, wake the process of reading up;
Step 4: by EMIF driver module, the FIFO of FPGA is mapped as to a memory address of DSP, to the read operation of FIFO be mapped as to the read operation to described memory address, the EMIF port of realizing the DSP in receiving trap carries out read operation to FIFO in the FPGA in receiving trap, completes the data communication between EMIF port and the interface of FPGA.
2. the interface driver method of the EMIF under embedded Linux system according to claim 1 and FPGA, is characterized in that, described loading and this driving arrangement of EMIF driver module to driving arrangement loading function of realizing unloads in the unloading of function,
EMIF driver module to the loading procedure of driving arrangement loading function is:
In process driving arrangement being driven at EMIF driver module, first, device number is applied for, and EMIF driver module is registered in (SuSE) Linux OS, (SuSE) Linux OS determines by device number the EMIF driver module that this equipment is corresponding, complete the loading of EMIF driver module to driving arrangement loading function
EMIF driver module to the uninstall process of driving arrangement unloading function is:
Device number is discharged, and internal memory shared EMIF driver module corresponding driving arrangement is discharged, and return to I/O resource to system, complete the unloading of EMIF driver module to driving arrangement unloading function.
3. the interface driver method of the EMIF under embedded Linux system according to claim 1 and 2 and FPGA, it is characterized in that, the detailed process that the described EMIF port of realizing the DSP in dispensing device carries out write operation to FIFO in the FPGA in dispensing device is
By write operation read () function, data are copied in the DSP from dispensing device in the FIFO of the FPGA in dispensing device.
4. the interface driver method of the EMIF under embedded Linux system according to claim 3 and FPGA, is characterized in that, the detailed process that the described EMIF port of realizing the DSP in receiving trap carries out read operation to FIFO in the FPGA in receiving trap is,
By read operation write () function by the data Replica of the kernel buffer area of DSP in receiving trap to user's space.
5. according to the EMIF under the embedded Linux system described in claim 1,2 or 4 and the interface driver method of FPGA, it is characterized in that, the DSP in described receiving trap receives after interrupt trigger signal, carry out the detailed process of interrupt handling program to be,
Step 4-1: remove interrupt identification, execution step 4-2,
Step 4-2: employing I/O handling function is the buffer area to the kernel spacing of the DSP of receiving trap by the data Replica of FIFO in the FPGA of receiving trap, execution step 4-3,
Step 4-3: judge the buffer area half of kernel spacing whether completely, result is yes, execution step 4-4, result is no, execution step 4-5,
Step 4-4: wake the process of reading of the user's space of obstruction up, execution step 4-5;
Step 4-5: interrupt returning.
6. the interface driver method of the EMIF under embedded Linux system according to claim 4 and FPGA, it is characterized in that, described read operation the write () function that passes through by the data Replica of the kernel buffer area of DSP in receiving trap to the detailed process of user's space is:
Step 5-1: whether the kernel buffer area that judges DSP in receiving trap is empty, and result is yes, execution step 5-2, result is no, execution step 5-3,
Step 5-2: read process dormancy, until buffer area is not while being empty, execution step 5-3,
Step 5-3: wake the process of reading up, execution step 5-4,
Step 5-4: by read operation write () function by the data Replica of the kernel buffer area of DSP in receiving trap to user's space, execution step 5-5,
Step 5-5: release semaphore.
7. the interface driver method of the EMIF under embedded Linux system according to claim 3 and FPGA, it is characterized in that, the described detailed process of passing through in write operation read () function copies to data the FPGA in dispensing device FIFO in the DSP from dispensing device is:
Step 3-1: in dispensing device, after the kernel spacing application buffer area of DSP, perform step 3-2,
Step 3-2: the buffer area by the data Replica of user's space to kernel spacing, execution step 3-3,
Step 3-3: by write operation read () function by kernel spacing buffer area content replication in the FIFO of the FPGA in dispensing device, execution step 3-4;
Step 3-4: release semaphore.
8. according to the EMIF under the embedded Linux system described in claim 1,2,4,6 or 7 and the interface driver method of FPGA, it is characterized in that, it is the chip realization of TMS320DM365 that the DSP in DSP and receiving trap in described dispensing device all adopts model.
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| CN114860640A (en) * | 2022-04-07 | 2022-08-05 | 湖南艾科诺维科技有限公司 | FlexSPI interface driving method and system for communication between FPGA and ARM |
| CN114860640B (en) * | 2022-04-07 | 2023-06-06 | 湖南艾科诺维科技有限公司 | FlexSPI interface driving method and system for FPGA and ARM communication |
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