CN103943507A - Embedded germanium-silicon epitaxy dislocation fault improving method - Google Patents
Embedded germanium-silicon epitaxy dislocation fault improving method Download PDFInfo
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- CN103943507A CN103943507A CN201410111325.7A CN201410111325A CN103943507A CN 103943507 A CN103943507 A CN 103943507A CN 201410111325 A CN201410111325 A CN 201410111325A CN 103943507 A CN103943507 A CN 103943507A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/8238—Complementary field-effect transistors, e.g. CMOS
- H01L21/823814—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the source or drain structures, e.g. specific source or drain implants or silicided source or drain structures or raised source or drain structures
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- Insulated Gate Type Field-Effect Transistor (AREA)
Abstract
The invention discloses an embedded germanium-silicon epitaxy dislocation fault improving method. The method includes the following steps that firstly, the source and drain of a PMOS device are removed in an etching mode; secondly, a germanium-silicon seed crystal transition layer is arranged on a groove where the source and the drain are removed in the etching mode in a deposition mode, wherein the mass percent of germanium in the germanium-silicon seed crystal transition layer ranges from 5% to 10%, and the film layer thickness of the germanium-silicon seed crystal transition layer ranges from 15 nm to 30 nm; thirdly, a germanium-silicon source and a germanium-silicon drain are arranged on the germanium-silicon seed crystal transition layer in a deposition mode. Boundary surfaces between the germanium-silicon source and germanium-silicon drain of the PMOS device prepared through the embedded germanium-silicon epitaxy dislocation fault improving method and a substrate are clear and smooth, dislocation faults are greatly improved, and stress relaxation is alleviated.
Description
Technical field
The present invention relates to technical field of semiconductors, relate in particular to a kind of improvement method of embedded germanium and silicon epitaxial dislocation defects.
Background technology
As everyone knows, the performance of cmos circuit is limited by PMOS to a great extent.Therefore, any technology that the performance of PMOS can be brought up to the level of NMOS is all considered to favourable.Refer to Fig. 3, the PMOS structural representation that causes strain gauge technique is inserted in the source/leakage of the silicon of germanium shown in Fig. 3.In the 2nd PMOS device 2 of 90nm, the researcher of Intel removes the source electrode of device, drain electrode etching, then deposit germanium silicon layer again, such the second source electrode 21, the second drain electrode 22 will produce a compression stress to described the second raceway groove 23, thereby improve the transmission characteristic of described the 2nd PMOS device 2.
As is known to the person skilled in the art, described germanium silicon source/leakage is implanted and caused strain gauge technique is to source/drain region by described germanium silicon mosaic, thereby produce compressive deformation at described the second raceway groove 23 places, improve the carrier mobility of described the 2nd PMOS device 2, and the raising of described carrier mobility can cause high drive current, and then improve the performance of described the 2nd PMIOS device 2.
But, at described Si Grown germanium-silicon thin membrane, the technique of developing strain layer is epitaxy technique process, normally at present, if there is defect in described flute surfaces, germanium silicon can not form good mono-crystalline structures, in growth course, relaxation will occur, and the strain meeting accumulating in film causes crystal-plane slip, interface atomic arrangement is staggered, strain sharply discharges, and produces a large amount of defects in film, causes deformation relaxation.
Refer to Fig. 4, Figure 4 shows that the defect TEM that the source/leakage of germanium silicon is inserted in epitaxy technique schemes.Existing epitaxy technique flow process mainly comprises the following steps, step S1: before extension, carry out wet-cleaned; Step S2: chamber etching and overlay film; Step S3: the H2 baking before epitaxial growth; Step S4: germanium siliceous deposits.Significantly, certainly will there is certain defect 24 in the flute surfaces after cleaning, causes after epitaxial growth, and in generation of interfaces defect source, serious defect may be extended to the growing surface of germanium silicon.
Therefore the problem existing for prior art, this case designer relies on the industry experience for many years of being engaged in, and active research improvement, so there has been the improvement method of a kind of embedded germanium and silicon epitaxial dislocation defects of the present invention.
Summary of the invention
The present invention be directed in prior art, certainly will there is certain defect in the flute surfaces of traditional PMOS device after cleaning, cause after epitaxial growth, in generation of interfaces defect source, serious defect may be extended to the problems such as the growing surface of germanium silicon provides a kind of improvement method of embedded germanium and silicon epitaxial dislocation defects.
In order to address the above problem, the invention provides a kind of improvement method of embedded germanium and silicon epitaxial dislocation defects, described method comprises:
Execution step S1: etching remove described PMOS device source electrode and drain electrode;
Execution step S2: the brilliant transition zone of deposit germanium silicon kind on the described source electrode of removing in etching and the groove of described drain electrode place, the germanium mass percentage content of the brilliant transition zone of described germanium silicon kind is 5%～10%, the thicknesses of layers of the brilliant transition zone of described germanium silicon kind is 15～30nm;
Execution step S3: deposit germanium silicon source and the drain electrode of germanium silicon on the brilliant transition zone of described germanium silicon kind.
Alternatively, the dislocation defects of the PMOS device of the improvement method manufacture by described embedded germanium and silicon epitaxial dislocation defects is less than or equal to 17%.
In sum, adopt the germanium silicon source of the described PMOS device of preparing after the improvement method of the embedded germanium and silicon epitaxial dislocation defects of the present invention and the drain electrode of germanium silicon clear, smooth with the interface of described substrate, dislocation defects greatly improves, and has reduced deformation relaxation.
Brief description of the drawings
Figure 1 shows that the flow chart of the improvement method of the embedded germanium and silicon epitaxial dislocation defects of the present invention;
Figure 2 shows that the TEM figure of the PMOS device of preparing after the improvement method that adopts the embedded germanium and silicon epitaxial dislocation defects of the present invention;
The PMOS structural representation that causes strain gauge technique is inserted in the source/leakage of the silicon of germanium shown in Fig. 3;
Figure 4 shows that the defect TEM that the source/leakage of germanium silicon is inserted in epitaxy technique schemes.
Embodiment
By describe in detail the invention technology contents, structural feature, reached object and effect, below in conjunction with embodiment and coordinate accompanying drawing to be described in detail.
Refer to Fig. 1, Figure 1 shows that the flow chart of the improvement method of the embedded germanium and silicon epitaxial dislocation defects of the present invention.The improvement method of described embedded germanium and silicon epitaxial dislocation defects comprises the following steps,
Execution step S1: etching remove a described PMOS device 1 the first source electrode and first drain electrode;
Execution step S2: the brilliant transition zone 12 of deposit germanium silicon kind on described the first source electrode of removing in etching and the groove 11 of described the first drain electrode place, the germanium mass percentage content of the brilliant transition zone 12 of described germanium silicon kind is 5%～10%, and the thicknesses of layers of the brilliant transition zone 12 of described germanium silicon kind is 15～30nm;
Execution step S3: deposit germanium silicon source 13 and germanium silicon drain electrode 14 on the brilliant transition zone 12 of described germanium silicon kind.
For disclosing more intuitively the present invention's technical scheme, highlight the present invention's beneficial effect, now set forth in conjunction with specific embodiment.In described embodiment, described embedded germanium and silicon epitaxial dislocation defects numerical value is only experiment statistics data, has repeatability.Meanwhile, its dislocation defects numerical value exists can accept deviation, and the concrete numerical value in embodiment should not be considered as the restriction to the technical program.
Refer to Fig. 2, and in conjunction with consulting Fig. 1, Figure 2 shows that the TEM figure of a PMOS device of preparing after the improvement method that adopts the embedded germanium and silicon epitaxial dislocation defects of the present invention.The improvement method of embedded germanium and silicon epitaxial dislocation defects of the present invention comprises the following steps,
Execution step S1: etching remove a described PMOS device 1 the first source electrode and first drain electrode;
Execution step S2: the brilliant transition zone 12 of deposit germanium silicon kind on described the first source electrode of removing in etching and the groove 11 of described the first drain electrode place, the germanium mass percentage content of the brilliant transition zone 12 of described germanium silicon kind is 5%～10%, and the thicknesses of layers of the brilliant transition zone 12 of described germanium silicon kind is 15～30nm;
Execution step S3: deposit germanium silicon source 13 and germanium silicon drain electrode 14 on the brilliant transition zone 12 of described germanium silicon kind.
Please continue to refer to Fig. 2, and in conjunction with consulting table 1, table 1 is depicted as different Ge contents and the brilliant transition region thickness of different germanium silicon kind causes the statistical form of dislocation defects.In table 1, nonrestrictive enumerating, the mass percent that described A is characterized by germanium in the brilliant transition zone 12 of described SiGe kind is 5%～10%, the thickness range that described B is characterized by the brilliant transition zone 12 of described SiGe kind is 10～20nm.
Table 1 is depicted as the brilliant transition region thickness of different Ge contents and different germanium silicon kind causes the statistical form of dislocation defects
Hold intelligibly as those skilled in the art, adopt germanium silicon source 13 and the drain electrode 14 of germanium silicon of a described PMOS device 1 of preparing after the improvement method of the embedded germanium and silicon epitaxial dislocation defects of the present invention clear, smooth with the interface of described substrate 15, dislocation defects greatly improves, and has reduced deformation relaxation.
In sum, adopt the germanium silicon source of a described PMOS device of preparing after the improvement method of the embedded germanium and silicon epitaxial dislocation defects of the present invention and the drain electrode of germanium silicon clear, smooth with the interface of described substrate, dislocation defects greatly improves, and has reduced deformation relaxation.
Those skilled in the art all should be appreciated that, in the situation that not departing from the spirit or scope of the present invention, can carry out various modifications and variations to the present invention.Thereby, if when any amendment or modification fall in the protection range of appended claims and equivalent, think that the present invention contains these amendments and modification.
Claims (2)
1. an improvement method for embedded germanium and silicon epitaxial dislocation defects, is characterized in that, described method comprises:
Execution step S1: etching remove described PMOS device source electrode and drain electrode;
Execution step S2: the brilliant transition zone of deposit germanium silicon kind on the described source electrode of removing in etching and the groove of described drain electrode place, the germanium mass percentage content of the brilliant transition zone of described germanium silicon kind is 5%～10%, the thicknesses of layers of the brilliant transition zone of described germanium silicon kind is 15～30nm;
Execution step S3: deposit germanium silicon source and the drain electrode of germanium silicon on the brilliant transition zone of described germanium silicon kind.
2. the improvement method of embedded germanium and silicon epitaxial dislocation defects as claimed in claim 1, is characterized in that, the dislocation defects of the PMOS device of the improvement method manufacture by described embedded germanium and silicon epitaxial dislocation defects is less than or equal to 17%.
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104392996A (en) * | 2014-11-26 | 2015-03-04 | 上海华力微电子有限公司 | Intercalated germanium-silicon device and preparation method thereof |
| CN104821336A (en) * | 2015-04-20 | 2015-08-05 | 上海华力微电子有限公司 | Method and system used for using shape-preserving filling layer to improve surface uniformity of device |
| WO2023035269A1 (en) * | 2021-09-13 | 2023-03-16 | 上海集成电路制造创新中心有限公司 | Gate-all-around device and source/drain preparation method therefor, device preparation method and electronic device |
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| US20080054347A1 (en) * | 2006-09-06 | 2008-03-06 | Yin-Pin Wang | Composite stressors in MOS devices |
| US20120329229A1 (en) * | 2006-07-28 | 2012-12-27 | Fujitsu Semiconductor Limited | Semiconductor device and method of manufacturing the same |
| CN102856202A (en) * | 2011-06-29 | 2013-01-02 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor structure and forming method of semiconductor structure, p-channel metal oxide semiconductor (PMOS) transistor and forming method of PMOS transistor |
| CN102938377A (en) * | 2011-08-15 | 2013-02-20 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor structure, forming method of semiconductor structure, P-channel metal oxide semiconductor (PMOS) transistor and forming method of P-channel metal oxide semiconductor transistor |
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2014
- 2014-03-24 CN CN201410111325.7A patent/CN103943507A/en active Pending
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20120329229A1 (en) * | 2006-07-28 | 2012-12-27 | Fujitsu Semiconductor Limited | Semiconductor device and method of manufacturing the same |
| US20080054347A1 (en) * | 2006-09-06 | 2008-03-06 | Yin-Pin Wang | Composite stressors in MOS devices |
| CN102856202A (en) * | 2011-06-29 | 2013-01-02 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor structure and forming method of semiconductor structure, p-channel metal oxide semiconductor (PMOS) transistor and forming method of PMOS transistor |
| CN102938377A (en) * | 2011-08-15 | 2013-02-20 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor structure, forming method of semiconductor structure, P-channel metal oxide semiconductor (PMOS) transistor and forming method of P-channel metal oxide semiconductor transistor |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104392996A (en) * | 2014-11-26 | 2015-03-04 | 上海华力微电子有限公司 | Intercalated germanium-silicon device and preparation method thereof |
| CN104821336A (en) * | 2015-04-20 | 2015-08-05 | 上海华力微电子有限公司 | Method and system used for using shape-preserving filling layer to improve surface uniformity of device |
| CN104821336B (en) * | 2015-04-20 | 2017-12-12 | 上海华力微电子有限公司 | For improving the method and system of device surface uniformity using conformal packed layer |
| WO2023035269A1 (en) * | 2021-09-13 | 2023-03-16 | 上海集成电路制造创新中心有限公司 | Gate-all-around device and source/drain preparation method therefor, device preparation method and electronic device |
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Application publication date: 20140723 |