CN103929138A - Operation transconductance amplifier with low power losses, high gain and high slew rate - Google Patents

Abstract

Provided is an operation transconductance amplifier with low power losses, high gain and a high slew rate. On the basis of a basic structure, with an input stage, an output stage and a load capacitor CL, of the operation transconductance amplifier, a self-adaptive bias circuit, a current detecting circuit, a difference current reallocating circuit and a dynamic output drive and control circuit are additionally arranged, the self-adaptive bias circuit is controlled by difference input signals, the currents generated by the self-adaptive bias circuit are detected through the current detecting circuit, the small signal current difference of a load is increased through the difference current reallocating circuit to improve the equivalent transconductance of the operation transconductance amplifier, the detected currents are collected by the dynamic output drive and control circuit, the currents at the output end are controlled dynamically, the comprehensive improvement of the slew rate of the operation transconductance amplifier is achieved, the contradiction between the speed and the precision which cannot be regulated by an ordinary operation transconductance amplifier is overcome thoroughly, and the comprehensive improvement of a circuit on the static performance and the dynamic performance is achieved.

Description

The operation transconductance amplifier of the high Slew Rate of a kind of low-power consumption high-gain

Technical field

The present invention relates to operation transconductance amplifier, relate in particular to the operation transconductance amplifier of a kind of low-power consumption, high-gain, high Slew Rate, belong to simulation integrated computation trsanscondutance amplifier technical field.

Background technology

In recent years, the kind of electronic product is more and more, people are also more and more higher to the requirement of its performance, particularly semiconductor integrated circuit product, this just requires us aspect the circuit structure of the inside of this series products and device material, studying, operational amplification circuit is the most important thing of carrying out circuit studies, and operational amplifier is one of most important module of a lot of analog circuits, is widely used in the analog signal processing circuit such as analog to digital conversion circuit, filter.

In the application of collection, processing and the communication system of sound, vision signal, require that operation transconductance amplifier unity gain bandwidth is large, slew rate is high, settling time is short, and can under lower supply voltage, work.In recent years, along with the performance of Circuits System aft-end assembly significantly promotes, to occupy the operation transconductance amplifier of signal chains front end in order matching with it, to avoid tying down the overall performance of signal chains, more and more tend to the future development to high speed.Owing at a high speed comprising broadband and two principal characters of high pressure Slew Rate, thereby it is significant to be equally devoted to the research of high pressure Slew Rate operation transconductance amplifier.

The operation transconductance amplifier of prior art generally comprises input stage, output stage and load capacitance C _l, as shown in Figure 1, it comprises: PMOS pipe MT1, MT2, MT3, MT8, MT9, NMOS pipe MT4～MT7 and load capacitance C _l.Wherein, input stage comprises PMOS pipe MT1, MT2, MT3 and NMOS pipe MT4, MT5, and PMOS pipe MT1 and MT2 are difference input pipe, and PMOS pipe MT3 provide tail current for it, the external biasing of the grid Vb of MT3 pipe, the load pipe that NMOS pipe MT4 and MT5 are input stage.NMOS pipe MT6, MT7 and PMOS pipe MT8, MT9 form the output stage of operation transconductance amplifier, and PMOS pipe MT8 and MT9 form a current mirror, the output that the drain electrode of MT7 and MT9 is operation transconductance amplifier, and meet load capacitance C _l.

In order to ensure that circuit normally works, must configuration circuit in all PMOS pipe and NMOS pipes be operated in saturation region, its load capacitance C _lon current formula be:

$i_C=\frac{\mathrm{dQ}}{\mathrm{dt}}=C\frac{{\mathrm{dV}}_C}{\mathrm{dt}}$ Formula 1

In formula 1, Q represents the quantity of electric charge of capacitance stores, and t represents the time, V _crepresent the voltage at electric capacity two ends, i _cthe charging and discharging currents that represents electric capacity, C represents the capacitance of electric capacity.The voltage that can be known electric capacity two ends by formula 1 can not suddenly change, and discharging and recharging of electric capacity needs the time.

Slew rate is defined as:

$\mathrm{Slewrate}=\frac{{\mathrm{dV}}_C\left(t\right)}{\mathrm{dt}}=\frac{i_C}{C}$ Formula 2

By formula 2 can know slew rate and output current proportional, with the load capacitance value relation that is inversely proportional to, so in the situation that load is definite, output current is larger, slew rate is also just higher.

The electric current that flows through PMOS pipe MT9 suppose output current maximum in Fig. 1 time is I ₁, the electric current that flows through NMOS pipe MT7 is I ₂, output current I so _c=I ₁-I ₂if can ensure, under the prerequisite of the normal work of circuit, to reduce to greatest extent I as above ₂be worth, just can effectively increase the slew rate of operation transconductance amplifier.

Meanwhile,

$\mathrm{Slew}{\mathrm{rate}}_{\mathrm{int}}=\frac{{\mathrm{dV}}_C\left(t\right)}{\mathrm{dt}}{|}_{\max }=\frac{I_{\mathrm{SS}}}{C}=\frac{I_{\mathrm{SS}}}{g_{m1}}\frac{g_{m1}}{C}=\frac{I_{\mathrm{SS}}}{g_{m1}}\×\mathrm{GBW}={\mathrm{\Δ}}_1\×\mathrm{GBW}$ Formula 3

In formula 3, GBW represents that the unity gain bandwidth of operation transconductance amplifier is long-pending, I _sSrepresent tail current, g _m1represent the small-signal transconductance of PMOS pipe MT1, GBW is the amount of one group of contradiction with gain, and from formula 3, slew rate is directly proportional to GBW, so gain is also the amount of one group of contradiction with slew rate, what the maximum of slew rate represented is the minimum value of above-mentioned formula 2 and formula 3 results.

Circuit as shown in Figure 1, its gain is:

$\mathrm{Gain}=g_{m1}\×\frac{1}{g_{m4}}$ Formula 4

In formula 4, g _m1represent the small-signal transconductance of PMOS pipe M1, g _m4represent the small-signal admittance of NMOS pipe MT4.The size of gain can realize by cascade multistage operations trsanscondutance amplifier, but multistage operations trsanscondutance amplifier can be introduced extra zero level point, affect the stable type of system, therefore need to find a kind of method in single-stage level operation transconductance amplifier, just to improve fully the gain of operation transconductance amplifier.

Summary of the invention

For the voltage gain of prior art operation transconductance amplifier and the contradiction of Slew Rate and power consumption, the invention provides the operation transconductance amplifier of the high Slew Rate of a kind of low-power consumption high-gain, can ensure under the substantially constant prerequisite of other performances of circuit, improve gain and the slew rate of operation transconductance amplifier simultaneously, thereby improve the performance of operation transconductance amplifier, increased its scope of application.

The technical scheme that the present invention solves the problems of the technologies described above is as follows:

An operation transconductance amplifier for the high Slew Rate of low-power consumption high-gain, is characterized in that, is being provided with input stage, output stage and load capacitance C _loperation transconductance amplifier basic structure basis on, set up adaptive bias circuit, current detection circuit, difference current and redistribute circuit and dynamically export Drive and Control Circuit, the input of input stage, adaptive bias circuit and current detection circuit respectively with differential input signal V _in+and V _in-connect, the output of adaptive bias circuit connects respectively current detection circuit and input stage, the output of current detection circuit connects respectively difference current and redistributes circuit and dynamically export Drive and Control Circuit, input stage is connected output stage jointly with the output that difference current is redistributed circuit, and the output of output stage and dynamically output Drive and Control Circuit is jointly by load capacitance C _loutput V _out; Wherein:

Input stage comprises PMOS pipe M1, M2 and NMOS pipe M3, M4, the grid of PMOS pipe M1, M2 respectively with differential input signal V _in+and V _in-connect, the drain electrode of PMOS pipe M1, M2 is connected with the drain electrode of NMOS pipe M3, M4 respectively, grid and the equal short circuit that drains of NMOS pipe M3, M4, the source grounding of NMOS pipe M3, M4;

Output stage comprises PMOS pipe M9～M12, NMOS pipe M5～M8 and resistance R 1, the drain electrode of the grid of PMOS pipe M9 and the PMOS pipe gate interconnection of M10 one end of contact resistance R1 and NMOS pipe M7, the grid of PMOS pipe M11 is managed the gate interconnection of M12 and is connected the PMOS pipe drain electrode of M9 and the other end of resistance R 1 with PMOS, the source electrode of PMOS pipe M11, M12 all connects power vd D, the drain electrode of PMOS pipe M11, M12 connects respectively the source electrode of PMOS pipe M9, M10, the drain electrode of PMOS pipe M10 connects the drain electrode of NMOS pipe M8, and the gate interconnection of NMOS pipe M7, M8 also connects bias voltage V _b2, the source electrode of NMOS pipe M7, M8 connects respectively the drain electrode of NMOS pipe M5, M6, and the grid of NMOS pipe M5 connects the grid of NMOS pipe M4 in input stage, and the grid of NMOS pipe M6 connects the grid of NMOS pipe M3 in input stage, the source grounding of NMOS pipe M5, M6;

Adaptive bias circuit comprises PMOS pipe MB1～MB4, NMOS manages MB5, MB6, the source electrode of PMOS pipe MB1, MB2 all connects power vd D, the grid of PMOS pipe MB1 is connected with the drain electrode of PMOS pipe MB3, MB5, the grid of PMOS pipe MB2 is connected with the drain electrode of PMOS pipe MB4, MB6, the drain electrode of PMOS pipe MB1 manages with PMOS the source electrode that MB3 source electrode interconnects and is connected PMOS pipe M2 in input stage, the drain electrode of PMOS pipe MB2 manages with PMOS the source electrode that MB4 source electrode interconnects and is connected PMOS pipe M1 in input stage, and the grid of PMOS pipe MB3, MB4 connects respectively differential input signal V _in+, V _in-, the grid of NMOS pipe MB5, MB6 all connects bias voltage V _b1, the source grounding of NMOS pipe MB5, MB6;

Current detection circuit comprises PMOS pipe MS1, MS2, and the grid of PMOS pipe MS1, MS2 connects respectively differential input signal V _in+, V _in-, the source electrode of PMOS pipe MS1, MS2 is connected with the drain electrode of PMOS pipe MB2, MB1 in adaptive bias circuit respectively;

Difference current is redistributed circuit and is comprised NMOS pipe MC1, MC2, and NMOS manages MD1～MD4, and the grid of NMOS pipe MC1, MC2 all connects bias voltage V _b2in the drain electrode of NMOS pipe MC1 and current detection circuit, the grid of the drain electrode of PMOS pipe MS2 and NMOS pipe MD1, MD3 links together, in the drain electrode of NMOS pipe MC2 and current detection circuit, the grid of the drain electrode of PMOS pipe MS1 and NMOS pipe MD2, MD4 links together, the source electrode of NMOS pipe MC1, MC2 connects respectively the drain electrode of NMOS pipe MD1, MD2, the drain electrode of NMOS pipe MD3, MD4 connects respectively the drain electrode of PMOS pipe M1, M2 in input stage, the source grounding of NMOS pipe MD1, MD2, MD3, MD4;

Dynamically output Drive and Control Circuit comprises NMOS pipe M13～M16, PMOS pipe M17～M20 and NMOS pipe M21～M26, NMOS manages M13, the gate interconnection of M14 is also managed M13 with NMOS, M21, the drain electrode of M23, NMOS manages M13, M23, the grid of M24 and difference current are redistributed the grid of MD2 in circuit and are linked together, the drain and gate of the drain electrode of NMOS pipe M14 and NMOS pipe M15, the grid of NMOS pipe M16, the drain and gate of NMOS pipe M22, the grid of NMOS pipe M21 and difference current are redistributed the grid of MD1 in circuit and are linked together, NMOS manages M13, M14, M15, M16, M21, M22, M25, the source grounding of M26, the drain and gate of the source electrode of NMOS pipe M23 and NMOS pipe M26 links together, the source electrode of NMOS pipe M24 connects the drain electrode of NMOS pipe M25, the grid of NMOS pipe M25 connects the grid of NMOS pipe M6 in output stage, the drain electrode of the drain electrode of NMOS pipe M24 and PMOS pipe M18, load capacitance C _lanode and output stage in the drain electrode of NMOS pipe M8 link together and as output V _out, load capacitance C _lnegativing ending grounding, the gate interconnection of PMOS pipe M17, M18 also connects the drain electrode of PMOS pipe M17 and the drain electrode of NMOS pipe M16, the source electrode of PMOS pipe M17 connects grid and the drain electrode of PMOS pipe M20, the source electrode of PMOS pipe M18 connects the drain electrode of PMOS pipe M19, the grid of PMOS pipe M19 connects the grid of PMOS pipe M11 in output stage, and the source electrode of PMOS pipe M19, M20 connects power vd D,

In foregoing circuit, adaptive bias circuit is according to the difference of input difference input signal, the adaptive bias of the different sizes of output, this electric current flow through input stage and current detection circuit, after the electric current of current detection circuit collection adaptive bias circuit output, split into two groups of difference currents, offering respectively difference current redistributes circuit and dynamically exports Drive and Control Circuit, difference current is redistributed circuit and is redistributed in proportion rear output for one group of difference current of current detection circuit output, in shunting input stage, flow through the difference current of load, input stage two-pass DINSAR electric current is numerically separated more, to increase the difference of difference current, thereby increase the equivalent transconductance of input stage, improve operation transconductance amplifier gain, output stage is amplified after copying the two-pass DINSAR current signal after separated again, further improve gain, dynamically output Drive and Control Circuit gathers another group difference current of current detection circuit output, through current ratio after output, draw upper and lower two of control output end, fill with current source, with the positive and negative Slew Rate under improving respectively dynamically.

Compared with prior art, advantage of the present invention and beneficial effect are:

(1) design of the adaptive bias circuit of uniqueness of the present invention not only effectively reduces the power consumption of operation transconductance amplifier, and provides precondition for the control driving with dynamic output of redistributing of difference current.

(2) the present invention adopts the way that difference current is redistributed, and effectively improves the equivalent transconductance of operation transconductance amplifier, thereby improves the gain of operation transconductance amplifier.

(3) the present invention adopts dynamic output Drive and Control Circuit, gathers and analyze the current signal that current detection circuit detects, with improve output extra draw, fill with electric current, thereby improve the positive and negative Slew Rate under operation transconductance amplifier large-signal.

(4) the present invention not only adopts the method for redistributing difference current, by configuration and the nonlinear effect of linear transfer breadth length ratio, effectively improve operation transconductance amplifier gain, also utilize the difference channel of redistributing through the current subtraction device in output Drive and Control Circuit, driver output, greatly improved the slew rate of operation transconductance amplifier, under realization static state, ac small signal and dynamic large-signal, circuit performance improves comprehensively.

(5) the present invention by the compatibility to current mirror nonlinear effect and the control of linear transfer ratio and integrated, redistributes the electric current in load, the coordinating and unifying of circuit speed and precision under acquisition power constraints.

Brief description of the drawings

Fig. 1 is a kind of schematic diagram of prior art operation transconductance amplifier;

Fig. 2 is the schematic diagram of the high Slew Rate high gain operational of the low-power consumption trsanscondutance amplifier that proposes of the present invention;

Fig. 3 is the specific works flow process figure of Fig. 2;

Fig. 4 is the concrete implementing circuit figure of Fig. 2;

Fig. 5 be Zhong Xian of the present invention ?nonlinear adaptive current mirroring circuit schematic diagram;

Fig. 6 is current subtraction device circuit theory diagrams in the present invention.

Embodiment

Below in conjunction with accompanying drawing, principle of the present invention and feature are described, the example of lifting, only for explaining the present invention, is not intended to limit scope of the present invention.

As Fig. 2, the present invention is being provided with input stage, output stage and load capacitance C _loperation transconductance amplifier basic structure basis on, set up adaptive bias circuit, current detection circuit, difference current and redistribute circuit and dynamically export Drive and Control Circuit, the input of input stage, adaptive bias circuit and current detection circuit respectively with differential input signal V _in+and V _in-connect, the output of adaptive bias circuit connects respectively current detection circuit and input stage, the output of current detection circuit connects respectively difference current and redistributes circuit and dynamically export Drive and Control Circuit, input stage is connected output stage jointly with the output that difference current is redistributed circuit, and the output of output stage and dynamically output Drive and Control Circuit is jointly by load capacitance C _loutput V _out.In figure, I ₁and I ₂the electric current that flows through operation transconductance amplifier input stage, I _s1and I _s2the output current that current detecting gathers, I _s1and I _s2cross complementary output, I _s1and I _s2after redistributing in proportion, be output as-I _d1with-I _d2, shunting I ₁and I ₂.

As Fig. 4, operation transconductance amplifier input stage comprises PMOS pipe M1, M2 and NMOS pipe M3, M4, and PMOS pipe M1, M2 form difference input pipe, its grid respectively with differential input signal V _in+and V _in-connect, the source electrode of PMOS pipe M1, M2 is connected with the drain electrode of PMOS pipe MB2, MB1 in adaptive bias circuit respectively, the drain electrode of PMOS pipe M1, M2 is connected with the drain electrode of NMOS pipe M3, M4 respectively, grid and the equal short circuit that drains of NMOS pipe M3, M4, the source grounding of NMOS pipe M3, M4.

Operation transconductance amplifier output stage comprises PMOS pipe M9～M12, NMOS pipe M5～M8 and resistance R 1, the drain electrode of the grid of PMOS pipe M9 and the PMOS pipe gate interconnection of M10 one end of contact resistance R1 and NMOS pipe M7, the grid of PMOS pipe M11 is managed the gate interconnection of M12 and is connected the PMOS pipe drain electrode of M9 and the other end of resistance R 1 with PMOS, PMOS manages M11, the source electrode of M12 all connects power vd D, PMOS manages M11, the drain electrode of M12 connects respectively PMOS pipe M9, the source electrode of M10, the drain electrode of PMOS pipe M10 connects the drain electrode of NMOS pipe M8, NMOS manages M7, the gate interconnection of M8 also connects bias voltage V _b2, the source electrode of NMOS pipe M7, M8 connects respectively the drain electrode of NMOS pipe M5, M6, and the grid of NMOS pipe M5 connects the grid of NMOS pipe M4 in input stage, and the grid of NMOS pipe M6 connects the grid of NMOS pipe M3 in input stage, the source grounding of NMOS pipe M5, M6.

Adaptive bias circuit comprises PMOS pipe MB1～MB4, NMOS manages MB5, MB6, the source electrode of PMOS pipe MB1, MB2 all connects power vd D, the grid of PMOS pipe MB1 is connected with the drain electrode of PMOS pipe MB3, MB5, the grid of PMOS pipe MB2 is connected with the drain electrode of PMOS pipe MB4, MB6, the drain electrode of PMOS pipe MB1 manages with PMOS the source electrode that MB3 source electrode interconnects and is connected PMOS pipe M2 in input stage, the drain electrode of PMOS pipe MB2 manages with PMOS the source electrode that MB4 source electrode interconnects and is connected PMOS pipe M1 in input stage, and the grid of PMOS pipe MB3, MB4 connects respectively differential input signal V _in+, V _in-, the grid of NMOS pipe MB5, MB6 all connects bias voltage V _b1, the source grounding of NMOS pipe MB5, MB6.Adaptive bias circuit provides self-adaptive current for operation transconductance amplifier input stage, redistributing and dynamically export Drive and Control Circuit collection comparison electric current for difference current creates conditions, according to the variation of circuit differential input signal, dynamically change the size of tail current, work as V _in+>V _in-time, the electric current in PMOS pipe MB3 reduces, and the electric current in corresponding PMOS pipe MB4 increases, and this just causes varying in size of adaptive bias output two-way current value: I _b1<I _b2, this just provides prerequisite for follow-up difference current is redistributed and dynamically export Drive and Control Circuit collection current signal, has effectively reduced the power consumption of operation transconductance amplifier.

Current detection circuit comprises PMOS pipe MS1, MS2, and the grid of PMOS pipe MS1, MS2 connects respectively differential input signal V _in+, V _in-, the source electrode of PMOS pipe MS1, MS2 is connected with the drain electrode of PMOS pipe MB2, MB1 in adaptive bias circuit respectively, and the drain electrode of PMOS pipe MS1, MS2 is redistributed with difference current the drain electrode that NMOS in circuit manages MC1, MC2 respectively and is connected.Current formula in metal-oxide-semiconductor is:

$I_D=\frac{\mathrm{\&beta;}}{2}{\left(\right|V_{\mathrm{GS}}|-|V_{\mathrm{TH}}\left|\right)}^2$ Formula 5

From formula 5, flow through the electric current I in PMOS pipe MS1 _s1with the electric current I flowing through in PMOS pipe M1 ₁equate, in like manner flow through the electric current I in PMOS pipe MS2 _s2with the electric current I flowing through in PMOS pipe M2 ₂equate.I _s1and I _s2after redistributing in proportion, be output as-I _d1with-I _d2, shunting I ₁and I ₂.

Difference current is redistributed circuit and is comprised NMOS pipe MC1, MC2, and NMOS manages MD1～MD4, and the grid of NMOS pipe MC1, MC2 all connects bias voltage V _b2in the drain electrode of NMOS pipe MC1 and current detection circuit, the grid of the drain electrode of PMOS pipe MS2 and NMOS pipe MD1, MD3 links together, in the drain electrode of NMOS pipe MC2 and current detection circuit, the grid of the drain electrode of PMOS pipe MS1 and NMOS pipe MD2, MD4 links together, the source electrode of NMOS pipe MC1, MC2 connects respectively the drain electrode of NMOS pipe MD1, MD2, the drain electrode of NMOS pipe MD3, MD4 connects respectively the drain electrode of PMOS pipe M1, M2 in input stage, the source grounding of NMOS pipe MD1, MD2, MD3, MD4.Wherein NMOS pipe MC1, MD1, MD3 form one group of linearity-nonlinear adaptive current mirror, and NMOS pipe MC2, MD2, MD4 form another group linearity-nonlinear adaptive current mirror.Difference current is redistributed circuit and is produced two-way output current-I _d1with-I _d2, shunting operation transconductance amplifier input stage flows into the electric current of load originally, and increasing in operation transconductance amplifier input stage the difference of current flowing in the load of both sides increases the equivalent transconductance of operation transconductance amplifier input stage, improves operation transconductance amplifier gain.

Dynamically output Drive and Control Circuit comprises NMOS pipe M13～M16, PMOS pipe M17～M20 and NMOS pipe M21～M26, wherein NMOS pipe M13 to M16 forms a current subtraction device, and NMOS pipe M21 to M24 forms another current subtraction device, and PMOS pipe M17, M18 form a linear current mirror.NMOS manages M13, the gate interconnection of M14 is also managed M13 with NMOS, M21, the drain electrode of M23, NMOS manages M13, M23, the grid of M24 and difference current are redistributed the grid of MD2 in circuit and are linked together, the drain and gate of the drain electrode of NMOS pipe M14 and NMOS pipe M15, the grid of NMOS pipe M16, the drain and gate of NMOS pipe M22, the grid of NMOS pipe M21 and difference current are redistributed the grid of MD1 in circuit and are linked together, NMOS manages M13, M14, M15, M16, M21, M22, M25, the source grounding of M26, the drain and gate of the source electrode of NMOS pipe M23 and NMOS pipe M26 links together, the source electrode of NMOS pipe M24 connects the drain electrode of NMOS pipe M25, the grid of NMOS pipe M25 connects the grid of NMOS pipe M6 in output stage, the drain electrode of the drain electrode of NMOS pipe M24 and PMOS pipe M18, load capacitance C _lanode and output stage in the drain electrode of NMOS pipe M8 link together and as output V _out, load capacitance C _lnegativing ending grounding, the gate interconnection of PMOS pipe M17, M18 also connects the drain electrode of PMOS pipe M17 and the drain electrode of NMOS pipe M16, the source electrode of PMOS pipe M17 connects grid and the drain electrode of PMOS pipe M20, the source electrode of PMOS pipe M18 connects the drain electrode of PMOS pipe M19, the grid of PMOS pipe M19 connects the grid of PMOS pipe M11 in output stage, and the source electrode of PMOS pipe M19, M20 connects power vd D.Dynamically output Drive and Control Circuit, gather in proportion the two-pass DINSAR electric current of current detection circuit output, and after this two-pass DINSAR electric current is compared, image copying by a certain percentage, with the size of control output end charge or discharge electric current, increase substantially the slew rate of operation transconductance amplifier under large-signal.Dynamically in output Drive and Control Circuit, comprise the PMOS pipe being connected with power supply, and the NMOS being connected to the ground pipe, two kinds of pipes are according to the different timesharing conductings of input signal, improve the extra electric current that draws, fills with to load capacitance, increase the Slew Rate of operation transconductance amplifier.

In foregoing circuit, adaptive bias circuit, difference current are redistributed circuit and are dynamically exported Drive and Control Circuit three close association, indispensable, jointly realize the coordinating and unifying of operation transconductance amplifier accuracy and runtime.

As shown in Figure 3: after switching on power, adaptive circuit can, according to the difference of differential input signal, be exported different adaptive bias.Work as V _in+=V _in-time, two-way bias current is identical, and the result of current detecting outputs to difference current redistributes the electric current I of circuit _c1=I _c2so after difference current is redistributed, the load small-signal current of operation transconductance amplifier is poor still constant, so operation transconductance amplifier is output as zero.In dynamically exporting Drive and Control Circuit, the difference of two-way electric current is also zero equally, dynamically exports PMOS pipe in Drive and Control Circuit and turn-offs with NMOS pipe simultaneously, and both all do not contribute output signal, are output as zero.

Work as V _in+>V _in-time, the result of current detecting outputs to difference current redistributes the electric current I of circuit _c1>I _c2, and two-way electric current I in operation transconductance amplifier input stage ₁<I ₂, in the time redistributing, I _s1and I _s2after redistributing in proportion, be output as-I _d1with-I _d2, shunting I ₁and I ₂this will cause less small-signal current in the load of operation transconductance amplifier input stage to deduct a larger electric current, larger small-signal current deducts a less electric current, like this through after redistributing, the small-signal current numerical difference of operation transconductance amplifier input stage is further expanded, be conducive to increase the equivalent small-signal transconductance of operation transconductance amplifier input stage, to reach the object that increases operation transconductance amplifier gain.Meanwhile, I _s1<I _s2the input current I of Drive and Control Circuit will be caused dynamically exporting ₅>I ₆, causing PMOS pipe conducting in dynamic output Drive and Control Circuit, NMOS manages cut-off, increases the charging current of load capacitance, for output signal provides a larger positive Slew Rate, and input signal V _in+>V _in-trend larger, positive Slew Rate improves more obviously;

Work as V _in+<V _in-time, the result of current detecting outputs to difference current redistributes the electric current I of circuit _c1<I _c2, and two-way electric current I in operation transconductance amplifier input stage ₁>I ₂, in the time redistributing, I _s1and I _s2after redistributing in proportion, be output as-I _d1with-I _d2, shunting I ₁and I ₂this also will cause less small-signal current in the load of operation transconductance amplifier input stage to deduct a larger electric current, larger small-signal current deducts a less electric current, like this through after redistributing, the poor quilt of small-signal current of operation transconductance amplifier input stage further expands, be conducive to increase the equivalent small-signal transconductance of operation transconductance amplifier input stage, to reach the object that increases operation transconductance amplifier gain.Meanwhile, I _s1>I _s2the input current I of Drive and Control Circuit will be caused dynamically exporting ₅<I ₆, causing NMOS pipe conducting in dynamic output Drive and Control Circuit, PMOS manages cut-off, increases the discharging current of load capacitance, for output signal provides a larger negative Slew Rate, and input signal V _in+<V _in-trend larger, negative Slew Rate improves more obviously.

The structure that difference current is redistributed the linearity-nonlinear adaptive current mirror in circuit as shown in Figure 5, at bias voltage V _b2and electric current I _c2all, under fixing condition, reduce to have the MD2 of same size and the W/L of MC2 two pipes, the mode of operation that makes current mirror is transformed to non-linear nature by linear behavio(u)r, on the contrary, increase W/L the mode of operation that makes current mirror is transformed to linear behavio(u)r by non-linear nature; By suitable W/L design, can as required this current mirror be set in to required linearity or nonlinear operation pattern.Differential pair is inputted driving current constant and bias voltage V to differential load under static conditions _b2constant, utilizing this point characteristic is the pattern that the adjusting of W/L is arranged on load current mirror under static conditions.

At bias voltage V _b2under the condition of all fixing with input pipe device size W/L, increase input current I _c2the mode of operation that makes current mirror is transformed to non-linear nature by linear behavio(u)r, on the contrary, reduce input current I _c2the mode of operation that makes current mirror is transformed to linear behavio(u)r by non-linear nature; Therefore,, by the variation of input current, can make current mirror realize the conversion between different transport properties.Differential pair changes to differential load input drive current under the little condition of ac small signal, but V _b2constant, W/L no longer changes after static schema is set, and utilizing this point characteristic is the dynamic self-adapting adjusting of variation realization mode of operation of load current mirror under ac small signal condition of input current.

The configurable current mirror of differential pair load model, under low static power consumption requires, quiescent biasing is in the non-linear critical working point of linearity or be slightly partial to nonlinear mode of operation, under difference condition of small signal, a pair of current mirror of differential load will be respectively to linear and non-linear two mode deflections, enter after large-signal input state, one of them load current mirror can be transferred to nonlinear operation pattern conventionally.

Suppose that non-linear current mirror NMOS pipe MD1 and the ratio of the grid width of NMOS pipe MD3 are 1:B, NMOS pipe MD2 is 1:B with the ratio of the grid breadth length ratio of NMOS pipe MD4, supposes V _in+>V _in-, self-adaptive current I so _b1<I _b2, can obtain difference current and redistribute the relation of the electric current in circuit: I _c1>I _c2, I _d1=BI _c1, I _d2=BI _c2, I ₁=1/2I _b1<I2=1/2I _b2so the electric current that just can obtain flowing through in load M3 is:

$I_3=\frac{1}{2}{I}_{B1}-B\&times;I_{C1}$ Formula 6

The electric current flowing through in load M4 is:

$I_4=\frac{1}{2}{I}_{B2}-B\&times;I_{C2}$ Formula 7

Tradition Differential OTA load current poor be I ₂-I ₁, the difference between current that introducing difference current is redistributed in circuit back loading M3 and M4 is:

I ₄-I ₃=I ₂-B × I _c2-(I ₁-B × I _c1)=I ₂-I ₁+ B × (I _c1-I _c2) formula 8

From formula 8, the difference between current in load further expands, and in load, the variation of difference between current becomes large by the equivalent transconductance of the operation transconductance amplifier input stage that causes load, and the mutual conductance of supposing operation transconductance amplifier input stage is g _m1, the admittance of NMOS pipe MD3 is g _md3, introduce electric current and redistribute the equivalent transconductance of rear operation transconductance amplifier input stage and be:

$G_m=\frac{i_o}{v_i}\&ap;\frac{{2g}_{m1}}{g_{m3}-g_{\mathrm{mC}3}}{g}_{m3}=\frac{{2g}_{m1}}{1-\frac{g_{\mathrm{md}3}}{g_{m3}}}=\frac{{2g}_{m1}}{1-\mathrm{\&eta;}}$ Formula 9

In formula 9, $\mathrm{\&eta;}=\frac{g_{\mathrm{md}3}}{g_{m3}},0<\mathrm{\&eta;}<1.$

From formula 9, the equivalent transconductance of operation transconductance amplifier input stage is improved on original basis, can, by changing the proportionate relationship of W/L, change the equivalent transconductance of operation transconductance amplifier.

Dynamically output Drive and Control Circuit comprises two current subtraction device circuit, the principle of current subtraction device as shown in Figure 6: each branch current is respectively I _m1to I _m4, work as I _m1>=I _m2time, M15 pipe is subject to clamping down on of M14 pipe, due to the conducting of M14 pipe, makes the namely grid voltage decline of M15 pipe of drain voltage of M14 pipe, cause the gate source voltage of M15 pipe cannot reach cut-in voltage and cause the cut-off of M15 pipe, so the output current I of the current mirror of M15, M16 composition _m4=0, work as I _m1<I _m2time, in the current mirror of M13 and M14 composition, M14 copies the electric current I in M13 _m1, cause flowing through the electric current I in M15 _m3=I _m2-I _m1, M16 copies the electric current in M15, I in proportion _m4=M (I _m2-I _m1).So I _m2with I _m1difference larger, output current I _m4larger.Two current subtraction device structures, mutual symmetry connects, and in the current mirror that in Fig. 4, M15, M16 form, the ratio of the grid breadth length ratio of NMOS pipe M15, M16 is 1:M, in the current mirror being made up of NMOS pipe M23, M24, the ratio of the grid breadth length ratio of NMOS pipe M23, M24 is 1:M.Suppose to flow through two electric currents in current subtraction device and be respectively I ₅and I ₆, the electric current flowing through in M15 and M23 is respectively I ₇and I ₈, work as so I ₅>I ₆time, the electric current in M16 is MI ₇meanwhile, electric current in M24 is zero, it is the cut-off of M24 pipe, along with input signal continues to become large, the electric current in M16 copies to output through the current mirror of M17 and M18 composition, according to input signal so, for load current provides extra charging current, increase the rising Slew Rate of operation transconductance amplifier in proportion; Together should I ₅<I ₆time, the electric current in M24 is MI ₈, meanwhile, the electric current in M16 is zero, i.e. M16 pipe cut-off, and along with input signal continues to become large, the electric current in M24, according to input signal, in proportion for load current provides extra discharging current, increases the decline Slew Rate of operation transconductance amplifier so.Both very perfectly combinations, have effectively solved the low Slew Rate problem of conventional operation trsanscondutance amplifier, and charging current and discharging current are risen to maximum, effectively raise the Slew Rate of operation transconductance amplifier.

The foregoing is only preferred embodiment of the present invention, be not limited to the present invention, for a person skilled in the art, the present invention can have various modifications and variations.Within the spirit and principles in the present invention all, any amendment of doing, be equal to replacement, improvement etc., within all should being included in protection scope of the present invention.

Claims (1)

1. an operation transconductance amplifier for the high Slew Rate of low-power consumption high-gain, is characterized in that, is being provided with input stage, output stage and load capacitance C _loperation transconductance amplifier basic structure basis on, set up adaptive bias circuit, current detection circuit, difference current and redistribute circuit and dynamically export Drive and Control Circuit, the input of input stage, adaptive bias circuit and current detection circuit respectively with differential input signal V _in+and V _in-connect, the output of adaptive bias circuit connects respectively current detection circuit and input stage, the output of current detection circuit connects respectively difference current and redistributes circuit and dynamically export Drive and Control Circuit, input stage is connected output stage jointly with the output that difference current is redistributed circuit, and the output of output stage and dynamically output Drive and Control Circuit is jointly by load capacitance C _loutput V _out; Wherein:

Input stage comprises PMOS pipe M1, M2 and NMOS pipe M3, M4, the grid of PMOS pipe M1, M2 respectively with differential input signal V _in+and V _in-connect, the drain electrode of PMOS pipe M1, M2 is connected with the drain electrode of NMOS pipe M3, M4 respectively, grid and the equal short circuit that drains of NMOS pipe M3, M4, the source grounding of NMOS pipe M3, M4;

Output stage comprises PMOS pipe M9～M12, NMOS pipe M5～M8 and resistance R 1, the drain electrode of the grid of PMOS pipe M9 and the PMOS pipe gate interconnection of M10 one end of contact resistance R1 and NMOS pipe M7, the grid of PMOS pipe M11 is managed the gate interconnection of M12 and is connected the PMOS pipe drain electrode of M9 and the other end of resistance R 1 with PMOS, the source electrode of PMOS pipe M11, M12 all connects power vd D, the drain electrode of PMOS pipe M11, M12 connects respectively the source electrode of PMOS pipe M9, M10, the drain electrode of PMOS pipe M10 connects the drain electrode of NMOS pipe M8, and the gate interconnection of NMOS pipe M7, M8 also connects bias voltage V _b2, the source electrode of NMOS pipe M7, M8 connects respectively the drain electrode of NMOS pipe M5, M6, and the grid of NMOS pipe M5 connects the grid of NMOS pipe M4 in input stage, and the grid of NMOS pipe M6 connects the grid of NMOS pipe M3 in input stage, the source grounding of NMOS pipe M5, M6;

Adaptive bias circuit comprises PMOS pipe MB1～MB4, NMOS manages MB5, MB6, the source electrode of PMOS pipe MB1, MB2 all connects power vd D, the grid of PMOS pipe MB1 is connected with the drain electrode of PMOS pipe MB3, MB5, the grid of PMOS pipe MB2 is connected with the drain electrode of PMOS pipe MB4, MB6, the drain electrode of PMOS pipe MB1 manages with PMOS the source electrode that MB3 source electrode interconnects and is connected PMOS pipe M2 in input stage, the drain electrode of PMOS pipe MB2 manages with PMOS the source electrode that MB4 source electrode interconnects and is connected PMOS pipe M1 in input stage, and the grid of PMOS pipe MB3, MB4 connects respectively differential input signal V _in+, V _in-, the grid of NMOS pipe MB5, MB6 all connects bias voltage V _b1, the source grounding of NMOS pipe MB5, MB6;

Current detection circuit comprises PMOS pipe MS1, MS2, and the grid of PMOS pipe MS1, MS2 connects respectively differential input signal V _in+, V _in-, the source electrode of PMOS pipe MS1, MS2 is connected with the drain electrode of PMOS pipe MB2, MB1 in adaptive bias circuit respectively;

Difference current is redistributed circuit and is comprised NMOS pipe MC1, MC2, and NMOS manages MD1～MD4, and the grid of NMOS pipe MC1, MC2 all connects bias voltage V _b2in the drain electrode of NMOS pipe MC1 and current detection circuit, the grid of the drain electrode of PMOS pipe MS2 and NMOS pipe MD1, MD3 links together, in the drain electrode of NMOS pipe MC2 and current detection circuit, the grid of the drain electrode of PMOS pipe MS1 and NMOS pipe MD2, MD4 links together, the source electrode of NMOS pipe MC1, MC2 connects respectively the drain electrode of NMOS pipe MD1, MD2, the drain electrode of NMOS pipe MD3, MD4 connects respectively the drain electrode of PMOS pipe M1, M2 in input stage, the source grounding of NMOS pipe MD1, MD2, MD3, MD4;

Dynamically output Drive and Control Circuit comprises NMOS pipe M13～M16, PMOS pipe M17～M20 and NMOS pipe M21～M26, NMOS manages M13, the gate interconnection of M14 is also managed M13 with NMOS, M21, the drain electrode of M23, NMOS manages M13, M23, the grid of M24 and difference current are redistributed the grid of MD2 in circuit and are linked together, the drain and gate of the drain electrode of NMOS pipe M14 and NMOS pipe M15, the grid of NMOS pipe M16, the drain and gate of NMOS pipe M22, the grid of NMOS pipe M21 and difference current are redistributed the grid of MD1 in circuit and are linked together, NMOS manages M13, M14, M15, M16, M21, M22, M25, the source grounding of M26, the drain and gate of the source electrode of NMOS pipe M23 and NMOS pipe M26 links together, the source electrode of NMOS pipe M24 connects the drain electrode of NMOS pipe M25, the grid of NMOS pipe M25 connects the grid of NMOS pipe M6 in output stage, the drain electrode of the drain electrode of NMOS pipe M24 and PMOS pipe M18, load capacitance C _lanode and output stage in the drain electrode of NMOS pipe M8 link together and as output V _out, load capacitance C _lnegativing ending grounding, the gate interconnection of PMOS pipe M17, M18 also connects the drain electrode of PMOS pipe M17 and the drain electrode of NMOS pipe M16, the source electrode of PMOS pipe M17 connects grid and the drain electrode of PMOS pipe M20, the source electrode of PMOS pipe M18 connects the drain electrode of PMOS pipe M19, the grid of PMOS pipe M19 connects the grid of PMOS pipe M11 in output stage, and the source electrode of PMOS pipe M19, M20 connects power vd D,

In foregoing circuit, adaptive bias circuit is according to the difference of input difference input signal, the adaptive bias of the different sizes of output, this electric current flow through input stage and current detection circuit, after the electric current of current detection circuit collection adaptive bias circuit output, split into two groups of difference currents, offering respectively difference current redistributes circuit and dynamically exports Drive and Control Circuit, difference current is redistributed circuit and is redistributed in proportion rear output for one group of difference current of current detection circuit output, in shunting input stage, flow through the difference current of load, input stage two-pass DINSAR electric current is numerically separated more, to increase the difference of difference current, thereby increase the equivalent transconductance of input stage, improve operation transconductance amplifier gain, output stage is amplified after copying the two-pass DINSAR current signal after separated again, further improve gain, dynamically output Drive and Control Circuit gathers another group difference current of current detection circuit output, through current ratio after output, draw upper and lower two of control output end, fill with current source, with the positive and negative Slew Rate under improving respectively dynamically.