CN103928394B - The preparation method of metal interconnect structure - Google Patents
The preparation method of metal interconnect structure Download PDFInfo
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- CN103928394B CN103928394B CN201310009778.4A CN201310009778A CN103928394B CN 103928394 B CN103928394 B CN 103928394B CN 201310009778 A CN201310009778 A CN 201310009778A CN 103928394 B CN103928394 B CN 103928394B
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
- H01L21/76879—Filling of holes, grooves or trenches, e.g. vias, with conductive material by selective deposition of conductive material in the vias, e.g. selective C.V.D. on semiconductor material, plating
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76886—Modifying permanently or temporarily the pattern or the conductivity of conductive members, e.g. formation of alloys, reduction of contact resistances
- H01L21/76892—Modifying permanently or temporarily the pattern or the conductivity of conductive members, e.g. formation of alloys, reduction of contact resistances modifying the pattern
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Abstract
A kind of preparation method of metal interconnect structure, be different from existing pair of composition scheme, the present invention proposes first in dielectric sacrifice layer, to form one group of groove with traditional single Damascus technics, and insert metal to form the first set metal pattern of metal interconnect structure, then remove this dielectric sacrifice layer, taking this layer of metal of first set metal pattern as core around it and between form the cover layer that thickness can accurately be controlled, form side wall by eat-backing this cover layer, the gap of filling between this side wall forms the second cover metal pattern, in above-mentioned etch back process, the gap depth between side wall is deepened, this intensification processing can make that follow-up to insert wherein the second cover metal pattern forming consistent with the first set metal pattern degree of depth of formation before, so complete two composition techniques of metal interconnect structure. because the second cover metal pattern is inserted between first set metal pattern, realize the object that pattern density is doubled. above-mentioned preparation method technique is simple, and metal pattern shape is easy to control.
Description
Technical field
The present invention relates to field of semiconductor manufacture, relate in particular to a kind of preparation method of metal interconnect structure.
Background technology
At present, along with the development that large scale integrated circuit is manufactured, in industry, more and more wish to form highThe semiconductor devices of integrated level. The semiconductor devices of this high integration, for example dynamic random access memoryEtc. (DRAM) comprise a large amount of meticulous patterns, for example metal interconnection pattern, these patterns are by lightCarve, etching procedure by mask plate design transfer to forming on semiconductor layer. The operation of photoetching is generally:Photoresist (PR) is coated on the destination layer that needs patterning, then, carries out exposure process and change partThe solubility of the photoresist in region, carries out afterwards developing procedure and forms the photoetching agent pattern that exposes destination layer,Above-mentioned operation has completed mask plate design transfer to photoresist. Carry out taking this photoetching agent pattern as maskEtching procedure is to be transferred to photoetching agent pattern on semiconductor layer. But, in exposure process because diffraction is existingThe existence of elephant, can not unrestrictedly improve critical size, becomes the bottleneck that integrated level further improves.
In order to address the above problem, the two patterning process (Self-alignedDouble of autoregistration in industry, are there arePtterning, SaDP). In general, two compositions comprise employing two cover mask plates, i.e. exposure-etching-expose to the sunTwo composition schemes of light-etching (Litho-Etch-Litho-Etch), or adopt a set of mask plate, cover with thisThe side wall (spacer) of the pattern that lamina membranacea forms carries out the side of pair compositions for what mask carried out etching based on side wallCase.
More double-pattern metallization processes please refer to the United States Patent (USP) literary composition that publication number is US2007/0148968A1Offer.
But the technique that mask plate is overlapped in above-mentioned employing two is comparatively complicated, adopts a set of mask plate to relate to rightThe etching technics of metal, the more difficult control of the shape of metal pattern in this etching process.
In view of this, the present invention proposes a kind of preparation method of new metal interconnect structure, above-mentioned to solveProblem.
Summary of the invention
The object that the present invention realizes is the preparation method that proposes a kind of new metal interconnect structure, its technique letterSingle, metal pattern shape is easy to control.
For achieving the above object, the invention provides a kind of preparation method of metal interconnect structure, comprising:
Semiconductor substrate is provided, in described Semiconductor substrate, there is successively anterior layer dielectric layer, quarter from bottom to topErosion stop layer, dielectric sacrifice layer;
In described dielectric sacrifice layer, etching forms multiple grooves;
In described groove, inserting metal planarization, to remove excess metal outside groove metal interconnected to formThe first set metal pattern of structure;
Remove dielectric sacrifice layer, retain the first set metal pattern of described metal interconnect structure;
Around the first set metal pattern of described metal interconnect structure and between form cover layer;
Eat-back described cover layer and form side wall, in the gap of described side wall, insert metal planarization and removeExcess metal outside described gap with form metal interconnect structure second cover metal pattern, described in eat-back rightInterstitial treatment between side wall can make the second cover metal pattern and the first set metal pattern degree of depth one forming beforeCause.
Alternatively, described anterior layer dielectric layer has target electrical connection region, the metal of inserting in groove orThe metal of inserting in gap is electrically connected joint area with described target.
Alternatively, described target electrical connection region is conductive plunger.
Alternatively, in described gap, insert metal planarization and remove the excess metal step outside described gapAfter rapid, also carry out:
Remove side wall and retain the metal pattern of metal interconnect structure;
Between described metal pattern, insert low K or ultralow K material to form low K or ultralow K dielectric layerMetal interconnect structure.
Alternatively, in described gap, insert metal planarization and remove the excess metal step outside described gapAfter rapid, also carry out:
Remove side wall and retain the metal pattern of metal interconnect structure;
On described metal pattern, deposit cap rock is to form the metal interconnect structure with air-gap.
Alternatively, described cap rock is the etch stop layer of rear layer metal interconnect structure.
Alternatively, the first set metal pattern of described metal interconnect structure around and between cover layer be logicalCross atomic layer deposition method form.
Alternatively, the material of described side wall is silica, silicon nitride, silicon oxynitride, carborundum, nitrogenAny combination of one or several in carborundum.
Alternatively, the material of described dielectric sacrifice layer be low K or ultralow K material dielectric layer, silica,One or several in organic material, silicon nitride, silicon oxynitride, carborundum, fire sand arbitrarilyCombination.
Alternatively, the metal of inserting in the metal of inserting in groove and gap be all copper, aluminium, silver, titanium,Tantalum, tungsten or its composition.
Compared with prior art, the present invention has the following advantages: employing two covers that 1) are different from prior artMask plate, the two composition schemes of exposure-etching-exposure-etching (Litho-Etch-Litho-Etch), or adoptA set of mask plate, the side wall (spacer) of the pattern forming taking this mask plate as mask carry out etching based onSide wall carries out the scheme of two compositions, and the present invention proposes first sacrificial in dielectric with traditional single Damascus technicsIn domestic animal layer, form one group of groove, and insert metal to form the first set metal pattern of metal interconnect structure;Then remove this dielectric sacrifice layer, then taking this layer of metal of first set metal pattern as core around it andBetween form that thickness can accurately be controlled and the cover layer of thickness equalization, eat-back described cover layer and form side wall(spacer) gap of, filling between this side wall forms the second cover metal pattern, offside in above-mentioned etch back processGap depth between wall is deepened, and this intensification processing can make follow-up the second cover gold wherein forming of insertingMetal patterns is consistent with the first set metal pattern degree of depth forming before, so completes the two of metal interconnect structureComposition technique. Because this second cover metal pattern is inserted between this first set metal pattern, having realized willThe object that pattern density doubles. Above-mentioned preparation method technique is simple, and metal pattern shape is easy to control.
2) in possibility, 1) on possibility basis, remove side wall, and at this side wall placeLow K(2.0≤k≤4.0 are inserted in region (between the metal pattern retaining)) or ultralow K(k < 2.0) materialMatter, to form the metal interconnect structure of low K or ultralow K dielectric layer, so can reduce parasitic capacitance.
3) in possibility, be different from 2) possibility, this programme proposes removing after side wall, directlyOn the metal pattern of this reservation, form cap rock, to form the metal interconnect structure with air-gap, due toThe dielectric constant k of air is about 1.0, thus with respect to general silica (k > 4.0), low K(2.0≤K≤4.0) or ultralow K(k < 2.0) material, parasitic capacitance can further be reduced.
4), in possibility, the accurate control of this overburden cover is by atomic layer deposition method (ALD)Realize, form the space of filling for the second cover metal pattern by eat-backing realization, aldMethod can realize the deposit of thinner side wall, and eat-back and do not adopt mask plate, thereby the restriction of the limit of not exposed,And can be to the cover layer in the gap between side wall, etch stop layer, even the removal amount of anterior layer dielectric layer is enteredRow is precisely controlled, and forms two covers that the depth is consistent or overlaps metal pattern more to realize.
Brief description of the drawings
Fig. 1 to Fig. 7 forms in each stage of preparation method of the metal interconnect structure of the embodiment of the present invention oneThe profile of structure;
Fig. 8 is the profile of the metal interconnect structure of the embodiment of the present invention two;
Fig. 9 is the profile of the metal interconnect structure of the embodiment of the present invention three.
Detailed description of the invention
As previously mentioned, the two composition schemes that are different from prior art adopt the exposure-etching of two cover mask plates-The two composition schemes of exposure-etching, or adopt a set of mask plate, the side wall of the pattern forming with this mask plate(spacer) carry out the scheme of two compositions for what mask carried out etching based on side wall, the present invention propose first withTraditional single Damascus technics forms one group of groove in dielectric sacrifice layer, and inserts metal to form goldBelong to the first set metal pattern of interconnection structure; Then remove this dielectric sacrifice layer, follow the gold in this reservationBelong to around and between metal, form that thickness can accurately be controlled and the cover layer of thickness equalization, covering by eat-backing thisCap rock forms side wall, and the gap of filling between this side wall forms the second cover metal pattern, in above-mentioned etch back processGap depth between side wall is deepened, and this intensification processing can make follow-up second of the wherein formation of insertingCover metal pattern is consistent with the first set metal pattern degree of depth forming before, so completes metal interconnect structureTwo composition techniques. Because this second cover metal pattern is inserted between this first set metal pattern, realizeThe object that pattern density is doubled.
On such scheme basis, the present invention also proposes two kinds of parasitism electricity that further reduce between interconnection structureThe scheme of holding: a) remove side wall, and fill out in the region at this side wall place (between the metal pattern retaining)Enter low K(2.0≤k≤4.0) or ultralow K(k < 2.0) material, to form low K or ultralow K dielectric layerMetal interconnect structure, so provide two composition schemes of low K or super low-K technology, and low K or superLow K material is not carried out etching, thereby defect is less. B) remove after side wall the direct metal in this reservationOn pattern, form cap rock, to form the metal interconnect structure with air-gap, due to the dielectric constant k of airBe about 1.0, thereby with respect to general silica (k > 4.0), low K(2.0≤k≤4.0) or ultralow K(k < 2.0) material, also can realize the object of further reduction parasitic capacitance.
For above-mentioned purpose of the present invention, feature and advantage can be become apparent more, below in conjunction with accompanying drawingThe specific embodiment of the present invention is described in detail. Because the present invention focuses on interpretation principle, therefore,Drawing not in scale.
Embodiment mono-
The preparation method of metal interconnect structure that the present invention proposes, belongs to the back-end process of semiconductor applications(BEOL), thereby, the present embodiment with on the conductive plunger in the anterior layer of metal interconnect structure form withThe metal interconnect structure of electrical connection be example, introduce in detail the each step of preparation method of the present invention.
Step S11: Semiconductor substrate 10 is provided, has successively from bottom to top in described Semiconductor substrate 10Anterior layer dielectric layer 11, etch stop layer 12, dielectric sacrifice layer 13.
Shown in Figure 1, in anterior layer dielectric layer 11, be formed with conductive plunger 14, this conductive plunger 14 withAnterior layer metal pattern (not shown) is connected, thereby, also claim the conductive plunger 14 of anterior layer; Comprise anterior layerThe substrate of conductive plunger 14 is the Semiconductor substrate 10 of the present embodiment. In the present embodiment, substrate can be silicon,Germanium or SiGe etc., be formed with multiple active, passive device on it.
The material of above-mentioned etch stop layer 12 can select existing this etching that realizes to stop (Etchstop)The material of function, such as silicon nitride, carborundum etc. Dielectric sacrifice layer 13 can select to be easy to the material of removalMatter is for example low K or ultralow K material dielectric layer, silica, organic material, silicon nitride, nitrogen oxygenAny combination of SiClx, carborundum, fire sand or above-mentioned one or more materials.
Step S12: as shown in Figure 2, form multiple grooves 15 in the interior etching of described dielectric sacrifice layer 13.
The technique that this step forms groove 15 is existing single Damascus technics, comprises photoetching and enters afterwardsThe dry etching of row, in dry etching, based on existing etching terminal detection technique, anterior layer dielectric layer 11Can exist segment thickness to be etched, be also that groove 15 exists over etching phenomenon.
Step S13: as shown in Figure 3, insert metal 16 planarization and remove first in described groove 15Excess metal outside groove 15.
The metal 16 of inserting in this step can be for the conventional material of existing metal interconnect structure, for example copper,Conductor or its compound or the compositions such as aluminium, silver, titanium, tantalum, tungsten. The technique that planarization is removed is chemistryMechanical lapping (CMP).
This step has formed the first set metal pattern of metal interconnect structure.
Step S14: as shown in Figure 4, remove dielectric sacrifice layer 13, retain described metal interconnect structureFirst set metal pattern.
The method of above-mentioned removal dielectric sacrifice layer 13 can be that dry etching or wet method are removed, and preferably adopts wetMethod is removed, and corresponding solution is selected according to the material of dielectric sacrifice layer 13, if for example when silica,Structure shown in Fig. 3 can be steeped in HF acid to remove silica, if when silicon nitride, can be by figureStructure shown in 3 is steeped in hot phosphoric acid to remove silicon nitride.
After dielectric sacrifice layer 13 is removed, the first set metal pattern of metal interconnect structure is retained.
Step S15, as shown in Figure 5, around the first set metal pattern of described metal interconnect structure and itBetween form cover layer 17.
Deposited capping layer 17 preferably forms the film of a layer thickness equalization by atomic layer deposition method (ALD),This atomic layer deposition method can deposit be thinner and thickness can precisely be controlled cover layer 17. These cover layer 17 materialsMatter can be selected existing dielectric material, be for example silica, silicon nitride, silicon oxynitride, carborundum,Any combination of one or more materials of fire sand or above-mentioned material. Except atomic layer deposition method, itsIn its embodiment, this cover layer 17 also can be realized the order that thickness can precisely be controlled by other deposition process.
Between above-mentioned cover layer 17, there is gap 18.
Step S16: as shown in Figures 6 and 7, eat-back described cover layer 17 and form side wall 19, describedIn the gap 18 of side wall 19, insert metal 16 planarization and remove the excess metal 16 outside described gap 18With form metal interconnect structure second cover metal pattern, described in eat-back 18 places, gap to 19 of side wallsReason can make the second cover metal pattern consistent with the first set metal pattern degree of depth forming before.
Formation side wall 19 is that the cover layer 17 by eat-backing (Etchback) this thickness equalization is realized,Eat-back and do not adopt mask plate, thereby the restriction of the limit of not exposed.
Gap 18 degree of depth to 19 of side walls in above-mentioned etch back process are deepened, in gap 18Cover layer 17, etch stop layer 12, even anterior layer dielectric layer 11 has carried out part and has removed, object isThe accurately depth H of control gap 18, makes to fill the second cover metal pattern that metal 16 forms thereinDegree of depth h2With first set metal pattern degree of depth h1(or claiming first set metal pattern each figure degree of depth) is consistent,Form each cover metal pattern that the depth is consistent. The etching of the end point determination that eat-back in gap 18 and groove 15End-point detection method is the same, also has over etching phenomenon.
Metal 16 materials of inserting in this step are the same with the metal of first set metal pattern, also can be for existingThe material that some metal interconnect structures are conventional, for example copper, aluminium, silver, titanium, tantalum or its compound or combinationThing. The technique that planarization is removed is cmp (CMP).
This step has formed the second cover metal pattern, and this second cover metal pattern is inserted in first equablyBetween each figure of cover metal pattern, thereby dwindle the spacing between figure, can improve pattern density.
Can find out, in the present embodiment, anterior layer conductive plunger 14 is electrically connected with first set metal pattern, byConsistent in the two cover metal pattern depths, thereby, in other embodiment, also can be by the second cover metal patternBe electrically connected with anterior layer conductive plunger.
It should be noted that, for convenience of the making of rear layer metal interconnect structure, step S16 removes at CMPWhen excess metal 16 outside gap 18, slightly overmastication, to remove the point on side wall 19 topsPoint.
So, completed two composition techniques of metal interconnect structure, be understandable that, such scheme is notBe limited to two composition technique, also can be for three compositions or many compositions technique.
Embodiment bis-
The metal interconnect structure that the present embodiment two provides and way thereof are roughly identical with embodiment mono-. Difference existsIn, also perform step S17: as shown in Figure 8, it is each cover that removal side wall 19 retains the metal 16(insertingMetal pattern), between described metal 16, insert low K or ultralow K material 20 to form low K(2.0≤ k≤4.0) or ultralow K(k < 2.0) metal interconnect structure of dielectric layer. Parasitic capacitance is so providedTwo composition schemes of less low K or super low-K technology, and low K or ultralow K material do not carry out etching,Thereby defect is less.
Embodiment tri-
The metal interconnect structure that the present embodiment three provides and way thereof are roughly identical with embodiment mono-. Difference existsIn, also perform step S17 ': as shown in Figure 9, it is each cover that removal side wall 19 retains the metal 16(insertingMetal pattern), on described metal 16, deposit cap rock 21 is to form the metal interconnected knot with air-gapStructure. Because the dielectric constant k of air is approximately 1.0, thus with respect to general silica (k > 4.0),Low K(2.0≤k≤4.0) or ultralow K(k < 2.0) material, parasitic capacitance can further be reduced.
In the present embodiment, this cap rock 21 is the etch stop layer of rear layer metal interconnect structure, other embodimentIn, other structure also can be set as required.
In the present invention, each embodiment adopts laddering literary style, emphasis describe from previous embodiment different itPlace, the same structure in each embodiment and preparation method are with reference to the same section of previous embodiment.
Although the present invention with preferred embodiment openly as above, it is not for limiting the present invention, appointsWhat those skilled in the art without departing from the spirit and scope of the present invention, can utilize above-mentioned announcementMethod and technology contents are made possible variation and amendment to technical solution of the present invention, therefore, every not de-From the content of technical solution of the present invention, that according to technical spirit of the present invention, above embodiment is done is anySimple modification, equivalent variations and modification, all belong to the protection domain of technical solution of the present invention.
Claims (10)
1. a preparation method for metal interconnect structure, is characterized in that, comprising:
Semiconductor substrate is provided, in described Semiconductor substrate, have successively from bottom to top anterior layer dielectric layer,Etch stop layer, dielectric sacrifice layer;
In described dielectric sacrifice layer, etching forms multiple grooves;
In described groove, insert metal planarization and remove excess metal outside groove to form metalThe first set metal pattern of interconnection structure;
Remove dielectric sacrifice layer, retain the first set metal pattern of described metal interconnect structure;
Around the first set metal pattern of described metal interconnect structure and between form cover layer;
Eat-back described cover layer and form side wall, in the gap of described side wall, insert metal and planarization is goneExcess metal except described gap is to form the second cover metal pattern of metal interconnect structure, described timeErosion makes the second cover metal pattern and the first set metal pattern forming before to the interstitial treatment between side wallThe degree of depth is consistent.
2. preparation method according to claim 1, is characterized in that, described anterior layer dielectric layer has targetElectrical connection region, the metal of inserting in the metal of inserting in groove or gap is electrically connected district with described targetTerritory connects.
3. preparation method according to claim 2, is characterized in that, described target electrical connection region is for leadingElectric plug.
4. preparation method according to claim 1, is characterized in that, in described gap, inserts metal alsoPlanarization is removed after the excess metal step outside described gap, also carries out:
Remove side wall and retain the metal pattern of metal interconnect structure;
Between described metal pattern, inserting low K or ultralow K material is situated between to form low K or ultralow KThe metal interconnect structure of electricity layer.
5. preparation method according to claim 1, is characterized in that, in described gap, inserts metal alsoPlanarization is removed after the excess metal step outside described gap, also carries out:
Remove side wall and retain the metal pattern of metal interconnect structure;
On described metal pattern, deposit cap rock is to form the metal interconnect structure with air-gap.
6. preparation method according to claim 5, is characterized in that, described cap rock is that rear layer is metal interconnectedThe etch stop layer of structure.
7. preparation method according to claim 1, is characterized in that, first of described metal interconnect structureCover metal pattern around and between cover layer be to form by atomic layer deposition method.
8. according to the preparation method described in claim 1 or 7, it is characterized in that, the material of described side wall is twoOne or several in silica, silicon nitride, silicon oxynitride, carborundum, fire sand arbitrarilyCombination.
9. preparation method according to claim 1, is characterized in that, the material of described dielectric sacrifice layer isLow K or ultralow K material dielectric layer, silica, organic material, silicon nitride, silicon oxynitride, carbonAny combination of one or several in SiClx, fire sand.
10. preparation method according to claim 1, is characterized in that, the metal of inserting in groove and gapThe metal of inside inserting is all copper, aluminium, silver, titanium, tantalum, tungsten or its composition.
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| CN109216163A (en) * | 2017-06-29 | 2019-01-15 | 中芯国际集成电路制造(上海)有限公司 | The manufacturing method of semiconductor devices |
| US11972977B2 (en) | 2021-09-08 | 2024-04-30 | International Business Machines Corporation | Fabrication of rigid close-pitch interconnects |
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| KR100817088B1 (en) * | 2007-02-16 | 2008-03-26 | 삼성전자주식회사 | Method of forming fine damascene metal pattern for semiconductor device |
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