CN103927270A - Shared data caching device for a plurality of coarse-grained dynamic reconfigurable arrays and control method - Google Patents
Shared data caching device for a plurality of coarse-grained dynamic reconfigurable arrays and control method Download PDFInfo
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Abstract
The invention discloses a shared data caching device for a plurality of coarse-grained dynamic reconfigurable arrays and a control method of the shared data caching device. The shared data caching device comprises a reconfigurable array data caching control unit, a reconfigurable array data caching unit, an external memory data prefetching caching unit and a data memory access reconfiguration unit, wherein the reconfigurable array data caching control unit is used for controlling data interaction between the reconfigurable arrays and the reconfigurable array data caching unit and data interaction between the reconfigurable array data caching unit and an external memory, the reconfigurable array data caching unit is used for storing data fetched from the external memory, the external memory data prefetching caching unit is used for prefetching data to be accessed to the reconfigurable array data caching unit, and the data memory access reconfiguration unit is used for sending address information and step length information needed by the reconfigurable array data caching unit. The control method is used for achieving data sharing between the coarse-grained dynamic reconfigurable arrays in a reconfigurable system. By means of the shared data caching device and the control method, access conflict is reduced, data processing time of the reconfigurable system is shortened, and the calculation performance of large-scale coarse-grained reconfigurable arrays is improved.
Description
Technical field
The present invention relates to imbedded reconfigurable design field, particularly, relate to a kind of shared data buffer storage device and control method towards multiple coarseness dynamic reconfigurable arrays.
Background technology
Processor and special IC (ASIC) are the calculate platforms in traditional Computer Systems Organization field, and the feature of processor is that the dependent instruction by carrying out in instruction set completes calculating, does not spend the hardware environment of changing bottom.But the arithmetic speed of processor is slow more a lot of than ASIC, each independently operation has higher executive overhead.The feature of special IC is that the operation that realizes application with hardware has very high speed, efficiency and precision, but its defect is that the construction cycle is oversize, and cost is too high, once and hardware circuit can not arbitrarily be changed after making.
The appearance of FPGA Reconfiguration Technologies, greatly change the method for traditional embedded design, restructural calculates the computation schema as a kind of novel time-space domain, obtained more and more widely and paid close attention to, its main application comprises multimedia processing, mobile communication, digital signal processing, data encrypting and deciphering etc.But, in military target coupling, count that computing, sonar wave beams are synthetic greatly, among the computer-aided design (CAD) of genome coupling, visual texture padding, integrated circuit etc., with the difference of application scenario, reconfigurable system also differs widely to the raising degree of performance.Generally, in system, FPGA quantity is more, and overall performance is just higher, averages by the number of chips of FPGA in system, and every FPGA can make arithmetic speed improve 7 ~ 30 times of left and right, but the speed multiple that average every chip block improves is lower.
Along with the raising of calculated performance requirement, computation complexity more and more higher, the computational resource of the reconstruction structure of coarseness also rolls up, complete these application with multiple reconfigurable arrays, when multiple reconfigurable arrays carry out data access simultaneously, can cause access conflict, produce access delay, increase the access time of data, calculated performance is reduced greatly.How to reduce the access time of data, improve the access speed of data, become the important topic improving in the research of reconfigurable system calculated performance.
Summary of the invention
The object of the invention is to, for the problems referred to above, provide a kind of shared data buffer storage device and control method towards multiple coarseness dynamic reconfigurable arrays, to improve the performance of extensive coarseness reconfigurable system.
For achieving the above object, the technical solution used in the present invention is:
Towards a shared data buffer storage for multiple coarseness dynamic reconfigurable arrays, comprise reconfigurable arrays data buffer storage control module, reconfigurable arrays data buffer storage unit, external memory storage data pre-fetching buffer unit, data memory access reconfiguration unit;
Described reconfigurable arrays data buffer storage unit: for storing the data of getting from external memory storage;
Described external memory storage data pre-fetching buffer unit: the data to data buffer unit that is about to access for looking ahead from external memory storage;
Described reconfigurable arrays data buffer storage control module: for controlling the data interaction between reconfigurable arrays and reconfigurable arrays data buffer storage unit and reconfigurable arrays data buffer storage unit and external memory storage;
Described data memory access reconfiguration unit: for sending the required address information of data buffer storage unit and step-length information.
According to a preferred embodiment of the invention, described reconfigurable arrays data buffer storage control module, is characterized in that, hardware configuration comprises, address resolver and step-length resolver;
Described address resolver: for resolving the address information receiving from data memory access reconfiguration unit, judge that according to address information reconfigurable arrays data buffer storage unit is now to carry out data interaction with external memory storage, or carry out data interaction with reconfigurable arrays;
Described step-length resolver: for resolving the step-length information receiving from data memory access reconfiguration unit, for the data storage cell that has N data memory feature district, step-length value bag N kind (N span 1-8), 0,1,2 ..., N-1;
According to a preferred embodiment of the invention, described be used for the reconfigurable arrays data buffer storage unit that storage gets from external memory storage, comprise N storage section (span of N is 1-8), judge that according to the address information receiving reconfigurable arrays data buffer storage unit is to carry out data interaction with external memory storage, or carry out data interaction with reconfigurable arrays, determine according to step-length information the storage section that each reconfigurable arrays can be accessed;
Towards the control method of the shared data buffer storage device of multiple coarseness dynamic reconfigurable arrays, in the time that multiple coarse-grained reconfigurable arrays are accessed reconfigurable arrays data buffer storage unit simultaneously, the storage section of each reconfigurable arrays at one time can only corresponding reconfigurable arrays data buffer storage unit, N is carried out to delivery (mod) computing with the line number M of reconfigurable arrays data buffer storage unit, operation result is n, be M mod N=n, reconfigurable arrays data buffer storage unit represented this line number be defined as to storage section #n.
Each reconfigurable arrays is determined by step-length with the corresponding relation of storage section.N-1 for step-length, reconfigurable arrays #0 access storage section #N-1, reconfigurable arrays #1 access storage section #0, reconfigurable arrays #N-1 access storage section #N-2.For example: if step-length is 0, reconfigurable arrays #0 corresponding stored section #0, reconfigurable arrays #1 corresponding stored section #1, reconfigurable arrays #N-1 access storage section #N-1; If step-length is 1, reconfigurable arrays #0 access storage section #1, reconfigurable arrays #1 access storage section #2, reconfigurable arrays #N-2 access storage section #N-1, reconfigurable arrays #N-1 access storage section #0; If step-length is 2, reconfigurable arrays #0 access storage section #2, reconfigurable arrays #1 access storage section #3, reconfigurable arrays #N-1 access storage section #1.
Technical scheme of the present invention is by providing a kind of shared data buffer storage device and control method thereof towards multiple coarseness dynamic reconfigurable arrays, make multiple reconfigurable arrays access conflict reduction, data access time decreased when visit data buffer memory simultaneously, change the access mode of data buffer storage in traditional reconfigurable system, thereby improved the calculated performance of reconfigurable system.
Other features and advantages of the present invention will be set forth in the following description, and, partly from instructions, become apparent, or understand by implementing the present invention.Object of the present invention and other advantages can be realized and be obtained by specifically noted structure in write instructions, claims and accompanying drawing.
Below by drawings and Examples, technical scheme of the present invention is described in further detail.
Brief description of the drawings
Accompanying drawing is used to provide a further understanding of the present invention, and forms a part for instructions, is used from explanation the present invention with embodiment one of the present invention, is not construed as limiting the invention.In the accompanying drawings:
Fig. 1 is the shared data buffer storage device schematic diagram towards multiple coarseness dynamic reconfigurable arrays;
Fig. 2 is reconfigurable arrays data buffer storage control module schematic diagram;
Fig. 3 is reconfigurable arrays data buffer storage control module workflow diagram;
Fig. 4 is towards the reconfigurable arrays of the shared data cache control method of multiple coarseness dynamic reconfigurable arrays and the corresponding relation block diagram of storage section;
Fig. 5 is the shared data buffer storage device towards multiple coarseness dynamic reconfigurable arrays described in the embodiment of the present invention and the application connection layout of control method.
Embodiment
Below in conjunction with accompanying drawing, the preferred embodiments of the present invention are described, should be appreciated that preferred embodiment described herein, only for description and interpretation the present invention, is not intended to limit the present invention.
As shown in Figure 1, towards shared data buffer storage device and the control method of multiple coarseness dynamic reconfigurable arrays, comprise reconfigurable arrays data buffer storage control module: for controlling the data interaction between reconfigurable arrays and reconfigurable arrays data buffer storage unit and reconfigurable arrays data buffer storage unit and external memory storage; Reconfigurable arrays data buffer storage unit: for storing the data of getting from external memory storage; External memory storage data pre-fetching buffer unit: the data that are about to access for looking ahead from external memory storage are to reconfigurable arrays data buffer storage unit; Data memory access reconfiguration unit: for sending the required address information of reconfigurable arrays data buffer storage unit and step-length information.
As shown in Figure 2, reconfigurable arrays data buffer storage control module, hardware configuration comprises address resolver and step-length resolver; Address resolver, for resolving the address information receiving from data memory access reconfiguration unit, judges that according to address information reconfigurable arrays data buffer storage unit is now to carry out data interaction with external memory storage, or carries out data interaction with reconfigurable arrays; Step-length resolver is used for resolving the step-length information receiving from data memory access reconfiguration unit, for the data storage cell that has N data memory feature district, and step-length value bag N kind (N span 1-8), 0,1,2 ..., N-1;
As shown in Figure 3, the workflow of reconfigurable arrays data buffer storage control module in reconfigurable system, first, data memory access reconstructed module transmission address information and step-length information are to reconfigurable arrays data buffer storage unit, then address resolver is according to the address information that receives, and judgement is now that reconfigurable arrays access data or reconfigurable arrays data buffer storage unit and external memory storage carry out data interaction.If reconfigurable arrays access data, step-length resolver resolving the step-length information receiving, reconfigurable arrays is accessed corresponding storage section according to corresponding step value, if external memory access data adopt the access mode of continuation address to carry out access to the data of reconfigurable arrays data buffer storage unit.
As shown in Figure 4, towards the control method of the shared data buffer storage device of multiple coarseness dynamic reconfigurable arrays.When multiple coarse-grained reconfigurable arrays are simultaneously when visit data buffer unit, the storage section of each reconfigurable arrays at one time can only corresponding data buffer unit, N is carried out to delivery (mod) computing with the line number M of data storage cell, operation result is n, be M mod N=n, data storage cell represented this line number be defined as to storage section #n.
Each reconfigurable arrays is determined by step-length with the corresponding relation of storage section.N-1 for step-length, reconfigurable arrays #0 access storage section #N-1, reconfigurable arrays #1 access storage section #0 ..., reconfigurable arrays #N-1 access storage section #N-2.For example: if step-length is 0, reconfigurable arrays #0 corresponding stored section #0, reconfigurable arrays #1 corresponding stored section #1 ..., reconfigurable arrays #N-1 access storage section #N-1; If step-length is 1, reconfigurable arrays #0 access storage section #1, reconfigurable arrays #1 access storage section #2,, reconfigurable arrays #N-2 access storage section #N-1, if reconfigurable arrays #N-1 access storage section #0 step-length is 2, reconfigurable arrays #0 access storage section #2, reconfigurable arrays #1 access storage section #3 ..., reconfigurable arrays #N-1 access storage section #1.
As shown in Figure 5, H.264 the high-definition digital video of agreement decoding (H.264 1080p@30fps HiP@Level4) has adopted shared data buffer storage device and the control method towards the multiple coarseness dynamic reconfigurable arrays that propose herein, can realize the H.264 high definition video decoding requirement of 1080p@30fps HiP@Level4.The structure of this system comprises: as ARM7TDMI processor, reconfigurable arrays data buffer storage, reconfigurable arrays RCA, ahb bus, the DDR SDRAM of primary controller.The ARM7TDMI processor of the advantages such as that selection has is small-sized, quick, low energy consumption, compiler are supported is as master cpu, for the scheduling of control system operation; Reconfigurable arrays data buffer storage is connected with ARM7TDMI processor by the ahb bus of 32bit, and external memory storage is selected the most frequently used embedded external memory storage DDR SDRAM, supports the data access bit wide of 64bit, has good cost performance and energy loss-rate; RCA has 4, and each RCA all contains 8 × 8 PE, identifies successively RCA0 ~ RCA3.Reconfigurable arrays data buffer storage unit, comprises 4 storage sections, and size is 64KB altogether.
Experiment as a comparison, be provided with a contrast verification system, be not adopt in reconfigurable arrays data buffer storage unit the mode of sub-module with the difference of above-mentioned verification system, the access mode of reconfigurable arrays data storage cell adopts conventional continuation address reading out data pattern in traditional design, and the size of reconfigurable arrays data storage cell is identical with structure.Experimental result shows, adopt the shared data buffer storage device of multiple coarseness dynamic reconfigurable arrays of the present invention's proposition, the average access conflict comparison of reconfigurable arrays data storage cell reduces by 38.9% than verification system, data access required time reduces more than 50%, and calculated performance has improved more than 2 times.
Wherein reconfigurable arrays (ReConfigurable Array) is called for short RCA; Basic processing unit (Processing Element) is called for short PE.
Finally it should be noted that: the foregoing is only the preferred embodiments of the present invention, be not limited to the present invention, although the present invention is had been described in detail with reference to previous embodiment, for a person skilled in the art, its technical scheme that still can record aforementioned each embodiment is modified, or part technical characterictic is wherein equal to replacement.Within the spirit and principles in the present invention all, any amendment of doing, be equal to replacement, improvement etc., within all should being included in protection scope of the present invention.
Claims (5)
1. the shared data buffer storage device towards multiple coarseness dynamic reconfigurable arrays; it is characterized in that, comprise reconfigurable arrays data buffer storage control module, reconfigurable arrays data buffer storage unit, external memory storage data pre-fetching buffer unit, data memory access reconfiguration unit;
Described reconfigurable arrays data buffer storage unit: for storing the data of getting from external memory storage;
Described external memory storage data pre-fetching buffer unit: the data to data buffer unit that is about to access for looking ahead from external memory storage;
Described reconfigurable arrays data buffer storage control module: for controlling the data interaction between reconfigurable arrays and reconfigurable arrays data buffer storage unit and reconfigurable arrays data buffer storage unit and external memory storage;
Described data memory access reconfiguration unit: for sending the required address information of data buffer storage unit and step-length information.
2. shared data buffer storage device according to claim 1, it is characterized in that, reconfigurable arrays data buffer storage unit comprises N storage section, the span of N is 1-8, judge that according to the address information receiving reconfigurable arrays data buffer storage unit is to carry out alternately with external memory storage, or carry out alternately, determining according to step-length information the storage section that each reconfigurable arrays can be accessed with reconfigurable arrays.
3. shared data buffer storage device according to claim 1, is characterized in that, reconfigurable arrays data buffer storage control module comprises address resolver, step-length resolver;
Described address resolver: for resolving the address information receiving from data memory access reconfiguration unit, judge that according to address information reconfigurable arrays data buffer storage unit is now to carry out data interaction with external memory storage, or carry out data interaction with reconfigurable arrays;
Described step-length resolver: for resolving the step-length information receiving from data memory access reconfiguration unit, for the data storage cell that has N data memory feature district, step-length value bag N kind (N span 1-8), 0,1,2 ..., N-1.
4. one kind is utilized the control method of the shared data buffer storage device towards multiple coarseness dynamic reconfigurable arrays described in any one in claim 1-3, it is characterized in that, the workflow of described reconfigurable arrays data buffer storage control module is: first, data memory access reconstructed module transmission address information and step-length information are to reconfigurable arrays data buffer storage unit, then address resolver is according to the address information receiving, judgement is now that reconfigurable arrays and reconfigurable arrays data buffer storage unit carry out data interaction or reconfigurable arrays data buffer storage unit and external memory storage and carry out data interaction, if reconfigurable arrays reading/writing data from reconfigurable arrays data buffer storage unit, step-length resolver is resolved the step-length information receiving, and reconfigurable arrays is accessed corresponding storage section according to corresponding step value, if reconfigurable arrays data buffer storage unit from external memory storage reading/writing data, adopts the access mode of continuation address data to be read or write reconfigurable data buffer unit.
5. control method according to claim 4, it is characterized in that, in the time that multiple coarse-grained reconfigurable arrays are accessed reconfigurable arrays data buffer storage unit simultaneously, the storage section of each reconfigurable arrays at one time can only corresponding reconfigurable arrays data buffer storage unit, N is carried out to delivery (mod) computing with the line number M of reconfigurable arrays data buffer storage unit, operation result is n, be M mod N=n, reconfigurable arrays data buffer storage unit represented this line number be defined as to storage section #n;
Each reconfigurable arrays is determined by step-length information with the corresponding relation of storage section;
N-1 for step-length, reconfigurable arrays #0 access storage section #N-1, reconfigurable arrays #1 access storage section #0 ... reconfigurable arrays #N-1 access storage section #N-2.
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