CN103926034B - The design of Silicon pressure chip structure and technique - Google Patents
The design of Silicon pressure chip structure and technique Download PDFInfo
- Publication number
- CN103926034B CN103926034B CN201410111931.9A CN201410111931A CN103926034B CN 103926034 B CN103926034 B CN 103926034B CN 201410111931 A CN201410111931 A CN 201410111931A CN 103926034 B CN103926034 B CN 103926034B
- Authority
- CN
- China
- Prior art keywords
- silicon
- layer
- ground floor
- insulating barrier
- pressure
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 title claims abstract description 141
- 229910052710 silicon Inorganic materials 0.000 title claims abstract description 111
- 239000010703 silicon Substances 0.000 title claims abstract description 111
- 238000000034 method Methods 0.000 title claims abstract description 21
- 230000004888 barrier function Effects 0.000 claims abstract description 29
- 238000007789 sealing Methods 0.000 claims abstract description 16
- 238000005516 engineering process Methods 0.000 claims abstract description 10
- 238000000151 deposition Methods 0.000 claims abstract description 6
- SBEQWOXEGHQIMW-UHFFFAOYSA-N silicon Chemical compound [Si].[Si] SBEQWOXEGHQIMW-UHFFFAOYSA-N 0.000 claims abstract description 5
- 230000015572 biosynthetic process Effects 0.000 claims abstract description 4
- 239000004020 conductor Substances 0.000 claims abstract description 3
- 230000008021 deposition Effects 0.000 claims abstract description 3
- 239000012528 membrane Substances 0.000 claims description 12
- 238000005530 etching Methods 0.000 claims description 10
- 239000002210 silicon-based material Substances 0.000 claims description 8
- 238000005260 corrosion Methods 0.000 claims description 7
- 230000007797 corrosion Effects 0.000 claims description 7
- 238000010276 construction Methods 0.000 claims description 6
- 239000011888 foil Substances 0.000 claims description 3
- 230000009467 reduction Effects 0.000 claims description 3
- 230000000694 effects Effects 0.000 claims description 2
- 238000000992 sputter etching Methods 0.000 claims description 2
- 238000001312 dry etching Methods 0.000 claims 1
- 230000008569 process Effects 0.000 abstract description 3
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 10
- 239000000377 silicon dioxide Substances 0.000 description 5
- 235000012239 silicon dioxide Nutrition 0.000 description 5
- 238000010586 diagram Methods 0.000 description 4
- 239000003292 glue Substances 0.000 description 4
- 238000003754 machining Methods 0.000 description 3
- 238000004519 manufacturing process Methods 0.000 description 3
- 230000008859 change Effects 0.000 description 2
- 239000010931 gold Substances 0.000 description 2
- 238000002955 isolation Methods 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- 239000002184 metal Substances 0.000 description 2
- 229910052751 metal Inorganic materials 0.000 description 2
- 238000004377 microelectronic Methods 0.000 description 2
- 229910021421 monocrystalline silicon Inorganic materials 0.000 description 2
- 230000002093 peripheral effect Effects 0.000 description 2
- 238000001259 photo etching Methods 0.000 description 2
- 238000001020 plasma etching Methods 0.000 description 2
- 238000005498 polishing Methods 0.000 description 2
- 239000000126 substance Substances 0.000 description 2
- 229910001128 Sn alloy Inorganic materials 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 230000007812 deficiency Effects 0.000 description 1
- 230000001419 dependent effect Effects 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 239000008393 encapsulating agent Substances 0.000 description 1
- 239000000945 filler Substances 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- JVPLOXQKFGYFMN-UHFFFAOYSA-N gold tin Chemical compound [Sn].[Au] JVPLOXQKFGYFMN-UHFFFAOYSA-N 0.000 description 1
- 208000015181 infectious disease Diseases 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 230000009916 joint effect Effects 0.000 description 1
- WABPQHHGFIMREM-UHFFFAOYSA-N lead(0) Chemical compound [Pb] WABPQHHGFIMREM-UHFFFAOYSA-N 0.000 description 1
- 239000000203 mixture Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000012544 monitoring process Methods 0.000 description 1
- 238000005457 optimization Methods 0.000 description 1
- 230000000246 remedial effect Effects 0.000 description 1
- 238000001039 wet etching Methods 0.000 description 1
Landscapes
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Measuring Fluid Pressure (AREA)
Abstract
The invention discloses a kind of structure design and processes using multilayer silicon structure to make pressure chip.It includes: (1) uses multilamellar (three layers) silicon structure of silicon insulating barrier silicon insulating barrier silicon to make pressure chip.Ground floor silicon arranges full-bridge pressure drag component, junction point and silicon sealing strip；Formation groove around pressure drag component and junction point；Formed with island structural cavities in the third layer silicon of multilamellar (three layers) silicon structure；(2) select another sheet routine SOI sheet as sealing structure, its ground floor silicon arranges silicon sealing strip and silicon connects post；(3) use silicon silicon to be good for conjunction technology and multilamellar (three layers) silicon structure and strong conjunction of conventional SOI sheet are formed multilamellar (five layers) silicon structure；(4) second layer silicon of thinning conventional SOI sheet；Dry plasma etch is used to open hole on the second layer silicon of conventional SOI sheet；(5) deposition insulating layer on the surface of second layer silicon and through-hole wall of conventional SOI sheet；And at through hole depositing conductive material, form the contact that is electrically connected.
Description
Technical field
The present invention relates to art of pressure sensors, specifically, be related specifically to a kind of multilayer silicon structure pressure chip and technique.
Background technology
Micro-electronic mechanical skill is also known as MEMS(Micro-Electro-Mechanical-System) technology is a kind of new and high technology by mechano-electronic device miniaturization, it is especially suited for use extensive manufacture high-performance micro mechano-electronic device, such as micro pressure sensor, micro accelerometer, minisize gyroscopes etc..Integrated circuit and frame for movement are combined by these microelectronic mechanical devices, have powerful, and precision is high, the feature that reliability is high.
MEMS pressure sensor is dependent on a stressor layer film and senses extraneous pressure medium, and the pressure drag component being in pressure membrane is by during from the pressure that pressure membrane transmits, and its electric property changes, and shows as resistance value and changes.By the monitoring to resistance change, it can be determined that the size of pressure, and by circuit, the size of pressure is converted into the signal of telecommunication and exports peripheral circuit control system.
Traditionally, MEMS pressure chip pressure membrane realizes by wet etching or etching technics, and the THICKNESS CONTROL of pressure membrane depends on corrosion or the time of etching.Due to current 6 inches and the area of above silicon chip own big, thickness deviation is big and corrodes and the uncontrollability of etching technics, the deviation causing MEMS pressure chip pressure membrane thickness is relatively big, to such an extent as to individually to compensate each pressure chip, and production efficiency is low.Corrosion and etching technics inevitably produce damage to Silicon pressure film simultaneously, reduce the mechanical strength of pressure membrane, thus cause the reduction of device reliability.Additionally the connection of pressure chip and peripheral circuit completes by external lead wire.These lead-in wires are exposed to outside pressure transducer, in dynamic environment, in vibration environment, easily lose efficacy.The most commonly used a kind of remedial is to be fixed by lead-in wire with special glue.This scheme proposes strict requirements to glue, i.e. high resiliency, can transmit pressure, high temperature resistance, and the life-span is long.Under the high temperature conditions, particularly temperature is more than 200 degree, and current glue still can not be fully achieved these requirements.
Therefore, it is badly in need of wanting a kind of new method making high temperature high precision MEMS pressure chip.
Summary of the invention
The design that it is an object of the invention to provide the pressure chip using multilayer silicon structure and the technique being processed as pressure chip, for the deficiencies in the prior art, be effectively improved answer pressure chip concordance and in hot environment the temperature stability of output signal, there is high stable, performance optimization and the feature of high reliability.
Technical problem solved by the invention can realize by the following technical solutions:
Multilamellar (three layers) silicon structure of a kind of silicon-insulating barrier-silicon-insulating barrier-silicon, described ground floor silicon has the quick pressure drag component of some power, and described some power quick pressure drag component composition full-bridge Wheatstone bridge, for changing into the signal of telecommunication by pressure signal；Described second layer silicon is arranged at the lower section of the first silicon material layer, is used as pressure membrane to experience the change of pressure, and the quick pressure drag component of power being conducted to ground floor silicon；The ground floor insulating barrier electrically connected between the two for isolation it is provided with between ground floor silicon and second layer silicon；Described third layer silicon is arranged at the lower section of second layer silicon, for constructing the supporting construction of pressure chip and the island structure of pressure membrane, is provided with the second insulating barrier at second layer silicon and third layer silicon.
A kind of multilayer silicon structure is processed as the technique of pressure chip, comprises the steps:
(1) full-bridge pressure drag component, junction point and silicon sealing strip are set on the ground floor silicon of above-mentioned multilamellar (three layers) silicon structure；Using ion etching or method formation groove around pressure drag component and junction point of corrosion, this groove runs through ground floor silicon, and the bottom of groove is positioned at ground floor silicon；
(2) on the third layer silicon of multilamellar (three layers) silicon structure, supporting construction and island structure are set；Using dry plasma etch, etching technics is automatically stopped in the second insulating barrier；
(3) select a piece of conventional SOI, including two-layer silicon and the insulating barrier between two-layer silicon, and silicon sealing strip and silicon connection post are set on ground floor silicon；
(4) use silicon-silicon to be good for conjunction technology multilamellar (three layers) silicon structure and conventional SOI foil gauge are good for and are combined, to form multilamellar (5 layers) silicon structure；
(5) by the second layer silicon material layer mechanical reduction of conventional SOI sheet；
(6) opening hole on the second layer silicon of conventional SOI sheet, second layer silicon and insulating barrier are run through in this hole, stop at ground floor silicon material layer；
(7) deposition insulating layer on the surface of second layer silicon material layer and through-hole wall of conventional SOI sheet；
(8) at above-mentioned through hole depositing conductive material, the contact that is electrically connected is formed.
Compared with prior art, beneficial effects of the present invention is as follows:
1) rely on groove that dependence ground floor insulating barrier is fully achieved between physical isolation, and pressure drag component and second layer Silicon pressure film between pressure drag component to realize electrically insulating completely.So completely eliminate the impact relying on the PN junction joint property high-temperature current leakage that brought of electric isolution excessive, make the pressure chip can at high temperature steady operation.
2) second layer insulating barrier, as corrosion/etching barrier layer, it is ensured that the performance of second layer Silicon pressure film and thickness by infection, do not improve stability and the concordance of pressure chip.
3) sealing of pressure chip uses strong conjunction of silicon-silicon to seal, and owing to encapsulant is commaterial (silicon), eliminates the thermal mismatching phenomenon that different materials thermal coefficient of expansion difference causes, improves the pressure chip stability at hot operation.
4) electrical connection uses without gage system, can avoid using glue anchor leg, improve the reliability of pressure chip.
Accompanying drawing explanation
Fig. 1 is the schematic diagram of multilamellar of the present invention (three layers) silicon structure.
Fig. 2 is pressure drag component of the present invention, silicon junction point and the schematic diagram of silicon sealing strip.
Fig. 3 is the machining sketch chart of multilamellar (three layers) the silicon structure ground floor silicon of technique of the present invention.
Fig. 4 is conventional SOI sheet silicon junction point and the silicon sealing strip schematic diagram of technique of the present invention.
Fig. 5 is the machining sketch chart of the conventional SOI sheet ground floor silicon material layer of technique of the present invention.
Fig. 6 is the machining sketch chart of multilamellar (five layers) silicon structure of technique of the present invention.
Fig. 7 is multilamellar (five layers) the silicon structure pressure chip schematic diagram of technique of the present invention.
Detailed description of the invention
For the technological means making the present invention realize, creation characteristic, reach purpose and be easy to understand with effect, below in conjunction with detailed description of the invention, the present invention is expanded on further.
As it is shown in figure 1, the present invention uses a kind of multilamellar (three layers) silicon structure, it includes the ground floor monocrystal silicon 100 set gradually from top to bottom, ground floor insulating barrier 200, second layer monocrystal silicon 300, second layer insulating barrier 400 and the 3rd layer of monocrystal silicon 500.The thickness of each layer, resistivity, can determine according to the performance requirement of foil gauge manufacturing this multilamellar (three layers) silicon structure when etc. physicochemical properties.
In this embodiment, ground floor monocrystal silicon 100 is (100) crystal orientation p type single crystal silicon, and thickness is 0.1 micron-5 microns, and THICKNESS CONTROL can use but be not limited to the mode of chemical mechanical polishing.Resistivity is 0.005 ohmcm-0.1 ohmcm, uses the mode of ion implanting or thermal diffusion to control, and the deviation of its resistivity is +/-1%.Ground floor insulating barrier 200 can be but not limited to silicon dioxide (SiO2), and thickness is 0.1 micron-5 microns, uses thermal oxide mode grow and control thickness.The thickness of second layer monocrystal silicon 300 is 2 microns-20 microns, uses the mode of chemical mechanical polishing to control thickness, and thickness deviation is +/-0.5 micron.Second layer insulating barrier 400 can be but not limited to silicon dioxide (SiO2), and thickness is 0.1 micron-5 microns, uses the mode of thermal oxide grow and control thickness.The thickness of the 3rd layer of monocrystal silicon 500 is 250 microns-800 microns, resistivity no requirement (NR).
As in figure 2 it is shown, this structure includes 4 pressure drag components, 120,4 silicon junction points 130 of 110,4 groups of silicon lines and 1 silicon sealing strip 140 closed.4 single pressure drag components 110 are connected into a complete full-bridge Wheatstone bridge by silicon connecting line 120, have a silicon junction point 130 often organizing, be used for drawing the signal of telecommunication between silicon line.Silicon sealing ring 140 is for the sealing of pressure chamber.
As it is shown on figure 3, use the photoetching process in IC technique or MEMS technology structure shown in Fig. 2 to be transferred on the ground floor monocrystalline silicon layer of multilamellar (three layers) silicon structure.Groove 150 uses plasma etching technology or wet corrosion technique to realize, and groove passes ground floor silicon 100, stops at ground floor insulating barrier 200.Pressure drag component 110,120,4 silicon junction points of silicon line 130 and sealing structure 140 are isolated by groove, form electric insulation.
As shown in Figure 4, this structure includes the silicon sealing strip 610 closed, and silicon connects post 620 and cavity 630.This structure can be transferred on the ground floor silicon 600 of conventional SOI sheet by the photoetching process in IC technique or MEMS technology, as shown in Figure 5.
As it is shown in figure 5, the structure of conventional SOI sheet includes ground floor silicon 600, ground floor insulating barrier 700 and second layer silicon 800.The thickness of ground floor silicon 600 is at 10 microns-150 microns.The thickness of ground floor insulating barrier 700 is 0.5 micron-5 microns.The thickness of second layer silicon 800 is at 400 microns-800 microns.
As shown in Figure 6, the mode that multilamellar (three layers) silicon structure and conventional SOI sheet use silicon-silicon to be good for conjunction is combined.Silicon sealing strip 140 on multilamellar (three layers) silicon structure ground floor silicon 100 seals structure 610 air-tightness with silicon on conventional SOI sheet ground floor silicon 600 and combines the pressure chamber that formation is airtight.Silicon junction point 130 and silicon connect post 620 closely strong conjunction and form electrical connection.The thickness of the second layer silicon 800 of conventional SOI sheet is thinned to 30 microns-50 microns.The third layer silicon 500 of multilamellar (three layers) silicon structure use plasma etching technology etch groove 510, island structure 520 and supporting construction 530.Island structure 520 and supporting construction 530 are isolated by groove 510.Etching automatic stop terminates in second layer insulating barrier 400.
As it is shown in fig. 7, use the method for etching or corrosion to open hole 810 on the second layer silicon 800 of conventional SOI sheet.Through hole 810 runs through second layer silicon 800 and ground floor insulating barrier 700, and the silicon stopping at ground floor silicon 600 connects on post 620.Sidewall on the surface of second layer silicon 800 and hole 810 deposits a layer insulating 820, and the material of insulating barrier can be SiO2.The insulating barrier 820 connected by silicon on post 620 is removed.Filler metal 830 in hole 810 again, as the leading point of the signal of telecommunication.Metal generally gold (Au) or gold-tin alloy (AuSn) are used for electrically connecting.
The ultimate principle of the present invention and principal character and advantages of the present invention have more than been shown and described.Skilled person will appreciate that of the industry; the present invention is not restricted to the described embodiments; the principle that the present invention is simply described described in above-described embodiment and description; without departing from the spirit and scope of the present invention; the present invention also has various changes and modifications, and these changes and improvements both fall within scope of the claimed invention.Claimed scope is defined by appending claims and equivalent thereof.
Claims (1)
1. use multilayer silicon structure tonnage chip, it is characterised in that described multilayer silicon structure includes from upper
The ground floor silicon set gradually under to, ground floor insulating barrier, second layer silicon, second layer insulating barrier and third layer
Silicon；Ground floor silicon is device layer, is used for making pressure-sensing device, silicon junction point and silicon sealing strip；First
Layer has ground floor insulating barrier between silicon, second layer silicon, the electric isolution between above-mentioned two-layer silicon；The second layer
Silicon is used as pressure membrane, and the thickness of described pressure membrane is determined by the thickness of the second layer silicon of multilayer silicon structure；3rd
Layer silicon is used as supporting construction and the island structure of pressure membrane of pressure chip；Second layer silicon, third layer silicon it
Between to have second layer insulating barrier, the effect of described second layer insulating barrier be for protection the when etching third layer silicon
Pressure membrane structure on two layers of silicon is not etched；
The technique using multilayer silicon structure tonnage chip, comprises the steps:
(1) on the ground floor silicon of above-mentioned multilayer silicon structure, arrange full-bridge pressure drag component, junction point and silicon seal
Bar；Use ion etching or method formation groove around pressure drag component and junction point of corrosion, this ditch
Groove runs through ground floor silicon, and the bottom of groove is positioned at ground floor silicon；
(2) on the third layer silicon of multilayer silicon structure, supporting construction and island structure are set；Use plasma dry
Etching, etching technics is automatically stopped in the second insulating barrier；
(3) a piece of conventional SOI is selected, including two-layer silicon and the insulating barrier between two-layer silicon, and the
Silicon sealing strip is set on one layer of silicon and silicon connects post；
(4) use silicon-silicon to be good for conjunction technology multilayer silicon structure and conventional SOI foil gauge are good for and are combined, with
Form five layers of silicon structure；
(5) by the second layer silicon material layer mechanical reduction of conventional SOI sheet；
(6) opening hole on the second layer silicon of conventional SOI sheet, second layer silicon and insulating barrier are run through in this hole, stop
Terminate in ground floor silicon material layer；
(7) deposition insulating layer on the surface of second layer silicon material layer and through-hole wall of conventional SOI sheet；
(8) at above-mentioned through hole depositing conductive material, the contact that is electrically connected is formed.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201410111931.9A CN103926034B (en) | 2014-03-25 | 2014-03-25 | The design of Silicon pressure chip structure and technique |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201410111931.9A CN103926034B (en) | 2014-03-25 | 2014-03-25 | The design of Silicon pressure chip structure and technique |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN103926034A CN103926034A (en) | 2014-07-16 |
| CN103926034B true CN103926034B (en) | 2016-08-31 |
Family
ID=51144333
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201410111931.9A Active CN103926034B (en) | 2014-03-25 | 2014-03-25 | The design of Silicon pressure chip structure and technique |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN103926034B (en) |
Families Citing this family (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104864988B (en) * | 2015-06-10 | 2017-07-04 | 中国电子科技集团公司第十三研究所 | MEMS pressure sensor of silicon island membrane structure and preparation method thereof |
| CN107894297B (en) * | 2017-11-07 | 2020-02-18 | 无锡必创传感科技有限公司 | Pressure sensor chip and manufacturing method thereof |
| CN110577185B (en) * | 2019-08-06 | 2021-11-16 | 西人马联合测控（泉州）科技有限公司 | MEMS structure, manufacturing method of MEMS structure and tire pressure sensor |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1561539A (en) * | 2001-10-01 | 2005-01-05 | 瓦尔蒂翁特克尼里伦图基穆斯克斯库斯公司 | Method for forming a cavity structure on SOI substrate and cavity structure formed on SOI substrate |
| US7052623B1 (en) * | 1998-10-15 | 2006-05-30 | Robert Bosch Gmbh | Method for processing silicon using etching processes |
| CN101244802A (en) * | 2008-03-27 | 2008-08-20 | 中国电子科技集团公司第十三研究所 | High depth-width ratio micro-machining based on silicon-silicon linking |
Family Cites Families (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP3575373B2 (en) * | 1999-04-19 | 2004-10-13 | 株式会社村田製作所 | Manufacturing method of external force detection sensor |
| JP2002200599A (en) * | 2000-10-30 | 2002-07-16 | Sony Corp | Producing method for three-dimensional structure |
| CN102320552A (en) * | 2011-06-10 | 2012-01-18 | 西安交通大学 | Method for making viscosity sensor chip based on separation by implantation of oxygen technology |
-
2014
- 2014-03-25 CN CN201410111931.9A patent/CN103926034B/en active Active
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7052623B1 (en) * | 1998-10-15 | 2006-05-30 | Robert Bosch Gmbh | Method for processing silicon using etching processes |
| CN1561539A (en) * | 2001-10-01 | 2005-01-05 | 瓦尔蒂翁特克尼里伦图基穆斯克斯库斯公司 | Method for forming a cavity structure on SOI substrate and cavity structure formed on SOI substrate |
| CN101244802A (en) * | 2008-03-27 | 2008-08-20 | 中国电子科技集团公司第十三研究所 | High depth-width ratio micro-machining based on silicon-silicon linking |
Non-Patent Citations (1)
| Title |
|---|
| 微机械谐振梁压力传感器研究;陈德勇;《中国优秀博硕士学位论文全文数据库 (博士)信息科技辑》;20021215(第2期);说明书第2.1节、第3.3节、第4.2节及图2.1、图4.4、4.5、4.6、4.7 * |
Also Published As
| Publication number | Publication date |
|---|---|
| CN103926034A (en) | 2014-07-16 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN110467148B (en) | Wafer-level packaging MEMS chip structure and processing method thereof | |
| US10962431B2 (en) | Pressure sensor generating a transduced signal with reduced ambient temperature dependence, and manufacturing method thereof | |
| CN203683082U (en) | Semiconductor device with hole | |
| CN103335753B (en) | The ultra-miniature pressure sensor chip of si-glass base beam diaphragm structure and manufacture method | |
| US20190242770A1 (en) | Mems pressure sensor and method for forming the same | |
| US8714021B2 (en) | Catheter die and method of fabricating the same | |
| CN104089727B (en) | The high performance pressure sensor chip and manufacture method of integrated temperature | |
| CN103604538B (en) | MEMS pressure sensor chip and its manufacture method based on SOI technology | |
| CN110550598B (en) | Resonant differential pressure sensor and preparation method thereof | |
| JP6440290B2 (en) | Micro-electromechanical system device having crack-resistant film structure and method for manufacturing the same | |
| CN110723712B (en) | MEMS device structure and manufacturing method | |
| CN105444931A (en) | SOI pressure-sensitive chip based on sacrificial layer technology, and manufacturing method thereof | |
| CN105486435A (en) | MEMS polysilicon nanofilm pressure sensor chip and manufacturing method thereof | |
| CN107963609A (en) | A kind of total silicon MEMS wafer-grade vacuum encapsulation methods based on anode linkage | |
| CN103926034B (en) | The design of Silicon pressure chip structure and technique | |
| TW201322366A (en) | Sensor manufacturing method | |
| CN103196596B (en) | Nanometer film pressure sensor based on sacrificial layer technology and manufacturing method thereof | |
| CN205449349U (en) | MEMS polycrystalline silicon nanometer membrane pressure sensor chip | |
| CN104236787A (en) | Mems differential pressure sensor chip and manufacturing method | |
| CN105084296B (en) | Manufacturing method for MEMS(Micro Electro Mechanical Systems) capacitive pressure transducer | |
| KR100904994B1 (en) | Method for fabricating pressure sensor and structure of the same | |
| CN111684252B (en) | Capacitive pressure sensor and other devices with suspended membrane and rounded corners at anchor edges | |
| CN205981503U (en) | High accuracy pressure sensor based on silicon bonded | |
| CN112924058A (en) | Pressure sensor and method for manufacturing the same | |
| CN112857628A (en) | MEMS capacitive pressure sensor chip and manufacturing process thereof |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| PE01 | Entry into force of the registration of the contract for pledge of patent right | ||
| PE01 | Entry into force of the registration of the contract for pledge of patent right |
Denomination of invention: Structural Design and Process of Silicon Pressure Chips Granted publication date: 20160831 Pledgee: Shanghai Rural Commercial Bank Co.,Ltd. Qingpu sub branch Pledgor: SMARTSTONE (SHANGHAI) SENSING & CONTROL TECH CO.,LTD. Registration number: Y2024310000067 |