CN103915828A - RC triggered ESD protection circuit for integrated circuit - Google Patents
RC triggered ESD protection circuit for integrated circuit Download PDFInfo
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- CN103915828A CN103915828A CN201410127313.3A CN201410127313A CN103915828A CN 103915828 A CN103915828 A CN 103915828A CN 201410127313 A CN201410127313 A CN 201410127313A CN 103915828 A CN103915828 A CN 103915828A
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Abstract
The invention provides an RC triggered ESD protection circuit for an integrated circuit, and belongs to the technical field of electronics. According to the RC triggered ESD protection circuit, an RC series circuit composed of a capacitor and a resistor triggers and starts a PMOS tube, the electric potential of an electric potential point (109) is increased by currents, therefore, an NMOS tube is started, and the electric potential of the electric potential point (109) is reduced; finally, positive feedback is formed so as to guarantee that output of a triggering circuit (103) is at a high electric potential. The RC triggered ESD protection circuit only needs 5-15-ns RC triggering time; compared with 20-ns RC triggering time of a traditional triggering circuit, the capacitance value and the resistance value are reduced to about one tenth of the original capacitance value and the original resistance value, namely, the layout area of the triggering circuit is also reduced to about one tenth of the original layout area. In addition, output voltage of an electric potential point (110) can be adjusted by adjusting the width-to-length ratio of the PMOS tube (107) and the magnitude of a second resistor (205), and therefore the discharge capacity of ESD currents of an ESD clamping device (104) is adjusted.
Description
Technical field
The invention belongs to electronic technology field, the static that relates to semiconductor integrated circuit chip discharges (ElectroStatic Discharge, referred to as ESD) protective circuit technology, espespecially a kind of RC trigger-type esd protection circuit for integrated circuit.
Background technology
Produce at integrated circuit, encapsulate, test, deposit, in handling process, static discharge is as the inevitable natural phenomena of one and ubiquity.Along with reducing and the development of various advanced technologies of integrated circuit technology characteristic size, the situation that integrated circuit is damaged by ESD phenomenon is more and more general, relevant research shows, 30% of ic failure product is all owing to suffering static discharge phenomenon caused.Therefore, use high performance ESD protective device to be protected and seem very important integrated circuit circuit.
Along with reducing and the development of various advanced technologies of integrated circuit technology characteristic size; particularly in the technique of deep-submicron; the traditional E SD that relies on the reverse-biased PN of clamps save to puncture protects structure to be difficult to meet the designing requirement of ESD, effective Protective IC of the method for opening esd clamp position device by RC circuits for triggering.
Fig. 1 is the RC trigger-type esd protection circuit of tradition for integrated circuit, comprising: RC circuits for triggering 103 and esd clamp position device 104.Circuits for triggering 103 comprise resistance 105, electric capacity 106, PMOS pipe 107 and NMOS pipe 108.Resistance termination VDD power line 101 after resistance 105 and electric capacity 106 series connection, its electric capacity termination VSS power line 102; The tie point 109 of resistance 105 and electric capacity 106 meets PMOS manages the grid of 107 grids and NMOS pipe 108, the source electrode of PMOS pipe 107 connects VDD power line 101, the source electrode of NMOS pipe 108 connects VSS power line 102, the drain electrode of the drain electrode of PMOS pipe 107 and NMOS pipe 108 interconnects and connects the control end of esd clamp position device 104, the high pressure termination VDD power line 101 of clamps 104, the low pressure termination VSS power line 102 of clamps 104.
The operation principle of this RC trigger-type esd protection circuit is: the time constant of the RC series circuit being made up of resistance 105 and electric capacity 106 in RC circuits for triggering 103 designs at 0.1～1us, in the situation that not powering on, when esd pulse is not added between power line 101 and 102, the current potential of potential point 109 is 0, in the time there is a positive esd pulse in VDD power line 101 ends, because ESD voltage has the very fast rate of climb (its rise time is about 5～15ns), the voltage of potential point 109 cannot be got caught up in the ESD rate of voltage rise of 101 ends because of RC late effect, therefore the electronegative potential of potential point 109 causes the current potential of the output 110 of the inverters that PMOS pipe 107 and NMOS pipe 108 form to rise to high potential by the ESD voltage on 101.And the high potential of potential point 110 can trigger esd clamp position device 104, thereby bypass is fallen ESD electric current.And under normal condition of work, the additional fixing operating voltage of VDD power line 101, in the time of start, the voltage of VDD power line 101 rises to 5V gradually from 0V, but due to the about 1ms of the voltage rising time left and right of VDD power line 101, and the time constant of RC circuits for triggering is designed to 0.1～1us, therefore the voltage of potential point 109 is got caught up in the 101 end operating voltage rates of climb, inverter can not be opened, potential point 110 keeps electronegative potential, thereby can not open esd clamp position device, can not affect the normal work of internal circuit.
Although these circuits for triggering can well be opened esd clamp position device, with the ESD electric current of releasing, but the side effect bringing is also clearly, because the RC time constant (being the RC triggered time) of RC circuits for triggering needs design within the scope of 0.1～1 μ s, conventional representative value is 200ns, therefore just need very large resistance and electric capacity (such as the electric capacity of 2pF and the resistance in 100K Europe), this often just needs very large chip area, increases design cost.
Summary of the invention
The RC time constant that the present invention is directed to the conventional RC trigger-type esd protection circuit RC circuits for triggering for integrated circuit is bigger than normal; need larger resistance and electric capacity; thereby cause the excessive technical problem of RC trigger-type esd protection circuit chip occupying area, a kind of RC trigger-type esd protection circuit for integrated circuit is provided.It is less that this RC trigger-type esd protection circuit has RC time constant, without the advantage of larger resistance and electric capacity, thereby RC trigger-type esd protection circuit chip occupying area reduced greatly, finally reaches the object that reduces integrated circuit cost.
The present invention solves the problems of the technologies described above adopted technical scheme:
For a RC trigger-type esd protection circuit for integrated circuit, as shown in Figure 2, comprising: RC circuits for triggering 103 and esd clamp position device 104.Circuits for triggering 103 comprise two resistance 105 and 205, electric capacity 106, PMOS pipe 107 and a NMOS pipe 108.Resistance termination VDD power line 101 after the first resistance 105 and electric capacity 106 series connection, its electric capacity termination VSS power line 102; The tie point 109 of the first resistance 105 and electric capacity 106 connects the drain electrode of grid and the NMOS pipe 108 of PMOS pipe 107, the source electrode of PMOS pipe 107 connects VDD power line 101, the source electrode of NMOS pipe 108 connects VSS power line 102, and the tie point 110 after the gate interconnection of the drain electrode of PMOS pipe 107 and NMOS pipe 108 connects VSS power line 102 by the second resistance 205 when connecing the control end of esd clamp position device 104.The high pressure termination VDD power line 101 of clamps 104, the low pressure termination VSS power line 102 of clamps 104.
Another kind provided by the invention, for the RC trigger-type esd protection circuit of integrated circuit, as shown in Figure 3, comprising: RC circuits for triggering 103 and esd clamp position device 104.Circuits for triggering 103 comprise two resistance 105 and 205, electric capacity 106, two PMOS pipes 107 and 207, two NMOS pipes 108 and 208.Electric capacity termination VDD power line 101 after the first resistance 105 and electric capacity 106 series connection, its resistance termination VSS power line 102; The tie point 109 of the first resistance 105 and electric capacity 106 connects the drain electrode of a PMOS pipe 107 and the grid of NMOS pipe 108, the source electrode of the one PMOS pipe 107 connects VDD power line 101, the source electrode of the one NMOS pipe 108 connects when tie point 110 after the grid of VSS power line 102, the one PMOS pipes 107 and the drain electrode interconnection of NMOS pipe 108 connects the grid of the 2nd PMOS pipe 207 and the 2nd NMOS pipe 208 and connects VDD power line 101 by the second resistance 205; The source electrode that the source electrode of the 2nd PMOS pipe 207 connects VDD power line 101, the two NMOS pipes 208 connects tie point 120 after the grid of VSS power line 102, the two PMOS pipes 207 and the gate interconnection of the 2nd NMOS pipe 208 and connects the control end of esd clamp position device 104.The high pressure termination VDD power line 101 of clamps 104, the low pressure termination VSS power line 102 of clamps 104.
Beneficial effect of the present invention is; the RC triggered time that only needs 5～15ns for the RC trigger-type esd protection circuit of integrated circuit provided by the invention; with respect to the RC triggered time (representative value is 200ns) of conventional trigger circuit 0.1～1 μ s; electric capacity and resistance value are reduced to 1/10th original left and right, are also that the chip area of circuits for triggering is reduced to 1/10th original left and right.In addition, scheme one can also be by regulating PMOS pipe 107(or PMOS pipe 107) breadth length ratio and the size of the second resistance 205 regulate the output voltage of potential point 110, thereby regulate the relieving capacity of the ESD electric current of esd clamp position device 104.
Accompanying drawing explanation
Fig. 1 is traditional RC trigger-type esd protection circuit.
Fig. 2 is a kind of RC trigger-type esd protection circuit for integrated circuit provided by the invention.
Fig. 3 is the RC trigger-type esd protection circuit of another kind provided by the invention for integrated circuit.
Fig. 4 be shown in Fig. 2 for the RC trigger-type esd protection circuit of integrated circuit the analog simulation figure under ESD condition.
Fig. 5 is for the RC trigger-type esd protection circuit of integrated circuit analog simulation figure in normal working conditions shown in Fig. 2.
Embodiment
Below in conjunction with drawings and Examples, describe technical scheme of the present invention in detail:
The invention provides the RC trigger-type esd protection circuit for integrated circuit.This RC trigger-type esd protection circuit can not affect the work of integrated circuit in normal working conditions, in the time that esd pulse arrives, can trigger in time esd clamp position device, thereby discharge ESD electric current plays the effect of Protective IC.With respect to traditional circuit, the advantage of this circuit maximum is exactly that the RC time constant (being the triggered time) of circuits for triggering is little, effectively reduces electric capacity and resistance, has reduced chip area, thereby has reduced the manufacturing cost of whole integrated circuit.
Embodiment 1:
For a RC trigger-type esd protection circuit for integrated circuit, as shown in Figure 2, comprising: RC circuits for triggering 103 and esd clamp position device 104.Circuits for triggering 103 comprise two resistance 105 and 205, electric capacity 106, PMOS pipe 107 and a NMOS pipe 108.Resistance termination VDD power line 101 after the first resistance 105 and electric capacity 106 series connection, its electric capacity termination VSS power line 102; The tie point 109 of the first resistance 105 and electric capacity 106 connects the drain electrode of grid and the NMOS pipe 108 of PMOS pipe 107, the source electrode of PMOS pipe 107 connects VDD power line 101, the source electrode of NMOS pipe 108 connects VSS power line 102, and the tie point 110 after the gate interconnection of the drain electrode of PMOS pipe 107 and NMOS pipe 108 connects VSS power line 102 by the second resistance 205 when connecing the control end of esd clamp position device 104.The high pressure termination VDD power line 101 of clamps 104, the low pressure termination VSS power line 102 of clamps 104.
Operation principle:
As shown in Figure 4, be the analog simulation figure of these routine circuits for triggering under esd pulse condition, X-axis represents the time, Y-axis represents voltage.It is 10ns that this emulation adopts the rise time, the voltage source simulation esd pulse that the burst length is 220ns.As can be seen from the figure, in the time of VDD power line 101 end applied voltage, due to RC time delay, the voltage of potential point 109 rises and will be slower than the rising of power line 101 voltages, the gate source voltage Vgs of PMOS pipe 107 is reduced gradually, and in the time that Vgs is less than the threshold voltage vt of PMOS pipe 107, PMOS pipe 107 is opened, electric current flows into VSS power line 102 through the second resistance 205, thereby has raised the voltage of potential point 110; In the time that the voltage of potential point 110 is greater than the threshold voltage of NMOS pipe 108, NMOS pipe 108 is opened, electric current flows through from the first resistance 105, thereby drag down the voltage of potential point 109 and guarantee that PMOS pipe 107 is in opening, final formation positive feedback, to guarantee the high potential of potential point 110 and to open esd clamp position device 104, reaches the object of the ESD electric current of releasing.Known by analysis of simulation result; the triggered time of the RC trigger architecture being made up of the first resistance 105 and electric capacity 106 in this invention is only greater than the rise time (5～15ns) of esd pulse; just can guarantee that RC circuits for triggering 103 circuit can effectively trigger esd clamp position device 104 under ESD condition, thereby play the object of Protective IC.And the RC time constant of RC circuits for triggering 103 only needs about 10ns, with respect to the traditional circuit 200ns triggered time, the chip area of circuits for triggering is reduced to original approximately 1/10th.
As shown in Figure 5, be these routine circuits for triggering analog simulation figure in normal working conditions, X-axis represents the time, Y-axis represents voltage.It is 1ms that this emulation adopts the rise time, the voltage source simulation normal working voltage that the burst length is 22ms.As can be seen from the figure, because the time constant of RC circuits for triggering 103 is much smaller than the rise time of operating voltage, so in the time of the additional normal working voltage of VDD power line 101 end, the voltage of potential point 209 completely and VDD power line 101 equipotentials, the gate source voltage Vgs of PMOS pipe 107 is 0V, and PMOS pipe 107 is in off state, and the current potential of potential point 110 is almost identical with VSS power line 102, guarantee that esd clamp position device 104, in off state, can not affect the work of integrated circuit.
Embodiment 2:
Another kind provided by the invention, for the RC trigger-type esd protection circuit of integrated circuit, as shown in Figure 3, comprising: RC circuits for triggering 103 and esd clamp position device 104.Circuits for triggering 103 comprise two resistance 105 and 205, electric capacity 106, two PMOS pipes 107 and 207, two NMOS pipes 108 and 208.Electric capacity termination VDD power line 101 after the first resistance 105 and electric capacity 106 series connection, its resistance termination VSS power line 102; The tie point 109 of the first resistance 105 and electric capacity 106 connects the drain electrode of a PMOS pipe 107 and the grid of NMOS pipe 108, the source electrode of the one PMOS pipe 107 connects VDD power line 101, the source electrode of the one NMOS pipe 108 connects when tie point 110 after the grid of VSS power line 102, the one PMOS pipes 107 and the drain electrode interconnection of NMOS pipe 108 connects the grid of the 2nd PMOS pipe 207 and the 2nd NMOS pipe 208 and connects VDD power line 101 by the second resistance 205; The source electrode that the source electrode of the 2nd PMOS pipe 207 connects VDD power line 101, the two NMOS pipes 208 connects tie point 120 after the grid of VSS power line 102, the two PMOS pipes 207 and the gate interconnection of the 2nd NMOS pipe 208 and connects the control end of esd clamp position device 104.The high pressure termination VDD power line 101 of clamps 104, the low pressure termination VSS power line 102 of clamps 104.
This example is identical with the operation principle of embodiment 1, what difference was that potential point 110 exports is electronegative potential, add by after the 2nd PMOS pipe 207 and the 2nd NMOS pipe 208 inverters that form, potential point 120 output potentials are high potentials, thereby open esd clamp position device 104, guarantee that integrated circuit can not damaged by ESD.
Claims (3)
1. for a RC trigger-type esd protection circuit for integrated circuit, comprising: RC circuits for triggering (103) and esd clamp position device (104); Circuits for triggering (103) comprise two resistance (105 and 205), an electric capacity (106), a PMOS pipe (107) and a NMOS pipe (108); Resistance termination VDD power line (101) after the first resistance (105) and electric capacity (106) series connection, its electric capacity termination VSS power line (102); The tie point (109) of the first resistance (105) and electric capacity (106) connects the drain electrode of grid and the NMOS pipe (108) of PMOS pipe (107), the source electrode of PMOS pipe (107) connects VDD power line (101), the source electrode of NMOS pipe (108) connects VSS power line (102), and the tie point (110) after the gate interconnection of the drain electrode of PMOS pipe (107) and NMOS pipe (108) connects VSS power line (102) by the second resistance (205) when connecing the control end of esd clamp position device (104); The high pressure termination VDD power line (101) of clamps (104), the low pressure termination VSS power line (102) of clamps (104).
2. for a RC trigger-type esd protection circuit for integrated circuit, comprising: RC circuits for triggering (103) and esd clamp position device (104); Circuits for triggering (103) comprise two resistance (105 and 205), an electric capacity (106), two PMOS pipes (107 and 207), two NMOS pipes (108 and 208); Electric capacity termination VDD power line (101) after the first resistance (105) and electric capacity (106) series connection, its resistance termination VSS power line (102); The tie point (109) of the first resistance (105) and electric capacity (106) connects the drain electrode of a PMOS pipe (107) and the grid of NMOS pipe (108), the source electrode of the one PMOS pipe (107) connects VDD power line (101), the source electrode of the one NMOS pipe (108) connects VSS power line (102), and the tie point (110) after the drain electrode interconnection of the grid of a PMOS pipe (107) and NMOS pipe (108) connects when the 2nd PMOS pipe (207) and the 2nd NMOS manage the grid of (208) and connects VDD power line (101) by the second resistance (205); The source electrode of the 2nd PMOS pipe (207) connects VDD power line (101), the source electrode of the 2nd NMOS pipe (208) connects VSS power line (102), and tie point (120) after the gate interconnection of the grid of the 2nd PMOS pipe (207) and the 2nd NMOS pipe (208) connects the control end of esd clamp position device (104); The high pressure termination VDD power line (101) of clamps (104), the low pressure termination VSS power line (102) of clamps (104).
3. the RC trigger-type esd protection circuit for integrated circuit according to claim 1, is characterized in that, SCR device or conventional nmos device that described esd clamp position device (104) triggers for substrate.
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| Application Number | Priority Date | Filing Date | Title |
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| CN201410127313.3A CN103915828A (en) | 2014-03-31 | 2014-03-31 | RC triggered ESD protection circuit for integrated circuit |
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| CN201410127313.3A CN103915828A (en) | 2014-03-31 | 2014-03-31 | RC triggered ESD protection circuit for integrated circuit |
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Cited By (13)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105281307A (en) * | 2014-07-18 | 2016-01-27 | 美国亚德诺半导体公司 | Apparatus and methods for transient overstress protection with active feedback |
| CN105676039A (en) * | 2016-03-24 | 2016-06-15 | 北京大学 | Electrostatic static discharge generator circuit |
| CN106877303A (en) * | 2017-04-01 | 2017-06-20 | 唯捷创芯(天津)电子技术股份有限公司 | The power clamp electrostatic discharge circuit of tunable trigger voltage, chip and communication terminal |
| CN107527879A (en) * | 2016-06-21 | 2017-12-29 | 美国亚德诺半导体公司 | For the triggering of Active control and the apparatus and method of latch release IGCT |
| US10199369B2 (en) | 2016-03-04 | 2019-02-05 | Analog Devices, Inc. | Apparatus and methods for actively-controlled transient overstress protection with false condition shutdown |
| US10734806B2 (en) | 2016-07-21 | 2020-08-04 | Analog Devices, Inc. | High voltage clamps with transient activation and activation release control |
| CN112054815A (en) * | 2020-05-07 | 2020-12-08 | 珠海市杰理科技股份有限公司 | Wireless device, transceiving radio frequency circuit thereof and ESD protection circuit thereof |
| US10861845B2 (en) | 2016-12-06 | 2020-12-08 | Analog Devices, Inc. | Active interface resistance modulation switch |
| CN113452004A (en) * | 2020-03-26 | 2021-09-28 | 长鑫存储技术有限公司 | Electrostatic protection circuit and full-chip electrostatic protection circuit |
| CN114172137A (en) * | 2020-11-03 | 2022-03-11 | 台湾积体电路制造股份有限公司 | Circuit and method for electrostatic discharge protection |
| US11387648B2 (en) | 2019-01-10 | 2022-07-12 | Analog Devices International Unlimited Company | Electrical overstress protection with low leakage current for high voltage tolerant high speed interfaces |
| CN117914115A (en) * | 2024-03-15 | 2024-04-19 | 芯联先锋集成电路制造(绍兴)有限公司 | Electrostatic discharge protection circuit and integrated circuit chip |
| CN117914115B (en) * | 2024-03-15 | 2024-05-28 | 芯联先锋集成电路制造(绍兴)有限公司 | Electrostatic discharge protection circuit and integrated circuit chip |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20050285657A1 (en) * | 2004-06-25 | 2005-12-29 | Jeffrey Watt | Gate triggered ESD clamp |
| US20070206339A1 (en) * | 2006-03-03 | 2007-09-06 | Hynix Semiconductor Inc. | Protection circuit against electrostatic discharge in semiconductor device |
| CN101442869A (en) * | 2007-11-23 | 2009-05-27 | 上海华虹Nec电子有限公司 | Dynamic detection electrostatic protection circuit |
| US20100296212A1 (en) * | 2009-05-20 | 2010-11-25 | Industrial Technology Research Institute | Electrostatic discharge clamp circuit |
-
2014
- 2014-03-31 CN CN201410127313.3A patent/CN103915828A/en active Pending
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20050285657A1 (en) * | 2004-06-25 | 2005-12-29 | Jeffrey Watt | Gate triggered ESD clamp |
| US20070206339A1 (en) * | 2006-03-03 | 2007-09-06 | Hynix Semiconductor Inc. | Protection circuit against electrostatic discharge in semiconductor device |
| CN101442869A (en) * | 2007-11-23 | 2009-05-27 | 上海华虹Nec电子有限公司 | Dynamic detection electrostatic protection circuit |
| US20100296212A1 (en) * | 2009-05-20 | 2010-11-25 | Industrial Technology Research Institute | Electrostatic discharge clamp circuit |
Cited By (19)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105281307A (en) * | 2014-07-18 | 2016-01-27 | 美国亚德诺半导体公司 | Apparatus and methods for transient overstress protection with active feedback |
| CN105281307B (en) * | 2014-07-18 | 2019-03-08 | 美国亚德诺半导体公司 | Device and method for the transient error protection with positive feedback |
| US10199369B2 (en) | 2016-03-04 | 2019-02-05 | Analog Devices, Inc. | Apparatus and methods for actively-controlled transient overstress protection with false condition shutdown |
| CN105676039A (en) * | 2016-03-24 | 2016-06-15 | 北京大学 | Electrostatic static discharge generator circuit |
| CN105676039B (en) * | 2016-03-24 | 2018-07-03 | 北京大学 | A kind of electro-static discharging generator circuit |
| CN107527879B (en) * | 2016-06-21 | 2020-09-22 | 美国亚德诺半导体公司 | Apparatus and method for actively controlled trigger and latch release thyristors |
| CN107527879A (en) * | 2016-06-21 | 2017-12-29 | 美国亚德诺半导体公司 | For the triggering of Active control and the apparatus and method of latch release IGCT |
| US10177566B2 (en) | 2016-06-21 | 2019-01-08 | Analog Devices, Inc. | Apparatus and methods for actively-controlled trigger and latch release thyristor |
| US10734806B2 (en) | 2016-07-21 | 2020-08-04 | Analog Devices, Inc. | High voltage clamps with transient activation and activation release control |
| US11569658B2 (en) | 2016-07-21 | 2023-01-31 | Analog Devices, Inc. | High voltage clamps with transient activation and activation release control |
| US10861845B2 (en) | 2016-12-06 | 2020-12-08 | Analog Devices, Inc. | Active interface resistance modulation switch |
| CN106877303A (en) * | 2017-04-01 | 2017-06-20 | 唯捷创芯(天津)电子技术股份有限公司 | The power clamp electrostatic discharge circuit of tunable trigger voltage, chip and communication terminal |
| US11387648B2 (en) | 2019-01-10 | 2022-07-12 | Analog Devices International Unlimited Company | Electrical overstress protection with low leakage current for high voltage tolerant high speed interfaces |
| US11784488B2 (en) | 2019-01-10 | 2023-10-10 | Analog Devices International Unlimited Company | Electrical overstress protection with low leakage current for high voltage tolerant high speed interfaces |
| CN113452004A (en) * | 2020-03-26 | 2021-09-28 | 长鑫存储技术有限公司 | Electrostatic protection circuit and full-chip electrostatic protection circuit |
| CN112054815A (en) * | 2020-05-07 | 2020-12-08 | 珠海市杰理科技股份有限公司 | Wireless device, transceiving radio frequency circuit thereof and ESD protection circuit thereof |
| CN114172137A (en) * | 2020-11-03 | 2022-03-11 | 台湾积体电路制造股份有限公司 | Circuit and method for electrostatic discharge protection |
| CN117914115A (en) * | 2024-03-15 | 2024-04-19 | 芯联先锋集成电路制造(绍兴)有限公司 | Electrostatic discharge protection circuit and integrated circuit chip |
| CN117914115B (en) * | 2024-03-15 | 2024-05-28 | 芯联先锋集成电路制造(绍兴)有限公司 | Electrostatic discharge protection circuit and integrated circuit chip |
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