CN103914409B - Method for memory device with plurality of processors - Google Patents
Method for memory device with plurality of processors Download PDFInfo
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- CN103914409B CN103914409B CN201310004231.5A CN201310004231A CN103914409B CN 103914409 B CN103914409 B CN 103914409B CN 201310004231 A CN201310004231 A CN 201310004231A CN 103914409 B CN103914409 B CN 103914409B
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Abstract
The invention provides a method for a memory device with a plurality of processors. The memory device comprises a plurality of host interfaces and a plurality of memory chips. The method comprises the following steps: receiving a first address from a host; generating a first memory unit group address on the basis of the first address, wherein the first memory unit group address is used for accessing a first memory unit group, and a plurality of first memory units are comprised in each of the memory chips, a memory unit group is composed of a plurality of second memory units, and the memory units in each of the memory unit groups can be accessed in parallel.
Description
Technical field
The present invention relates to solid storage device（Solid Storage Device,SSD）, more particularly it relates to
The scheduling of multiple processors of storage device and address generate.
Background technology
Similar, the solid storage device with mechanical type hard disk（SSD）It is also the Large Copacity, non-volatile for computer system
Property storage device.Solid storage device is typically with flash memory（Flash）As storage medium.High performance solid storage device by with
In high-performance computer.High-performance computer generally has multiple central processing units（CPU, Central Process Unit）,
And each CPU may include multiple CPU cores.
As the memory capacity of solid storage device increases, the quantity of included flash chip in solid storage device
And/or memory capacity is consequently increased, the probability of existing defects is consequently increased in flash chip, and accesses flash memory in system
Occurring the probability of mistake during chip is also increasing.It is special in the U.S. of Publication No. US20100268985A1 referring to Fig. 1
In profit application, data reconstruction method and equipment in solid-state memory system are disclosed.In Fig. 1, storage device includes memorizer
Target（target）Group 510-513 and 520.Memory target is that the shared chip in nand flash memory encapsulation is enabled（CE,Chip
Enable）One or more logical blocks of signal（Logic Unit）.Each logical block has LUN（LUN,
Logic Unit Number）.One or more tube cores are may include in nand flash memory encapsulation（Die）.Typically, logical block pair
Should be in single tube core.Logical block may include multiple planes（Plane）.Multiple planes in logical block can be deposited parallel
Take, and the multiple logical blocks in nand flash memory chip can independently of one another perform order and report state.Can be from
http://www.micron.com/~/media/Documents/Products/Other%20Documents/ONFI3_
" the Open NAND Flash Interface Specification that 0Gold.ashx is obtained（Revision3.0）" in, there is provided
With regard to target（target）, logical block, LUN, plane（Plane）Implication, it is a part for prior art.
In Fig. 1, data register（0-n）（501-504）It is respectively coupled to memory target group 510-513.Data register
Device R500 is coupled to memory target group 520.Memory target group 520 stores redundant data.From memory target group 510-
513 and 520 data perform xor operation by data reconstruction circuit 650, so as to deposit in the case of an error in data, can
Mistake is corrected by data reconstruction circuit 650.Thus, using RAID（Redundant Array ofInexpensive
Disks）Technology, improves the reliability of solid storage device.
In fig. 2, flash memory of the U.S. Patent Application Publication of Publication No. US20080209116A1 with multiprocessor
Storage device.Storage device 200 includes host interface controller 204.Storage device 200 also includes multiple processor units 202
（1-n）.Each processor unit has special RAM.Special RAM is used for data cached and other data management functions.RAM
Also include flash-memory management data（FMD,Flash ManagementData）Table, it includes LBA（LBA,Logic
Block Address）With the state of flash memory.Processor unit 202（1-n）It is low-cost processes device.Each processor unit tool
There is special bus 205（1-n）It is coupled to flash memory 201（1-n）.Processor unit is used to process the order from main frame.In Fig. 2
In, processor unit 202（1-n）With flash memory 201（1-n）It is one-to-one relationship, in other embodiments, processor unit
Can otherwise couple between flash memory.Data flow control 203 is connected to host interface controller 204 by bus, number
Determine which flash memory passage used according to stream controller 203, i.e. which processor unit used.Data flow control 203 can
Sequential processing access request, will first request be sent to processor 202（1）, next request is sent to into processor 202
（2）.Data flow control 203 can also randomly choose the processor 202 for processing request（1-n）.In other embodiments, alternatively
A certain processor unit distributes specific flash memory space.For example, it is processor 202（1）Distribute the sudden strain of a muscle for storing routine data
Nonresident portion, and by processor 202（2）Distribute the flash parts for storing Backup Data.By providing many in storage device
Individual processor, improves the I/O request disposal ability and autgmentability of storage device.
However, or order random in prior art needs each processor to the mode of processor allocation request
The access request of whole flash memory address space is processed, this will cause big resource to use expense or conflict.And at each
The mode of the data space of reason device distribution special-purpose, then will cause during system operation, and the utilization rate of each processor is uneven
Weighing apparatus.
The content of the invention
According to the first aspect of the invention, there is provided a kind of storage device, including HPI, multiple memory chips；
Each memory chip includes more than first memory element, and by more than second memory element memory cell group is constituted, and each is deposited
Memory element in storage unit group can concurrent access；The data storage device also includes memory cell group address generating circuit,
The first memory element group address is generated from the first address that HPI is received for basis, wherein first memory cell group
Address is used to access the first memory cell group.
Each of multiple memory element in storage device according to the first aspect of the invention, wherein each storage chip
It is logical block, tube core or plane.
Storage device according to the first aspect of the invention, wherein the memory cell group address generating circuit is by described
One address obtains the first business and the first remainder divided by the quantity of the memory cell group in data storage device, and first business makees
For the first memory element group address.
Storage device according to the first aspect of the invention, also including multiple processors, in the plurality of processor
One processor receives the first memory element group address, and the first memory element group address is used to deposit to described first
The access of storage unit group.
Described storage device according to the first aspect of the invention, wherein by first remainder relative to the plurality of
The quantity modulus of processor, obtain the first mould, and based on first mould first processor is selected.
Storage device according to the first aspect of the invention, wherein selecting described first with round robin or random fashion
Processor.
Storage device according to the first aspect of the invention, it is described for obtaining also including memory cell group counting circuit
First quantity of the memory element in data storage device, and determined in the data storage device based on first quantity
The quantity of memory cell group.
Storage device according to the first aspect of the invention, also including first circuit board, arranges on the first circuit board
There are multiple storage chips；Wherein described memory cell group counting circuit obtains the described of the memory element on the first circuit board
First quantity.
Storage device according to the first aspect of the invention, also including first circuit board and second circuit board, described first
Multiple storage chips are disposed with circuit board, multiple storage chips are disposed with the second circuit board；
Wherein the memory cell group counting circuit obtains the storage on the first circuit board and the second circuit board
First quantity of unit.
Storage device according to the first aspect of the invention, wherein each memory cell group include N number of memory element, wherein
First quantity obtains the quantity of the memory cell group in the data storage device divided by N.
Storage device according to the first aspect of the invention, wherein multiple memory element bags of first memory cell group
It is contained in first memory chip.
Storage device according to the first aspect of the invention, wherein the access to first memory cell group includes
Multiple or whole memory element in first memory cell group.
According to the second aspect of the invention, there is provided a kind of server, including storage according to the first aspect of the invention
Equipment, the storage device is coupled with the server by the HPI.
According to the third aspect of the invention we, there is provided a kind of method for storage device, the storage device includes many
Individual HPI and multiple memory chips, methods described includes：Receive from the first address of main frame；Based on described first
Address generates the first memory element group address, wherein the first memory element group address is used to access the first memory cell group,
And wherein each memory chip includes more than first memory element, and by more than second memory element memory element is constituted
Group, the memory element in each memory cell group can concurrent access.
Each of multiple memory element in method according to the third aspect of the invention we, wherein each storage chip is pipe
Core, logical block or plane.
Method according to the third aspect of the invention we, wherein it is by will be described to generate the first memory element group address
First address obtains the first business and the first remainder, first business divided by the quantity of the memory cell group in data storage device
As the first memory element group address.
Method according to the third aspect of the invention we, wherein the storage device also includes multiple processors, methods described
Also include：The first memory element group address is received by the first processor in the plurality of processor, and by described first
Memory element group address is used for the access to first memory cell group.
Method according to the third aspect of the invention we, wherein by first remainder relative to the plurality of processor number
Amount modulus, obtain the first mould, and based on first mould first processor is selected.
Method according to the third aspect of the invention we, wherein selecting described first to process with round robin or random fashion
Device.
Method according to the third aspect of the invention we, also including the of the memory element obtained in the data storage device
One quantity, and the quantity of the memory cell group in the data storage device is determined based on first quantity.
Method according to the third aspect of the invention we, wherein the storage device also include first circuit board, described first
Multiple storage chips are disposed with circuit board；And wherein obtain the first quantity of memory element in the data storage device
To obtain first quantity of the memory element on the first circuit board.
Method according to the third aspect of the invention we, wherein the storage device also includes first circuit board and second circuit
Plate, is disposed with multiple storage chips on the first circuit board, multiple storage chips are disposed with the second circuit board；And
The first quantity of the memory element in the data storage device is wherein obtained to obtain the first circuit board and described second
First quantity of the memory element on circuit board.
Method according to the third aspect of the invention we, wherein each memory cell group include N number of memory element, wherein described
First quantity obtains the quantity of the memory cell group in the data storage device divided by N.
Method according to the third aspect of the invention we, wherein multiple memory element of first memory cell group are contained in
In first memory chip.
The method of method according to the third aspect of the invention we, wherein the access bag to first memory cell group
Include the multiple or whole memory element in first memory cell group.
Description of the drawings
When reading together with accompanying drawing, by reference to the detailed description of illustrative embodiment, will be best understood by below
The present invention and preferred use pattern and its further objects and advantages, wherein accompanying drawing includes：
Fig. 1 is the structured flowchart of the storage device according to prior art；
Fig. 2 is the structured flowchart of another storage device according to prior art；
Fig. 3 is the front view of storage device according to an embodiment of the invention；
Fig. 4 A-4E are the flash chips and control circuit of the circuit daughter board of storage device according to an embodiment of the invention
The schematic diagram of connected mode；
Fig. 5 shows the schematic diagram of the organizational form of the memory element of storage device according to an embodiment of the invention；
Fig. 6 shows the figure of the address mapping relation for implementing embodiments of the invention；
Fig. 7 shows the figure for implementing the memory element group address with the mapping relations of processor of embodiments of the invention；
Fig. 8 is the theory diagram according to storage device of the present invention；
Fig. 9 is the block diagram of storage system according to an embodiment of the invention；And
Figure 10 A, 10B are the flow charts of processing method according to an embodiment of the invention.
Specific embodiment
Fig. 3 is the front view of storage device according to an embodiment of the invention.Storage device shown in Fig. 3 includes that circuit is female
Plate 400.Circuit motherboard 400 is the circuit board with the high card forms of PCIE half, and it can be connected to computer by PCIE slots.
Circuit daughter board 410,420,430 and 440 is disposed with circuit motherboard 400.In one embodiment, circuit daughter board 410,420,
Flash chip 411-413,421-423,431-433 and 441-443 are respectively disposed with 430 and 440 so that circuit daughter board
410th, 420,430 and 440 memory capacity is provided to storage device.Although figure 3 illustrates in the every of circuit daughter board 410-440
Three pieces of flash chips of individual upper placement, one of ordinary skill in the art will recognize can also place it on circuit daughter board 410-440
The flash chip of his quantity, for example, on circuit daughter board 410 on the surface relative with the surface that flash chip 411-413 is located
Place flash chip.One of ordinary skill in the art will additionally appreciate can be connected to circuit motherboard by the circuit daughter board of varying number
400。
Although figure 3 illustrates the storage device with PCIE interfaces including flash chip, art technology
Personnel will present invention can be suitably applied to the various electronic with other functions, it is realized that it is only a kind of citing, and can lead to
Cross various interface modes and be coupled to computer, multiple interfaces include but is not limited to SATA（SerialAdvanced Technology
Attachment, Serial Advanced Technology Attachment）、USB（Universal Serial Bus, USB (universal serial bus)）、PCIE
（Peripheral Component Interconnect Express, quick peripheral assembly interconnecting）、SCSI（Small
Computer System Interface, small computer system interface）、IDE（IntegratedDrive
Electronics, integrated drive electronics）Deng.Also, it is suitable for the other kinds of storage beyond including flash memory
Chip, for example, phase transition storage, Memister, ferroelectric memory etc..
Control circuit 660 is there also is provided on circuit motherboard 400, to control to circuit daughter board 410,420,430 and 440
On flash chip access, and process from computer interface command.Such as DRAM is there also is provided on circuit motherboard 400
（Dynamic Random Access Memory, dynamic RAM）Memorizer 662,664,666 and 668.Deposit
Reservoir 662,664,666 and 668 can be coupled to control circuit 660.Control circuit 660 can be FPGA（Field-
Programmable gate array, field programmable gate array）、ASIC（Application Specific
Integrated Circuit, application specific integrated circuit）Or the form of its combination.Control circuit 660 can also include place
Reason device or controller.One, two or more processor cores are may include in control circuit 660, each processor core is used to control
System accesses the part or all of of multiple circuit subcards.Each processor core can also be used for access or control circuit subcard on it is many
Individual flash chip it is part or all of.
Adapter 628 and 629 is there also is provided on circuit motherboard 400 as shown in Figure 3.May be used also by adapter 628 and 629
Respectively circuit daughter board will be connected to into circuit motherboard 400.So as in the electricity with the high card forms of PCIE half as shown in Figure 3
On road motherboard 400, up to 6 pieces circuit daughter boards can be connected.Circuit daughter board 410 is connected to circuit motherboard by flexible PCB 640
400.Circuit daughter board 420 is connected to circuit motherboard 400 by flexible PCB 642.Circuit daughter board 430 passes through flexible PCB
644 are connected to circuit motherboard 400.Circuit daughter board 440 is connected to circuit motherboard 400 by flexible PCB 646.With the side being similar to
Formula, circuit daughter board is connected to circuit motherboard 400 also by flexible PCB via adapter 628 or 629.
Multiple circuit daughter boards placement parallel to each other on circuit motherboard 400.The long edge circuit motherboard of multiple circuit subcards
400 minor face is placed, and the minor face of multiple circuit daughter boards is placed along the long side of circuit motherboard 400.The minor face of multiple circuit daughter boards is big
Place along same straight line on body.Circuit daughter board 410 is relative with 420 head and the tail, and the sky that shared flexible PCB 640,642 is formed
Between, so as to form circuit daughter board group.Circuit daughter board 430 is relative with 440 head and the tail, and the shared formation of flexible PCB 644,646
Space, so as to form circuit daughter board group.Similarly, also head and the tail are relative to be connected to circuit daughter board of the adapter 628 with 629, and shape
Into circuit daughter board group.There can be space between multiple circuit daughter boards and circuit motherboard, other electronics units can be arranged within this space
Part.
In a preferred embodiment, heat abstractor is also provided, for by the flash chip on multiple circuit daughter boards and/or control
Heat transfer produced by circuit processed 660 and/or memorizer 662,664,666 and 668 is to outside storage device.
Fig. 4 A-4 E are the flash chips and control electricity of the circuit daughter board 410 of storage device according to an embodiment of the invention
The schematic diagram of the connected mode on road 660.Circuit daughter board 420-440 can be connected to control circuit 660 by the same manner.In order to promote
Enter the concurrency of the operation of multiple flash chips, and save the IO for controlling the control circuit 660 required for multiple flash chips
Resource, the multiple flash chips on circuit daughter board 410 are arranged in multiple passages.One or many is disposed with each passage
Individual flash chip, the multiple flash chip shared datas and/or controlling bus in each passage, and in order to access each
Flash chip, the chip of the multiple flash chips in each passage is enabled（Chip Enable,CE）Port, can be by control circuit
660 are individually controlled.
Referring to Fig. 4 A, 3 passages are disposed with circuit daughter board 410.Flash chip 411,414 is included in first passage,
And control circuit 660 is coupled to by the bus 490 for sharing.Control circuit 660 can be with independently controlled flash chip 411,414
CE ports.Flash chip 412,415 is included in the second channel, and is coupled to control circuit by the bus 492 for sharing
660.Control circuit 660 can be with the CE ports of independently controlled flash chip 412,415.Flash chip 413,416 is included in
In triple channel, and control circuit 660 is coupled to by the bus 494 for sharing.Control circuit 660 can be with independently controlled flash memory core
The CE ports of piece 413,416.
Alternatively, there can be the flash chip of other quantity on each passage.Referring to Fig. 4 B, flash chip 411,412 with
413 are included in first passage, and are coupled to control circuit 660 by the bus 490 for sharing.Control circuit 660 can be independent
The CE ports of ground control flash chip 411,412 and 413.Flash chip 414,415 and 416 is included in the second channel, and leads to
Cross shared bus 494 and be coupled to control circuit 660.Control circuit 660 can with independently controlled flash chip 414,415 with
416 CE ports.
Still alternatively, there can be the flash chip of varying number on each passage.Referring to Fig. 4 C, flash chip 411,
414 are included in first passage, and are coupled to control circuit 660 by the bus 490 for sharing.Control circuit 660 can be independent
The CE ports of ground control flash chip 411,414.Flash chip 412,415 include in the second channel, and by share it is total
Line 492 is coupled to control circuit 660.Control circuit 660 can be with the CE ports of independently controlled flash chip 412,415.Flash memory
Chip 413 is included in third channel, and is coupled to control circuit 660 by bus 494.Control circuit 660 can control to dodge
Deposit the CE ports of chip 413.Notice in figure 4 c, flash chip 416 is not provided.Again it was noticed that in figure 4 c, first
In passage and second channel, 2 flash chips are disposed with, and in third channel, are only disposed with 1 flash chip, i.e. each
Flash chip with varying number on passage.Although it is pointed out that there is the flash memory of varying number on each passage
Memory capacity on chip, but each passage can be the same or different.When the flash chip 411-415 in Fig. 4 C has phase
With memory capacity when, the memory capacity on third channel is the half of the memory capacity of first passage.Flash memory can also be provided
Chip 413 so that its memory capacity is two times of flash chip 411,412,414 or 415, so that depositing on each passage
Storage capacity is identical.
Although still it is pointed out that in the embodiment of Fig. 4 C, not including flash chip 416, in phase therewith
In corresponding circuit daughter board, it is preferable that provide and the circuit daughter board identical interface arrangement for including 6 flash chips.I.e., although
Including the circuit daughter board of 6 flash chips, it is not necessary to provide the lead of the CE ports for being coupled to flash chip 416 in the interface,
But it is favourable to provide identical interface arrangement for various different circuit daughter boards, and this will allow the connection in circuit motherboard 400
Different circuit daughter boards are coupled on device, so as to improve the motility of storage device, and the installation of storage device 400 is simplified
Journey, because the circuit daughter board 410 with particular memory capacity or flash chip quantity is not limited to connect installed in specific motherboard
On device.
In one embodiment, in the interface of circuit daughter board 410, there is provided 3 leads, every lead is transmitted by it
1 flash chip or 2 sudden strains of a muscle are disposed with a passage in signal of telecommunication instruction first passage, second channel and third channel
Deposit chip.One of ordinary skill in the art may also be appreciated that the mode of the configuration of other indicating circuit daughter boards 410.For example, in electricity
In the interface of way plate 410, there is provided 2 leads, it can transmit " 00 ", " 01 ", " 10 " and " 11 " four kinds of different states,
A kind of particular configuration of each condition indication circuit daughter board 410.Indicated by service wire, can also be on circuit daughter board 410
Storage chip quantity, or the memory capacity provided on circuit daughter board 410, or on circuit daughter board 410 it is included logical
Road quantity is configured with the flash chip in each passage（Quantity and/or memory capacity）.
Referring to Fig. 4 D, flash chip 411,414 is included in first passage, and is coupled to control by the bus 490 for sharing
Circuit processed 660.Control circuit 660 can be with the CE ports of independently controlled flash chip 411,414.Flash chip 412 is included in
In second channel, and control circuit 660 is coupled to by bus 492.Control circuit 660 can control the CE of flash chip 412
Port.Flash chip 413 is included in third channel, and is coupled to control circuit 660 by bus 494.Control circuit 660 can
To control the CE ports of flash chip 413.
Referring to Fig. 4 E, flash chip 411 is included in first passage, and is coupled to control circuit 660 by bus 490.
Control circuit 660 can be with the CE ports of independently controlled flash chip 411.Flash chip 412 is included in the second channel, and leads to
Cross bus 492 and be coupled to control circuit 660.Control circuit 660 can be with the CE ports of independently controlled flash chip 412.Flash memory
Chip 413 is included in third channel, and is coupled to control circuit 660 by bus 494.Control circuit 660 can be independently
The CE ports of control flash chip 413.
Fig. 5 shows the schematic diagram of the organizational form of the memory element of storage device according to an embodiment of the invention.
Logical block 460-472 in storage device is organized as into memory cell group.Logical block is can independently hold in flash chip
The memory element of line command and report state.For example, logical block can be a tube core in flash chip.In other configurations
In, logical block can also include multiple tube cores.Each memory cell group includes N number of logical block, wherein L logical block
For storing user data, and M logical block is used for redundant data, and N=L+M, N, L and M are natural number.Art
Technical staff will recognize the quantity by adjusting L and M, it is possible to provide different fault-tolerant abilitys.For example, as L=M=1, at each
In memory cell group, 1 logical block is used to store user data, and another 1 logical block is used to store Backup Data, when with
When mistake occurs in user data, the user data for mistake occur is recovered using Backup Data.In another example, L=7, and M=
1, the mode for adopting even-odd check provides protection for user data.Can also be deposited to improve using other fault-tolerant encoding modes
The reliability of storage equipment.Control circuit 660 is controlled to memory cell group and the wherein operation of each logical block, to memory element
The EDC error detection and correction of the data of group is also implemented by control circuit 660.
In a preferred embodiment, the N number of logical block for forming memory cell group is located at same flash chip.So that depositing
When there is irrecoverable error in storage unit group, can less cost remove or replace and wrong flash chip occur.Another
In embodiment, N number of logical block of memory cell group is formed from multiple or N number of circuit daughter board（410-440）So that in storage
When some logical block failures or service life in unit group will be most, can be by changing circuit daughter board（410-440）And it is real
Now repair.
By the way that logical block is organized as into memory cell group, and with memory cell group as unit store user data and
Redundant data, can improve the reliability of storage device.Also, multiple logical blocks can concurrent access, thus, with memory cell group
The readwrite performance that data do not interfere with storage device is write and read for unit.One of ordinary skill in the art will be, it is realized that also may be used
So that multiple planes or tube core are organized as into memory cell group.
However, main frame accesses storage device 400 with continuous linear address space, so that by from the linear of main frame
Address（Logical address）Be mapped to each memory cell group, will logical address be converted to memory element group address.Fig. 6 is to illustrate
The schematic diagram of address mapping relation according to an embodiment of the invention.In the disclosed embodiment, storage device 400 includes
M memory cell group, each memory cell group includes n data block.Storage device 400 is to the master using the storage device 400
Machine is presented with 0 ~ (nm-1)（In units of 4KB/8KB/16KB data blocks）The logical address space of address realm.Logic list
Unit may include multiple memory blocks, and each memory block may include multiple pages, and typically, one page is 4KB or 8KB or 16KB sizes.For
Clear, the Method of Data Organization being indifferent to here inside logical block.In one embodiment, logical address is LBA
（Logic BlockAddress, LBA）
Table 540 shows storage device 400 and presents the address with 0 ~ (nm-1) in units of data block to main frame
Scope.And table 550 then show it is corresponding with each logical address of table 540, be presented as memory element group address with storage
The address format of unit group bias internal.In table 550, lateral attitude corresponds to each memory cell group, and lengthwise position is corresponded to
Each memory cell group bias internal in memory cell group.When each memory cell group include n data block when, table 550 indulge
Include n different memory cell group bias internal to position.For example, for the logical address 0 in table 540, in being mapped as table 550
No. 0 memory cell group and No. 0 memory cell group bias internal.And the logical address 1 in table 540, No. 1 be mapped as in table 550
Memory cell group and No. 0 memory cell group bias internal.Logical address m in table 540, No. 0 memory element being mapped as in table 550
Group and No. 1 memory cell group bias internal.Logical address nm-1 in table 540, the m-1 memory cell groups being mapped as in table 550
With n-1 memory cell group bias internals.Table 540 can be expressed as with the mapping relations of table 550, and logical address is set divided by storage
The number of memory cell group in standby 400, the remainder of gained is used as memory element group address, and the business of gained is used as memory cell group
Bias internal.Circuit daughter board of the memory element group address corresponding to storage device 400（410-440）One memory cell group of formation
Specific flash memory chip specific multiple logical blocks（Or tube core）.And memory cell group bias internal is indicated in memory cell group
Interior linear address space.
The logical address in table 540 can be mapped as into the memory element group address in table 550 and storage using divider
Unit group bias internal.Also mapping can be realized using the mode of look-up table.And when using look-up table, can in logical address,
To in the mapping of memory element group address and memory cell group bias internal, using other mapping relations.Can be in storage device
By to circuit daughter board when 400 startups or the configuration of storage device 400 change（410-440）Enumerating for configuration and send out
The quantity for storing the logical block of user data in the quantity and memory cell group of existing memory cell group determines storage
The size of the logical address space that equipment 400 is presented to main frame, and it is single with storage to memory element group address to set up logical address
The mapping relations of tuple bias internal.
In an embodiment of the present invention, logical block is organized as into memory cell group, and with memory cell group as unit
Storage user data and redundant data, and control circuit 660 is visited using memory element group address with memory cell group bias internal
Ask corresponding memory cell group.In one embodiment, control circuit 660 includes two processors.By to memory cell group
Access request is favourable to conduct interviews to memory cell group to two processors with approximately equalised probability assignments.And point
It is favourable that the memory cell group of two processors of dispensing is separate, can so reduce resource and use expense or conflict.Institute
Category art personnel by, it is realized that control circuit 660 may include the processor of other quantity, by the access to memory cell group
Request is also advantageous to the processor of other quantity with approximately equalised probability assignments with conducting interviews to memory cell group.
Fig. 7 shows the figure for implementing the memory element group address with the mapping relations of processor of embodiments of the invention.
As an example, control circuit 660 includes two processors in the embodiment of Fig. 7, and its processor numbering is respectively 0 and 1.In Fig. 7
Table 560 row 562, give numbering be 0 or 1 processor relative to multiple memory cell groups the method for salary distribution.Specifically,
Send the request for accessing memory element group address 0 to processor 0 to be processed, the request of memory element group address 1 will be accessed
Send processor 1 to be processed, send the request for accessing memory element group address 2 to processor 0 and process, and will access
The request of memory cell group m-1 sends processor 1 to and processes（Here, m is even number）.In other words, by memory element group address
Quantity modulus to processor（Or memory element group address divided by processor quantity obtained by remainder）, it is as a result right as processing
Should memory element group address request processor numbering.One of ordinary skill in the art will be, it is realized that other can be adopted
Mode will request assignment to one of multiple processors corresponding to memory cell group.For example, by it is multiple request in order or wheel
The mode of inquiry is sent to one of multiple processors, or by multiple requests be sent at random multiple processors it
Fig. 8 is the theory diagram of storage device of the invention.The control circuit 660 of storage device is coupled to circuit
Plate 410,420.Circuit daughter board 410,420 is coupled to control circuit 660 each via dedicated buss.Can also wrap in storage device
Include more circuit daughter boards.Control circuit 660 is also coupled to main frame 720 by HPI 720.Control circuit 660 also includes
Processor 726,728, storage unit count circuit 724 and memory cell group address generating circuit 722.
Memory unit address generative circuit 724 obtains the configuration of circuit daughter board 410,420.Specifically, memory unit address
Generative circuit 724 obtains the quantity of the logical block of each of circuit daughter board 410,420, and calculates all in storage device
The total amount of the logical block that circuit daughter board 410,420 has, is designated as S.Further, storage unit count circuit 724 is calculated and deposited
The linear address that storage equipment is presented to main frame 710（Logical address）The scope in space.In one example, each memory cell group
Including N=L+M logical block, wherein L logical block is used to store user data, and M logical block is used to store redundancy
Data.So, in the case where every logical block includes b data block, the linear address that storage device presents to main frame 710
（Logical address）Spatial dimension is 0 ~ S*L*b/N（In units of data block）.Storage unit count circuit 724 also calculates storage
The quantity of the memory cell group of equipment, such as, by calculating S/N, obtain the quantity of the memory cell group of storage device, and should
Quantity S/N is sent to memory cell group address generating circuit 722.
When the access request from main frame is received, wherein included logical address is extracted, the logical address is sent out
Give memory cell group address generating circuit 722.Memory cell group address calculating circuit is by the logical address divided by memory element
Quantity S/N of group, resulting remainder Q is that memory element group address, i.e. data block corresponding to the logical address are located at storage
Unit group address is in the memory cell group of Q.Further, using the logical address divided by the business obtained by S/N as memory cell group
Bias internal, and complete access request.Memory cell group bias internal indicates the linear address space in memory cell group.At one
In example, by for the address mapping table of memory cell group, will reflect for the memory cell group bias internal of the memory cell group
Penetrate be data block for the memory cell group physical address.
In one embodiment, the data block size corresponding to the logical address of the access request of main frame, different from storage
Data block size in unit group.For example, the corresponding data blocks of LBA from main frame are 4KB, and the memory element of storage device
The data block of group（For example, page）For 8KB, then, the LBA is moved to right one by memory cell group address generating circuit 722, to give up
The lowest order of the LBA, then by the LBA after moving to right divided by memory cell group quantity S/N, the remainder Q of result is single as storage
First group address, using the business of result as memory cell group bias internal.Similarly, when the corresponding data blocks of LBA are 4KB, and store
When the data block of the memory cell group of equipment is 16KB, the LBA is moved to right two by memory cell group address generating circuit 722, then
By the LBA after moving to right divided by memory cell group quantity S/N.
The memory element group address of generation is sent to processor 726 or is processed by memory cell group address generating circuit 722
Device 728.In a preferred embodiment, for the memory element group address of even number processor 726 will be sent to, and by depositing for odd number
Storage unit group address is sent to processor 728.So that processor 726 processes respectively the visit to different memory cell groups from 728
Request is asked, also, the probability that processor 726 processes access request with 728 is substantially the same.Can have other modes to access please
Ask and be sent to processor 726 and 728.For example, when the lowest order of the memory element group address for calculating is 0, by the storage list
First group address is sent to processor 726, and when the lowest order of the memory element group address for calculating is 1, by the memory element
Group address is sent to processor 728.Can also by memory element group address divided by processor quantity, according to the remainder of gained,
Memory element group address is sent to into corresponding processor, for example, when remainder is 0, memory cell group processor is sent to into
726（No. 0 processor）, and when remainder is 1, memory element group address is sent to into processor 728（No. 1 processor）.Another
In one embodiment, can be according to the sequencing of access request, being sequentially assigned to processor 726 or 728, or will storage
Unit group address is randomly assigned to processor 726 or 728.
In another embodiment, control circuit 410 includes the processor of three or more.One of ordinary skill in the art will
Recognizing to adopt to memory element group address relative to processor quantity modulus, and the remainder based on gained, will storage it is single
First group address is sent to the processor corresponding with the remainder.Can also be using being randomly assigned or the mode such as order-assigned, choosing
Select the processor for processing access request.
In still another embodiment, it is not based on memory cell group address computation and receives the memory element group address
Processor, but based on the logical address from HPI 720（Or LBA）Calculate the place for receiving respective memory unit group address
Reason device.
The memory element group address for receiving is used for processor 726 access to corresponding memory cell group with 728.By
Include multiple logical blocks in each memory cell group, processor 726 and 728 also calculates data in the multiple of memory cell group
Distribution between logical block.In one example, the data block size corresponding to the access request from HPI 720,
Different from the data block size for performing storage/access operation in multiple logical blocks of memory cell group, in the case, place
Reason device 726 and 728 can by the data merged block corresponding to the multiple access requests from main frame, with write storage unit group, or
Person will read corresponding data from memory cell group, and it is merged with the data corresponding to access request, then write storage unit
Group.In the case where memory cell group includes N number of logical block, the data after merging are write into N number of patrolling in fault-tolerant encoding mode
In collecting unit.In another example, the data that the process of processor 726 and 728 will read from memory cell group are therefrom extracted
Go out the data corresponding to the access request from HPI 720, and be sent to main frame 710.
Fig. 9 is the block diagram of storage system according to an embodiment of the invention.Storage system bag according to embodiments of the present invention
Include main frame 710 and storage device 400.One or more storage devices 400 can be connected to main frame 710.In one example, deposit
Storage equipment 400 is connected to main frame 710 by PCIE interfaces.Storage device 400 can also be coupled to into master with various other interfaces
Machine 710, multiple interfaces include but is not limited to SATA, USB, PCIE, SCSI, IDE, FC etc..
Figure 10 A, 10B are the flow charts of processing method according to an embodiment of the invention.In storage device run duration, connect
Receive the access request from main frame（1010）.The memory cell group address generating circuit 722 of storage device is based in access request
Logical address（Such as LBA）, generate memory element group address（1020）.In one example, by with logical address divided by
The quantity of the memory cell group of storage device, using the remainder of gained as memory element group address.（Obtain memory cell group number
Amount）Logical address can also be mapped as into memory element group address by the way of such as look-up table.In selecting storage device
One of multiple processors, by memory element group address selected processor is sent to（1030）.In one example, based on depositing
Storage unit group address carrys out selection processor to processor quantity modulus.In another example, by depositing corresponding to access request
Storage unit group address order is randomly sent to one of multiple processors.In still another example, based on access request
In logical address selection processor is come to processor quantity modulus.Next, selected processor is by the storage for receiving
Unit group address is used for the access to corresponding memory cell group（1040）.
The quantity of memory cell group, electric on a storage device in obtain storage device（1050）Afterwards, storage device is obtained
In memory element（For example, logical block）Quantity（1050）.In one example, the detection of control circuit 660 is coupled to and is deposited
The configuration of multiple circuit daughter boards of storage equipment, and the quantity of the memory element of each circuit daughter board is obtained, to each circuit daughter board
Memory element quantity summation, obtain the number of memory cells of storage device.Next, calculating the storage list in storage device
The quantity of tuple（1070）.When each memory cell group includes N=M+L memory element, by the storage list in storage device
Divided by N, the business of gained is the quantity of the memory cell group of storage device to quantity S of unit.And the memory element obtained by preserving
The quantity of group（1080）.The quantity of the memory cell group for calculating can be saved in the nonvolatile memory of storage device,
So that storage device is gone up after electricity next time, without the need for execution step 1050 again step 1080 is arrived.When the number of memory cells of storage device
After amount changes（For example, the circuit subcard for being coupled to storage device changes, or the memory chip on circuit subcard
Break down）, step 1050- step 1080 is re-executed, with the number of the memory cell group in the storage device after being changed
Amount.
The description of this invention is presented for the purpose for illustrating and describing, and be not intended to disclosed shape
Formula limit limits the present invention.To one of ordinary skill in the art, many adjustment and change are obvious.
Claims (5)
1. a kind of method for storage device, the storage device includes multiple main frames interface and multiple memory chips,
The storage device also includes multiple processors, and methods described includes：
The access request from main frame is received, the access request includes logical address；
By the logical address divided by the quantity of the memory cell group in storage device, the first business and the first remainder are obtained, it is described
First remainder is used as the first memory element group address, wherein the first memory element group address is used to access the first memory element
Group, and wherein each memory chip includes more than first logical block, constitutes storage by more than second logical block single
Tuple, the logical block in each memory cell group can concurrent access；
By first remainder relative to the quantity modulus of the plurality of processor, the first mould is obtained, selected based on first mould
Select first processor；And
The first processor receives the first memory element group address, and the first processor is stored described first
Unit group address is used for the access to first memory cell group.
2. method according to claim 1, also including the first quantity for obtaining the logical block in the storage device, and
The quantity of the memory cell group in the storage device is determined based on first quantity.
3. method according to claim 2, wherein the storage device also includes first circuit board, the first circuit board
On be disposed with multiple storage chips；And wherein obtain logical block in the storage device the first quantity it is described to obtain
First quantity of the logical block on first circuit board.
4. method according to claim 2, wherein the storage device also includes first circuit board and second circuit board, institute
State and be disposed with first circuit board multiple storage chips, multiple storage chips are disposed with the second circuit board；And wherein
The first quantity of logical block in the storage device is obtained to obtain on the first circuit board and the second circuit board
Logical block first quantity.
5. the method according to one of claim 1-4, wherein multiple logical blocks of first memory cell group are included
In first memory chip.
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