CN103904125A - Thin-film transistor - Google Patents

Thin-film transistor Download PDF

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Publication number
CN103904125A
CN103904125A CN201210573688.3A CN201210573688A CN103904125A CN 103904125 A CN103904125 A CN 103904125A CN 201210573688 A CN201210573688 A CN 201210573688A CN 103904125 A CN103904125 A CN 103904125A
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CN
China
Prior art keywords
thin
layer
film transistor
atom
film transistors
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Pending
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CN201210573688.3A
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Chinese (zh)
Inventor
曾坚信
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Hongfujin Precision Industry Shenzhen Co Ltd
Hon Hai Precision Industry Co Ltd
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Hongfujin Precision Industry Shenzhen Co Ltd
Hon Hai Precision Industry Co Ltd
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Priority to CN201210573688.3A priority Critical patent/CN103904125A/en
Publication of CN103904125A publication Critical patent/CN103904125A/en
Pending legal-status Critical Current

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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76Unipolar devices, e.g. field effect transistors
    • H01L29/772Field effect transistors
    • H01L29/78Field effect transistors with field effect produced by an insulated gate
    • H01L29/786Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78696Thin film transistors, i.e. transistors with a channel being at least partly a thin film characterised by the structure of the channel, e.g. multichannel, transverse or longitudinal shape, length or width, doping structure, or the overlap or alignment between the channel and the gate, the source or the drain, or the contacting structure of the channel
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/10Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/1025Channel region of field-effect devices
    • H01L29/1029Channel region of field-effect devices of field-effect transistors
    • H01L29/1033Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Thin Film Transistor (AREA)

Abstract

The invention provides a thin-film transistor comprising a grid electrode, a channel layer, a grid insulating layer which is arranged between the grid electrode and the channel layer, and a source electrode and a drain electrode which are arranged on the opposite two sides of the channel layer and respectively contacted with the channel layer. A first atom capture layer is clamped between the channel layer and the grid insulating layer. The thin-film transistor is not liable to be influenced by the external environment and is stable in electrical properties.

Description

Thin-film transistor
Technical field
The present invention relates to a kind of thin-film transistor.
Background technology
Along with the progress of technology, thin-film transistor has been widely applied among display, to adapt to the demand such as slimming and miniaturization of display.Thin-film transistor generally comprises the parts such as grid, drain electrode, source electrode and channel layer, and its voltage by control grid changes the conductivity of channel layer, makes to form between source electrode and drain electrode the state of conducting or cut-off.
Thin-film transistor adopts transparent oxide semiconductor material (Transparent oxide semiconductor) conventionally, as indium oxide gallium zinc (InGaZnO), tin indium oxide zinc (InSnZnO), indium zinc oxide (IZO) etc. is made channel layer, its main charge carrier is by adulterating or lattice defect (lattice defects), as oxygen vacancies (oxygen vacancies), metal hole (metal vacancies), defect between lattice (interstitials) or the defect (oxygen associated defects) relevant with oxygen form, the oxygen vacancies that particularly oxygen forms forms.Therefore the carrier concentration that, makes metal oxide semiconductor material is easily direct associated because have with the external environment such as oxygen content, aqueous vapor, illumination and plasma (plasma damage).
Summary of the invention
In view of this, be necessary to provide a kind of and be difficult for being affected by the external environment, have the thin-film transistor of stable electric property.
A kind of thin-film transistor, comprise grid, channel layer, gate insulation layer between grid and channel layer and be positioned at the both sides that channel layer is relative and source electrode and the drain electrode contacting with channel layer respectively, between this channel layer and gate insulation layer, being folded with one first atom seizure layer.
In thin-film transistor provided by the invention, atom seizure layer can form atom bond with oxygen atom, make oxygen atom be difficult to infiltration from the oxygen atom in oxygen or aqueous vapor outside channel layer thereby catch, and this atom seizure layer can also stop oxygen atom in the channel layer of being made up of oxide semiconductor to exosmosis, thereby the metal-oxygen defect weak to bond power in oxide semiconductor forms protection, change to reduce the lattice defect relevant to oxygen in oxide semiconductor, make thin-film transistor be difficult for being affected by the external environment and there is stable electric property.
Brief description of the drawings
Fig. 1 is the structural representation of the thin-film transistor that provides of first embodiment of the invention.
Fig. 2 is the structural representation of the thin-film transistor that provides of second embodiment of the invention.
Fig. 3 is the structural representation of the thin-film transistor that provides of third embodiment of the invention.
Main element symbol description
Thin-film transistor 10、20、30
Substrate 11
Grid 12
Gate insulation layer 13
Atom seizure layer 14、18
Channel layer 15
Source electrode 16
Drain electrode 17
Following embodiment further illustrates the present invention in connection with above-mentioned accompanying drawing.
Embodiment
Refer to Fig. 1, the thin-film transistor 10 that first embodiment of the invention provides is bottom grating structure thin-film transistor.This thin-film transistor 10 comprises substrate 11, grid 12, gate insulation layer 13, atom seizure layer 14, channel layer 15, source electrode 16 and drain electrode 17.
This substrate 11 is for carrying grid 12.The making material of this substrate 11 can be glass, quartz, silicon wafer, Merlon, polymethyl methacrylate or metal forming etc.
This grid 12 is arranged on the upper surface of substrate 11, and is positioned at the upper face center of substrate 11.The making material of this grid 12 can be selected from copper, aluminium, nickel, magnesium, chromium, molybdenum, tungsten and alloy thereof.
This gate insulation layer 13 is arranged on the upper surface of substrate 11, and cover gate 12.The making material of this gate insulation layer 13 comprises the oxide S iOx of silicon, and the nitride SiNx of silicon or the nitrogen oxide SiONx of silicon, or the insulating material of other high-ks, as Ta 2o 5or HfO 2.
This atom seizure layer 14 is arranged on the upper surface of gate insulation layer 13, and is positioned at the upper face center of gate insulation layer 13.The main component of this atom seizure layer 14 can comprise at least one in carbon (C), silicon (Si), germanium (Ge), tin (Sn), plumbous (Pb), magnesium (Mg), calcium (Ca), strontium (Sr), barium (Ba), titanium (Ti), nickel (Ni), aluminium (Al), cobalt (Co), platinum (Pt), palladium (Pd) and manganese (Mn).Being doping to of this atom seizure layer 14 point is selected from the one in silicon (Si), germanium (Ge), carbon (C), nitrogen (N), aluminium (Al), boron (B), magnesium (Mg), calcium (Ca), strontium (Sr), barium (Ba), titanium (Ti), nickel (Ni) and cobalt (Co).
Atom seizure layer 14 can have two-dimensional structure or three-dimensional structure.In the time having two-dimensional structure, this atom seizure layer 14 can be Graphene (graphene) layer or silicon atom layer doped layer (Si atomic layer doping layer) etc.The atomic layer doping composition of this atom seizure layer 14 also can be selected from the one in germanium (Ge), carbon (C), nitrogen (N), aluminium (Al), boron (B), magnesium (Mg), calcium (Ca), strontium (Sr), barium (Ba), titanium (Ti), nickel (Ni) and cobalt (Co).In the time having three-dimensional structure, this atom seizure layer 14 can form by multiple graphene layers is stacking, also can be porous semiconductor layer or amorphism semiconductor layer.During for porous semiconductor layer, atom seizure layer 14 can be the porous semiconductor layer of silicon, germanium, SiGe or carbon material, for example: porous Si xge 1-xsemiconductor layer, wherein 0≤x≤1.During for amorphism semiconductor layer, atom seizure layer 14 can be the amorphism semiconductor layer of silicon, germanium, SiGe or carbon material, for example: amorphism Si xge 1-xsemiconductor layer, wherein 0≤x≤1.This atom seizure layer 14 also can be metal level, and its material can be selected from one or its alloy in aluminium (Al), tin (Sn), plumbous (Pb), magnesium (Mg), calcium (Ca), strontium (Sr), barium (Ba), titanium (Ti), nickel (Ni), cobalt (Co), platinum (Pt), palladium (Pd) and manganese (Mn).
This channel layer 15 is arranged on the upper surface of atom seizure layer 14, and covers this atom seizure layer 14.This channel layer 15 can be amorphism, polycrystallinity, crystalline structure or has micro-crystallization structure.This channel layer 15 can be made up of oxide semiconductor.Preferably, this channel layer 15 is metal oxide semiconductor layer, and this metal oxide semiconductor layer institute containing metal is selected from least one in indium, gallium, zinc, tin, aluminium, lead, molybdenum, manganese, magnesium, germanium and cadmium.In this enforcement, this channel layer 15 is indium oxide gallium zinc layers.
This source electrode 16 and drain electrode 17 are arranged on the upper surface of channel layer 15.This source electrode 16 and the drain electrode 17 relative both sides that are positioned on channel layer 15 upper surfaces, thereby this source electrode 16 and drain electrode 17 are extended to the direction away from the other side respectively, contact to cover the both sides of the edge of channel layer 15 and atom seizure layer 14 and to extend to the upper surface of gate insulation layer 13.When channel layer 15 covers this atom seizure layer 14 completely, or when atom seizure layer 14 is not electrically connected with source electrode 16 and drain electrode 17 simultaneously, this atom seizure layer 14 can be also metal level, and its material can be selected from one or its alloy in aluminium (Al), tin (Sn), plumbous (Pb), magnesium (Mg), calcium (Ca), strontium (Sr), barium (Ba), titanium (Ti), nickel (Ni), cobalt (Co), platinum (Pt), palladium (Pd) and manganese (Mn).
In above-mentioned thin-film transistor 10, atom seizure layer 14 can form atom bond with oxygen atom, make oxygen atom be difficult to infiltration from the oxygen atom in oxygen or aqueous vapor outside channel layer 15 thereby catch, and this atom seizure layer 14 can also stop oxygen atom in the channel layer 15 of being made up of oxide semiconductor to exosmosis, thereby the metal-oxygen defect weak to bond power in oxide semiconductor forms protection, change to reduce the lattice defect relevant to oxygen in oxide semiconductor, make thin-film transistor 10 be difficult for being affected by the external environment and there is stable electric property.
Referring to Fig. 2, the thin-film transistor 20 that second embodiment of the invention provides is top-grate structure thin film transistor.This thin-film transistor 20 comprises substrate 11, grid 12, gate insulation layer 13, atom seizure layer 14, channel layer 15, source electrode 16 and drain electrode 17 equally.
This source electrode 16 and drain electrode 17 are arranged on the upper surface of substrate 11, and are positioned at the both sides of substrate 11 upper surfaces.Middle position local covering that this channel layer 15 is arranged on substrate 11 upper surfaces are positioned at the source electrode 16 of substrate 11 upper surface both sides and drain 17.This atom seizure layer 14 is arranged on the upper surface of channel layer 15 and covers this channel layer 15.This gate insulation layer 13 is arranged on the upper surface of atom seizure layer 14 and covers the middle position of atom seizure layer 14 upper surface.This grid 12 is arranged on gate insulation layer 13 upper surfaces, and is positioned at the middle position of gate insulation layer 13 upper surfaces.
The material that above-mentioned thin-film transistor 20 is each layer is selected can be identical with thin-film transistor 10, and the two difference is only that thin-film transistor 20 is for top-grate structure thin film transistor, and thin-film transistor 10 is bottom grating structure thin-film transistor.
Referring to Fig. 3, the thin-film transistor 30 that third embodiment of the invention provides is bottom grating structure thin-film transistor.This thin-film transistor 30 comprises substrate 11, grid 12, gate insulation layer 13, atom seizure layer 14, channel layer 15, source electrode 16 and drain electrode 17 equally.The structure configuration of this thin-film transistor 30 is identical with thin-film transistor 10 cardinal principles, and difference is, this thin-film transistor 30 is than more than 10 atom seizure layers 18 of thin-film transistor.This atom seizure layer 18 is positioned at the side of channel layer 15 away from gate insulation layer 13.Concrete, this atom seizure layer 18 is between source electrode 16 and drain electrode 17, and not with source electrode 16 with drain and 17 contact.It should be noted that.This atom seizure layer 18 also can be connected with the one in source electrode 16 and drain electrode 17.
In addition, understandable, the configuration structure of thin-film transistor of the present invention is not limited to above-mentioned three contents that embodiment introduces, for example, this thin-film transistor not only can be top gate structure or bottom grating structure thin-film transistor, can be also coplanar structure or anti-co-planar thin film transistor, staggered or reciprocal cross shift thin-film transistor.
Be understandable that, for the person of ordinary skill of the art, can make change and the distortion that other various pictures are answered by technical conceive according to the present invention, and all these change the protection range that all should belong to the claims in the present invention with distortion.

Claims (27)

1. a thin-film transistor, comprise grid, channel layer, gate insulation layer between grid and channel layer and be positioned at the both sides that channel layer is relative and source electrode and the drain electrode contacting with channel layer respectively, it is characterized in that: between this channel layer and gate insulation layer, be folded with one first atom seizure layer.
2. thin-film transistor as claimed in claim 1, is characterized in that, described channel layer is amorphism, polycrystallinity or crystalline structure.
3. thin-film transistor as claimed in claim 2, is characterized in that, described channel layer has micro-crystallization structure.
4. thin-film transistor as claimed in claim 1, is characterized in that, described channel layer is oxide semiconductor layer.
5. thin-film transistor as claimed in claim 4, it is characterized in that, described channel layer is metal oxide semiconductor layer, and this metal oxide semiconductor layer institute containing metal is selected from least one in indium, gallium, zinc, tin, aluminium, lead, molybdenum, manganese, magnesium, germanium and cadmium.
6. thin-film transistor as claimed in claim 5, is characterized in that, described channel layer is indium oxide gallium zinc layer.
7. thin-film transistor as claimed in claim 1, is characterized in that, this thin-film transistor is top gate structure or bottom grating structure thin-film transistor.
8. thin-film transistor as claimed in claim 1, is characterized in that, this thin-film transistor is coplanar structure or anti-co-planar thin film transistor.
9. thin-film transistor as claimed in claim 1, is characterized in that, this thin-film transistor is staggered or reciprocal cross shift thin-film transistor.
10. thin-film transistor as claimed in claim 1, is characterized in that, the composition of described the first atom seizure layer comprises at least one in carbon, silicon, germanium, tin, lead, magnesium, calcium, strontium, barium, titanium, nickel, aluminium, cobalt, platinum, palladium and manganese.
11. thin-film transistors as claimed in claim 1, is characterized in that, described the first atom seizure layer has two-dimensional structure.
12. thin-film transistors as claimed in claim 11, is characterized in that, described the first atom seizure layer is graphene layer.
13. thin-film transistors as claimed in claim 11, is characterized in that, described the first atom seizure layer is silicon atom layer doped layer.
14. thin-film transistors as claimed in claim 1, is characterized in that, being doping to of described the first atom seizure layer point is selected from the one in silicon, germanium, carbon, nitrogen, aluminium, boron, magnesium, calcium, strontium, barium, titanium, nickel and cobalt.
15. thin-film transistors as claimed in claim 1, is characterized in that, described the first atom seizure layer has three-dimensional structure.
16. thin-film transistors as claimed in claim 15, is characterized in that, stacking the forming that described the first atom seizure layer is multiple graphene layers.
17. thin-film transistors as claimed in claim 15, is characterized in that, described the first atom seizure layer is porous semiconductor layer.
18. thin-film transistors as claimed in claim 17, is characterized in that, described the first atom seizure layer is the porous semiconductor layer of silicon, germanium, SiGe or carbon material.
19. thin-film transistors as claimed in claim 18, is characterized in that, described the first atom seizure layer is porous Si xge 1-xsemiconductor layer, wherein 0≤x≤1.
20. thin-film transistors as claimed in claim 15, is characterized in that, described the first atom seizure layer is amorphism semiconductor layer.
21. thin-film transistors as claimed in claim 20, is characterized in that, described the first atom seizure layer is the amorphism semiconductor layer of silicon, germanium, SiGe or carbon material.
22. thin-film transistors as claimed in claim 21, is characterized in that, described the first atom seizure layer is amorphism Si xge 1-xsemiconductor layer, wherein 0≤x≤1.
23. thin-film transistors as claimed in claim 1, is characterized in that, described the first atom seizure layer is metal level, and are not electrically connected with source electrode and drain electrode simultaneously.
24. thin-film transistors as claimed in claim 23, is characterized in that, the material of described the first atom seizure layer is selected from one or its alloy in aluminium, tin, lead, magnesium, calcium, strontium, barium, titanium, nickel, cobalt, platinum, palladium and manganese.
25. thin-film transistors as claimed in claim 1, is characterized in that, this thin-film transistor also comprises the second atom seizure layer, and this second atom seizure layer is positioned at the side of channel layer away from gate insulation layer.
26. thin-film transistors as described in claim 1 or 25, is characterized in that, this thin-film transistor also comprises the second atom seizure layer, and this second atom seizure layer is between source electrode and drain electrode.
27. thin-film transistors as claimed in claim 26, is characterized in that, this second atom seizure layer is connected with the one in source electrode and drain electrode.
CN201210573688.3A 2012-12-26 2012-12-26 Thin-film transistor Pending CN103904125A (en)

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Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN104779299A (en) * 2015-04-16 2015-07-15 京东方科技集团股份有限公司 Metal oxide thin film transistor, preparation method of transistor, display substrate and display device
CN109698240A (en) * 2017-10-24 2019-04-30 乐金显示有限公司 Thin film transistor (TFT) including two-dimensional semiconductor and the display equipment including it
WO2023240715A1 (en) * 2022-06-15 2023-12-21 武汉华星光电半导体显示技术有限公司 Display panel, display apparatus, and manufacturing method

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CN1109213A (en) * 1993-12-27 1995-09-27 夏普公司 Method for producing semiconductor film and semiconductor device having the same
US20010053607A1 (en) * 1996-02-28 2001-12-20 Kiyofumi Sakaguchi Fabrication process of semiconductor substrate
CN1574225A (en) * 2003-05-20 2005-02-02 Lg.飞利浦Lcd有限公司 Method of fabricating polycrystalline silicon and switching device using polycrystalline silicon
CN1842916A (en) * 2004-07-07 2006-10-04 松下电器产业株式会社 Solid-state image pickup device, manufacturing method thereof and camera using the solid-state image pickup device
US20120104381A1 (en) * 2010-10-29 2012-05-03 Chan-Long Shieh Metal oxide tft with improved stability
CN102709326A (en) * 2012-04-28 2012-10-03 北京京东方光电科技有限公司 Thin film transistor and manufacturing method thereof as well as array substrate and display device

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1109213A (en) * 1993-12-27 1995-09-27 夏普公司 Method for producing semiconductor film and semiconductor device having the same
US20010053607A1 (en) * 1996-02-28 2001-12-20 Kiyofumi Sakaguchi Fabrication process of semiconductor substrate
CN1574225A (en) * 2003-05-20 2005-02-02 Lg.飞利浦Lcd有限公司 Method of fabricating polycrystalline silicon and switching device using polycrystalline silicon
CN1842916A (en) * 2004-07-07 2006-10-04 松下电器产业株式会社 Solid-state image pickup device, manufacturing method thereof and camera using the solid-state image pickup device
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CN102709326A (en) * 2012-04-28 2012-10-03 北京京东方光电科技有限公司 Thin film transistor and manufacturing method thereof as well as array substrate and display device

Cited By (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN104779299A (en) * 2015-04-16 2015-07-15 京东方科技集团股份有限公司 Metal oxide thin film transistor, preparation method of transistor, display substrate and display device
WO2016165224A1 (en) * 2015-04-16 2016-10-20 京东方科技集团股份有限公司 Metal oxide thin film transistor and preparation method therefor, display substrate and display device
US10199395B2 (en) 2015-04-16 2019-02-05 Boe Technology Group Co., Ltd. Metal oxide thin film transistor and manufacturing method thereof, display substrate and display device
CN109698240A (en) * 2017-10-24 2019-04-30 乐金显示有限公司 Thin film transistor (TFT) including two-dimensional semiconductor and the display equipment including it
KR20190045659A (en) * 2017-10-24 2019-05-03 엘지디스플레이 주식회사 Thin film trnasistor comprising 2d semiconductor and display device comprising the same
KR20220057511A (en) * 2017-10-24 2022-05-09 엘지디스플레이 주식회사 Thin film trnasistor comprising 2d semiconductor and display device comprising the same
CN109698240B (en) * 2017-10-24 2022-06-14 乐金显示有限公司 Thin film transistor including two-dimensional semiconductor and display device including the same
KR102418493B1 (en) * 2017-10-24 2022-07-06 엘지디스플레이 주식회사 Thin film trnasistor comprising 2d semiconductor and display device comprising the same
KR102547131B1 (en) * 2017-10-24 2023-06-22 엘지디스플레이 주식회사 Thin film trnasistor comprising 2d semiconductor and display device comprising the same
WO2023240715A1 (en) * 2022-06-15 2023-12-21 武汉华星光电半导体显示技术有限公司 Display panel, display apparatus, and manufacturing method

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Application publication date: 20140702