CN103901772A - Double-DSP redundancy inertial-platform controller - Google Patents
Double-DSP redundancy inertial-platform controller Download PDFInfo
- Publication number
- CN103901772A CN103901772A CN201410166141.0A CN201410166141A CN103901772A CN 103901772 A CN103901772 A CN 103901772A CN 201410166141 A CN201410166141 A CN 201410166141A CN 103901772 A CN103901772 A CN 103901772A
- Authority
- CN
- China
- Prior art keywords
- dsp processor
- module
- dsp
- signal
- output terminal
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Images
Landscapes
- Hardware Redundancy (AREA)
Abstract
The invention provides a double-DSP redundancy inertial-platform controller and belongs to the field of platform stable loop control, follow-up ring follow-up control and follow-up ring locked control. The double-DSP redundancy inertial-platform controller aims to solve the problem that when a processor of an existing inertial navigation system breaks down, operation cannot be conducted due to a lack of a standby controller. The double-DSP redundancy inertial platform controller comprises an AD conversion circuit, an IO circuit, a bus module, a power output module, a switching module, a judging module, a first DSP and a second DSP. The AD conversion circuit is in communication with the two DSPs at the same time. An IO circuit is in communication with the two DSPs at the same time through an optocoupler. The second DSP monitors the work state of the first DSP through a McBSP. The judging module is used for judging the state of the judging module and the work state of the first DSP. The switching module conducts switching on the first DSP and the second DSP according to signals of the judgment module. The power output module outputs PWM signals according to switching signals. The bus module is used for receiving data of the power outputting module, the first DSP and the second DSP. The double-DSP redundancy inertial-platform controller is used for an inertial platform of the inertial navigation system.
Description
Technical field
The invention belongs to platform stabilizing circuit control, the servo-actuated control of phantom ring and phantom ring locking control field.
Background technology
Being widely used in the inertial platform of inertial navigation system, also claiming gyrostabilized platform, is the vitals in inertial navigation.By set up a mode that is not subject to the reference frame that aircraft movements affects on aircraft, measure the attitude information of aircraft.The stability of inertial platform, will produce conclusive impact to whole navigational system.
Along with the development of computer technology, high integration, microprocessor appearance cheaply commercialization fast at a high speed,, microprocessor in the powerful advantages aspect data operation and control ability, has been widely used in the each side such as space flight, navigation, military affairs, industrial automation, traffic, the energy with it.At present, DSP is widely used in the inertial platform in space industry,
In the servo servo-actuated circuit of controlling in platform stabilizing circuit control, the servo-actuated control of phantom ring and phantom ring locking, play great role.
In the servocontrol of inertial platform, due to defect of various unpredictable external interference or servo control software system etc., all may cause the problems such as processor deadlock, program fleet, once there is such accident in inertial navigation system, the massive losses that just may cause personnel and financial resources, produces serious consequence.And in traditional controller, once processor breaks down, be just difficult to guarantee the safety and steady operation of navigational system.So in the very high inertial platform of stability requirement, it is very important introducing fault-tolerant technique.
Summary of the invention
The processor generation fault the object of the invention is in order to solve current inertial navigation system causes owing to lacking spare controller the problem that cannot move, the invention provides a kind of two DSP redundancy inertial platform controllers.
Of the present invention pair of DSP redundancy inertial platform controller, described controller comprises A/D convertor circuit, IO circuit, bus module, power output module, handover module, judging module, the first dsp processor and the second dsp processor;
The gyro digital signal output end of A/D convertor circuit is connected with the gyro digital signal input end of the first dsp processor and the second dsp processor simultaneously, the data output end of IO circuit is connected with the data input pin of the first dsp processor and the second dsp processor by optocoupler simultaneously, the working state signal output terminal of the first dsp processor is connected with the working state signal input end of the second dsp processor by McBSP, the periodic pulse signal output terminal of the first dsp processor is connected with the periodic pulse signal input end of judging module, the first dsp processor fault detection signal output terminal of the second dsp processor is connected with the first dsp processor fault detection signal input end of judging module,
The decision signal output terminal of judging module is connected with the decision signal input end of handover module, the pwm signal input/output terminal of the first dsp processor is connected with the first pwm signal input/output terminal of handover module, the pwm signal input/output terminal of the second dsp processor is connected with the second pwm signal input/output terminal of handover module, the pwm signal output terminal of handover module is connected with the input end of the pwm signal of power output module, the pwm signal output terminal of power output module is connected with the pwm signal input end of bus module
The data input/output terminal of the first dsp processor is connected with the first data input/output terminal and the second data input/output terminal of bus module respectively with the data input/output terminal of the second dsp processor.
Described judging module comprises FPGA module, detection module and combinational logic circuit;
FPGA module, for by the pulse signal of GPIO pin that detects the first dsp processor, determines whether the first dsp processor breaks down, and sends the first dsp processor fault to combinational logic circuit and judge signal;
Whether detection module, break down for detection of FPGA module, and judge signal to combinational logic circuit transmission FPGA module failure;
Combinational logic circuit, for adjudicating according to receiving the first dsp processor fault detection signal that the first dsp processor fault judge that signal, FPGA module failure judges that signal and the second dsp processor are exported, export the decision signal whether the first dsp processor 7 and the second dsp processor switch.
Beneficial effect of the present invention is, use two dsp processors to carry out redundancy fault-tolerant design, take full advantage of on the one hand the powerful advantages of dsp processor aspect deal with data, effectively inertial platform is controlled at a high speed, guaranteed permissible accuracy and stability in inertial navigation; Judge by input whether the first dsp processor 7 normally works on the other hand, if combinational logic circuit judges main frame and breaks down, send a command to handover module, and then be switched to the second dsp processor 8 by the first dsp processor 7 when realizing processor and breaking down, guarantee the safe operation of inertial navigation system.In addition judging module not only detects the first dsp processor 7 by FPGA module, also by the second dsp processor 8, the first dsp processor 7 is detected, increase the detection module that detects FPGA module simultaneously, guaranteed the reliability to the first dsp processor 7 faults whether judged result.Ensure the normal stable operation of inertial navigation system.
Accompanying drawing explanation
Fig. 1 is the principle schematic of the two DSP redundancy inertial platform controllers described in embodiment one.
Fig. 2 is the principle schematic of the A/D convertor circuit described in embodiment one.
Fig. 3 is the principle schematic of the IO circuit described in embodiment one.
Fig. 4 is the principle schematic of the judging module described in embodiment two.
Fig. 5 is the principle schematic of the detection module described in embodiment three.
Fig. 6 is the principle schematic of the combinational logic circuit described in embodiment four.
Fig. 7 is the principle schematic of the handover module 5 described in embodiment seven.
Embodiment
Embodiment one: present embodiment is described in conjunction with Fig. 1, Fig. 2 and Fig. 3, two DSP redundancy inertial platform controllers described in present embodiment, described controller comprises A/D convertor circuit 1, IO circuit 2, bus module 3, power output module 4, handover module 5, judging module 6, the first dsp processor 7 and the second dsp processor 8;
The gyro digital signal output end of A/D convertor circuit 1 is connected with the gyro digital signal input end of the first dsp processor 7 and the second dsp processor 8 simultaneously, the data output end of IO circuit 2 is connected with the data input pin of the first dsp processor 7 and the second dsp processor 8 by optocoupler simultaneously, the working state signal output terminal of the first dsp processor 7 is by McBSP(Multichannel Buffered Serial Port, multichannel buffer serial port) be connected with the working state signal input end of the second dsp processor 8, the periodic pulse signal output terminal of the first dsp processor 7 is connected with the periodic pulse signal input end of judging module 6, the first dsp processor 7 fault detection signal output terminals of the second dsp processor 8 are connected with the first dsp processor 7 fault detection signal input ends of judging module 6,
The decision signal output terminal of judging module 6 is connected with the decision signal input end of handover module 5, the pwm signal input/output terminal of the first dsp processor 7 is connected with the first pwm signal input/output terminal of handover module 5, the pwm signal input/output terminal of the second dsp processor 8 is connected with the second pwm signal input/output terminal of handover module 5, the pwm signal output terminal of handover module 5 is connected with the input end of the pwm signal of power output module 4, the pwm signal output terminal of power output module 4 is connected with the pwm signal input end of bus module 3
The data input/output terminal of the data input/output terminal of the first dsp processor 7 and the second dsp processor 8 is connected with the first data input/output terminal and the second data input/output terminal of bus module 3 respectively.
In present embodiment, using original DSP as the first dsp processor 7, increase a slice DSP and realize principal and subordinate's Redundancy Design as the second dsp processor 8, the first dsp processors 7 and the second dsp processor 8.
The A/D convertor circuit 1 gyrostatic analog input amount in Jiang San road respectively by two independently AD chip carry out parallel access the first dsp processor 7 and the second dsp processor 8 after analog to digital conversion, the signal of each passage adopts isolation design, avoids occurring coupled relation; 5V voltage is received in AD tetra-tunnels, compare through conversion, judge that whether AD is normal.As shown in Figure 2.
In the IO of present embodiment circuit 2, the parallel GPIO(General Purpose Input Output that is linked into the first dsp processor 7 and the second dsp processor 8 of 1ms bus timing look-at-me He Si road IO control signal, general input/output port) in, guarantee the 3.3V IO level match of the GPIO of outside 5V level and dsp processor by light-coupled isolation, as shown in Figure 3.
In present embodiment, handover module is realized by one-level commutation circuit, the selection signal deciding being produced by judging module is exported the pwm signal of which dsp processor, if judging module is output as 0, export the pwm signal of the first dsp processor 7, if Combinational logic output is 1, export the pwm signal of the second dsp processor 8.Embodiment two: in conjunction with Fig. 4, present embodiment is described, present embodiment is the further restriction to the two DSP redundancy inertial platform controllers described in embodiment one, and described judging module 6 comprises FPGA module, detection module and combinational logic circuit;
FPGA module, for by the pulse signal of GPIO pin that detects the first dsp processor 7, determines whether the first dsp processor 7 breaks down, and sends the first dsp processor 7 faults to combinational logic circuit and judge signal;
Whether detection module, break down for detection of FPGA module, and judge signal to combinational logic circuit transmission FPGA module failure;
Combinational logic circuit, for adjudicating according to receiving the first dsp processor 7 fault detection signals that the first dsp processor 7 faults judges that signal, FPGA module failure judge that signal and the second dsp processor 8 are exported, export the decision signal whether the first dsp processor 7 and the second dsp processor 8 switch.
Detect the GPIO pin of the first dsp processor 7 by FPGA module, the second 8 of dsp processors are by McBSP(Multichannel Buffered Serial Port, multichannel buffer serial port) monitoring the first dsp processor 7 working condition, once FPGA module and the second dsp processor 8 detect that the first dsp processor 7 breaks down simultaneously, be switched to the second dsp processor 8 and carry out work, and operation is gone down always, no longer switches; For the damage meeting that prevents FPGA module itself impact on bringing on a disaster property of whole system, by detection module, FPGA module is detected again, if FPGA is working properly, the pulse in its IO mouth 1ms cycle of output, normally whether can detecting by detection module, and then whether FPGA module failure is judged of this pulse; Testing result to FPGA module of the testing result of FPGA module to the first dsp processor, testing circuit and the second dsp processor 8 to the testing result of the first dsp processor 7 by combinational logic circuit draw whether carry out that the firstth dsp processor 7 and the second dsp processor 8 switch conclusion.
Embodiment three: present embodiment is described in conjunction with Fig. 5, present embodiment is the further restriction to the two DSP redundancy inertial platform controllers described in embodiment two, described detection module is monostalbe trigger circuit, and adopts monostalbe trigger SN54LS123J to realize.
As shown in Figure 7, detect FPGA module and whether break down by can heavily triggering monostalbe trigger 74LS123.In the time being input as clock signal, the inverse output terminal mouth of trigger can produce negative pulse, and can regulate additional capacitance-resistance value to set the width of negative pulse.In the time that negative pulse width is greater than the one-period of input clock and is less than two cycles, its inverse output terminal mouth is no longer negative pulse sequence, but a low level.In the time no longer there is suddenly low and high level and change in input clock signal, its inverse output terminal mouth in the end a negative pulse to finish rear redirect be high level.
Embodiment four: in conjunction with Fig. 6, present embodiment is described, present embodiment is the further restriction to the two DSP redundancy inertial platform controllers described in embodiment two, and combinational logic circuit comprises a Sheffer stroke gate and a rejection gate; The first dsp processor 7 faults judge that the first dsp processor 7 fault detection signals that signal and the second dsp processor 8 are exported input to respectively two input ends of Sheffer stroke gate, the output signal of Sheffer stroke gate and FPGA module failure judge that signal inputs to respectively two input ends of rejection gate, and rejection gate is exported the decision signal whether the first dsp processor 7 and the second dsp processor 8 switch.
Corresponding to the function that realizes combinational logic circuit, adopt a Sheffer stroke gate CD4011BF and a rejection gate CD4001BF to realize.
Embodiment five: present embodiment is the further restriction to the two DSP redundancy inertial platform controllers described in embodiment four, a is the true value that the first dsp processor 7 faults of FPGA module output judge signal, b is the true value that the FPGA module failure of detection module output judges signal, c is the true value of the first dsp processor 7 fault detection signals of exporting of the second dsp processor 8, f is the true value of the decision signal that whether switches of the first dsp processor 7 and the second dsp processor 8, mistake! Do not find Reference source., when a or b or c are low level, represent that current judged result is trouble-free, otherwise for there being fault, when f is high level, represent to switch the first dsp processor 7 and the second dsp processor 8, the second dsp processor 8 is replaced the first dsp processor 7 and is worked.
In present embodiment, in the time being low level, represent that current judged result is trouble-free, otherwise for there being fault.Tri-of a, b and c judge signal, entered after combinational logic circuit, obtain total judgement output, this judgement output can be designated as f, f drives change-over switch, completes the switching of PWM output signal, in the time that f is low level, export the pwm signal of the first dsp processor 7, otherwise be output as the pwm signal of the second dsp processor 8.The combined expression of f is
the truth table of described combinational logic circuit is:
The truth table of table 1 combinational logic circuit
Embodiment six: present embodiment is the further restriction to the two DSP redundancy inertial platform controllers described in embodiment one, and described bus module 3 is RS422/RS485 bus module.
In RS422/RS485 bus module, RS485 and RS422 bus are after level transferring chip, then by light-coupled isolation, then input to two SCI modules of F2812, RS485 adopts one-way transmission mode, only receives and does not send out, and between Max485 and optocoupler, increases current drives; RS422 adopts bus carry form, the serial ports of two DSP is exported after light-coupled isolation and level conversion, and directly carry is in RS422 bus, and two-way RS422 can receive data simultaneously, but once can only have one in transmission state, the Enable Pin of transmission is controlled by the GPIO of DSP.
Embodiment seven: in conjunction with Fig. 7, present embodiment is described, present embodiment is the further restriction to the two DSP redundancy inertial platform controllers described in embodiment one, described handover module 5 adopts chip SN54517 to realize.
Embodiment eight: present embodiment is described in conjunction with Fig. 7, present embodiment is the further restriction to the two DSP redundancy inertial platform controllers described in embodiment seven, and described power output module 4 comprises power device MSK4201 and filtering buffer circuit; The pwm signal that handover module 5 is exported inputs to power device MSK4201 after optocoupler, and the pwm signal of power device MSK4201 output inputs to filtering buffer circuit.
The pwm signal of two DSP, first selects by chip SN54157, then isolates through 6N137 optocoupler, because the output current of SN54157 can reach 16mA, can directly drive optocoupler.Pwm signal, through optocoupler rear drive power device MSK4201, at power output stage,, with reference to original motor-drive circuit, has increased filtering and buffer circuit.
It is of the present invention that to realize the implementation procedure that the first dsp processor 7 and the second DSP of place reason device switches as follows:
The first step, 5V voltage is received in A/D convertor circuit 1 tetra-tunnels, A/D convertor circuit 1 this four circuit-switched data is delivered to the first dsp processor 7, utilize the data volume digital quantity comparison corresponding with known 5V after the conversion of Si road, if in certain threshold value, the first dsp processor 7 judges that AD is normal, if comparative result exceeds certain threshold value, the first dsp processor 7 judges that A/D convertor circuit 1 occurs extremely.
Second step, detect the GPIO pin output of the first dsp processor 7 by FPGA module, under normal circumstances, the pulse that the GPIO pin of the first dsp processor 7 can be 1ms in the output cycle, if the first dsp processor 7 detects that A/D convertor circuit 1 breaks down or himself breaks down in the first step, the first dsp processor 7 no longer sends this pulse to FPGA module, and judges that the fault of the first dsp processor 7 judges that signal becomes high level.
Simultaneously, the second dsp processor 8 is monitored the first dsp processor 7 by McBSP, the first dsp processor 7 is every sends a signal to the second dsp processor 8, and the timer 0 just set again in the second dsp processor 8, utilizes timer 0 can detect whether the first dsp processor 7 breaks down.If the second dsp processor 8 detects that the first dsp processor 7 breaks down or himself breaks down, judge that the FPGA module failure of detection module output judges that signal becomes high level.
The 3rd step, detect the 1ms recurrent pulse of the IO mouth output of FPGA module by can heavily triggering monostalbe trigger, when FPGA module is normal, monostalbe trigger output low level, FPGA module occurs when abnormal, its IO mouth is no longer exported recurrent pulse, monostalbe trigger delivery outlet in the end a negative pulse to finish rear redirect be high level, judge that the first dsp processor 7 fault detection signals that the second dsp processor 8 is exported are also the outputs level signals of monostalbe trigger.
The 4th step, a, b and tri-of c that second step and the 3rd step are obtained judge that signal is transferred to combinational logic circuit, through combinational logic, computing obtains total judgement output f.
The 5th step, decision signal f drives change-over switch, completes the switching of pwm output signal, and f exports the pwm signal of the first dsp processor 7 at 0 o'clock, on the contrary the pwm signal of defeated the second dsp processor 8.
Claims (8)
1. pair DSP redundancy inertial platform controller, it is characterized in that being, described controller comprises A/D convertor circuit (1), IO circuit (2), bus module (3), power output module (4), handover module (5), judging module (6), the first dsp processor (7) and the second dsp processor (8);
The gyro digital signal output end of A/D convertor circuit (1) is connected with the gyro digital signal input end of the first dsp processor (7) and the second dsp processor (8) simultaneously, the data output end of IO circuit (2) is connected with the data input pin of the first dsp processor (7) and the second dsp processor (8) by optocoupler simultaneously, the working state signal output terminal of the first dsp processor (7) is connected with the working state signal input end of the second dsp processor (8) by McBSP, the periodic pulse signal output terminal of the first dsp processor (7) is connected with the periodic pulse signal input end of judging module (6), the first dsp processor fault detection signal output terminal of the second dsp processor (8) is connected with the first dsp processor fault detection signal input end of judging module (6),
The decision signal output terminal of judging module (6) is connected with the decision signal input end of handover module (5), the pwm signal input/output terminal of the first dsp processor (7) is connected with the first pwm signal input/output terminal of handover module (5), the pwm signal input/output terminal of the second dsp processor (8) is connected with the second pwm signal input/output terminal of handover module (5), the pwm signal output terminal of handover module (5) is connected with the input end of the pwm signal of power output module (4), the pwm signal output terminal of power output module (4) is connected with the pwm signal input end of bus module (3),
The data input/output terminal of the data input/output terminal of the first dsp processor (7) and the second dsp processor (8) is connected with the first data input/output terminal and the second data input/output terminal of bus module (3) respectively.
2. according to claim 1 pair of DSP redundancy inertial platform controller, is characterized in that, described judging module (6) comprises FPGA module, detection module and combinational logic circuit;
FPGA module, for by the pulse signal of GPIO pin that detects the first dsp processor, determines whether the first dsp processor breaks down, and sends the first dsp processor fault to combinational logic circuit and judge signal;
Whether detection module, break down for detection of FPGA module, and judge signal to combinational logic circuit transmission FPGA module failure;
Combinational logic circuit, for adjudicating according to receiving the first dsp processor fault detection signal that the first dsp processor fault judge that signal, FPGA module failure judges that signal and the second dsp processor (8) are exported, export the decision signal whether the first dsp processor (7) and the second dsp processor (8) switch.
3. according to claim 2 pair of DSP redundancy inertial platform controller, is characterized in that, described detection module is monostalbe trigger circuit, and adopts monostalbe trigger SN54LS123J to realize.
4. according to claim 2 pair of DSP redundancy inertial platform controller, is characterized in that, combinational logic circuit comprises a Sheffer stroke gate and a rejection gate; The first dsp processor fault judges that the first dsp processor fault detection signal of signal and the second dsp processor (8) output inputs to respectively two input ends of Sheffer stroke gate, the output signal of Sheffer stroke gate and FPGA module failure judge that signal inputs to respectively two input ends of rejection gate, and rejection gate is exported the decision signal whether the first dsp processor (7) and the second dsp processor (8) switch.
5. according to claim 4 pair of DSP redundancy inertial platform controller, is characterized in that, the truth table of described combinational logic circuit is:
The truth table of combinational logic circuit
A is the true value that the first dsp processor fault of FPGA module output judges signal, b is the true value that the FPGA module failure of detection module output judges signal, c is the true value of the first dsp processor fault detection signal of the second dsp processor (8) output, f is the true value of the decision signal that whether switches of the first dsp processor (7) and the second dsp processor (8)
when a, b or c are low level, represent that current judged result is trouble-free, otherwise for there being fault, when f is high level, represent to switch the first dsp processor (7) and the second dsp processor (8), the second dsp processor (8) is replaced the first dsp processor (7) work.
6. according to claim 1 pair of DSP redundancy inertial platform controller, is characterized in that, described bus module (3) is RS422/RS485 bus module.
7. according to claim 1 pair of DSP redundancy inertial platform controller, is characterized in that, described handover module (5) adopts chip SN54517 to realize.
8. according to claim 7 pair of DSP redundancy inertial platform controller, is characterized in that, described power output module (4) comprises power device MSK4201 and filtering buffer circuit; The pwm signal of handover module (5) output inputs to power device MSK4201 after optocoupler, and the pwm signal of power device MSK4201 output inputs to filtering buffer circuit.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201410166141.0A CN103901772B (en) | 2014-04-23 | 2014-04-23 | Two CSTR redundancy inertial platform controller |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201410166141.0A CN103901772B (en) | 2014-04-23 | 2014-04-23 | Two CSTR redundancy inertial platform controller |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN103901772A true CN103901772A (en) | 2014-07-02 |
| CN103901772B CN103901772B (en) | 2016-04-13 |
Family
ID=50993165
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201410166141.0A Active CN103901772B (en) | 2014-04-23 | 2014-04-23 | Two CSTR redundancy inertial platform controller |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN103901772B (en) |
Cited By (14)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104571066A (en) * | 2015-01-28 | 2015-04-29 | 上海明华电力技术工程有限公司 | DCS (distributed control system) platform-based adjusting-type executor backup operation method and system |
| CN105157702A (en) * | 2015-06-30 | 2015-12-16 | 北京航天控制仪器研究所 | All-attitude three-frame four-axis inertial platform servo ring control method |
| CN106647351A (en) * | 2016-10-19 | 2017-05-10 | 浙江中控技术股份有限公司 | Redundancy switching circuit |
| CN107219856A (en) * | 2016-03-21 | 2017-09-29 | 波音公司 | Unmanned vehicle flight control system |
| CN107895937A (en) * | 2017-12-12 | 2018-04-10 | 北京动力源科技股份有限公司 | A kind of electric machine controller redundancy protecting circuit and electronic equipment |
| CN108241359A (en) * | 2017-12-15 | 2018-07-03 | 中国航空工业集团公司西安飞行自动控制研究所 | A kind of failure safe output method based on SAFEBus buses |
| CN108919636A (en) * | 2018-06-11 | 2018-11-30 | 北京三快在线科技有限公司 | Aircraft and its control method and computer readable storage medium |
| CN109358531A (en) * | 2018-09-04 | 2019-02-19 | 南宁学院 | A kind of field control system based on Time-sharing control handover control |
| CN109508313A (en) * | 2018-09-28 | 2019-03-22 | 天津市英贝特航天科技有限公司 | A kind of dual redundant 1553B bus protocol module based on CPCI-E |
| CN111343386A (en) * | 2018-12-19 | 2020-06-26 | 北京小米移动软件有限公司 | Image signal processing method and device, electronic device and storage medium |
| CN111708291A (en) * | 2020-05-28 | 2020-09-25 | 漳州科华技术有限责任公司 | DSP information mutual transmission method for domestic chip |
| CN112510733A (en) * | 2021-02-04 | 2021-03-16 | 沈阳微控新能源技术有限公司 | Flywheel energy storage system, control method thereof and computer readable storage medium |
| CN115022159A (en) * | 2022-06-27 | 2022-09-06 | 汉中一零一航空电子设备有限公司 | Control equipment main controller redundancy backup system and method |
| CN115561992A (en) * | 2022-09-29 | 2023-01-03 | 西门子（中国）有限公司 | Power module control system, method, electronic device, and storage medium |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4785453A (en) * | 1985-05-10 | 1988-11-15 | Tandem Computers Incorporated | High level self-checking intelligent I/O controller |
| CN102331786A (en) * | 2011-07-18 | 2012-01-25 | 北京航空航天大学 | Dual-computer cold-standby system of attitude and orbit control computer |
| CN202261338U (en) * | 2011-10-18 | 2012-05-30 | 广州五舟信息科技有限公司 | Dual-computer fault-tolerant system for electronic commerce platform |
| CN102650962A (en) * | 2012-04-10 | 2012-08-29 | 北京航空航天大学 | Soft core fault-tolerant spaceborne computer based on FPGA (Field Programmable Gata Array) |
-
2014
- 2014-04-23 CN CN201410166141.0A patent/CN103901772B/en active Active
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4785453A (en) * | 1985-05-10 | 1988-11-15 | Tandem Computers Incorporated | High level self-checking intelligent I/O controller |
| CN102331786A (en) * | 2011-07-18 | 2012-01-25 | 北京航空航天大学 | Dual-computer cold-standby system of attitude and orbit control computer |
| CN202261338U (en) * | 2011-10-18 | 2012-05-30 | 广州五舟信息科技有限公司 | Dual-computer fault-tolerant system for electronic commerce platform |
| CN102650962A (en) * | 2012-04-10 | 2012-08-29 | 北京航空航天大学 | Soft core fault-tolerant spaceborne computer based on FPGA (Field Programmable Gata Array) |
Non-Patent Citations (3)
| Title |
|---|
| 张汨: "双机系统的冗余及仲裁策略研究", 《中国优秀硕士学位论文全文数据库 信息科技辑（月刊）》 * |
| 李贻斌，等: "双机容错系统的仲裁器设计", 《微计算机信息》 * |
| 魏志明，等: "双机容错系统中基于FPGA容错控制器的设计", 《科学技术与工程》 * |
Cited By (19)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104571066A (en) * | 2015-01-28 | 2015-04-29 | 上海明华电力技术工程有限公司 | DCS (distributed control system) platform-based adjusting-type executor backup operation method and system |
| CN105157702A (en) * | 2015-06-30 | 2015-12-16 | 北京航天控制仪器研究所 | All-attitude three-frame four-axis inertial platform servo ring control method |
| CN105157702B (en) * | 2015-06-30 | 2017-11-07 | 北京航天控制仪器研究所 | A kind of axle inertial platform phantom ring control method of three framework of full posture four |
| CN107219856A (en) * | 2016-03-21 | 2017-09-29 | 波音公司 | Unmanned vehicle flight control system |
| CN106647351A (en) * | 2016-10-19 | 2017-05-10 | 浙江中控技术股份有限公司 | Redundancy switching circuit |
| CN107895937A (en) * | 2017-12-12 | 2018-04-10 | 北京动力源科技股份有限公司 | A kind of electric machine controller redundancy protecting circuit and electronic equipment |
| CN107895937B (en) * | 2017-12-12 | 2023-09-15 | 北京动力源新能源科技有限责任公司 | Redundant protection circuit of motor controller and electronic equipment |
| CN108241359B (en) * | 2017-12-15 | 2021-06-01 | 中国航空工业集团公司西安飞行自动控制研究所 | Safety fault output method based on safebus bus |
| CN108241359A (en) * | 2017-12-15 | 2018-07-03 | 中国航空工业集团公司西安飞行自动控制研究所 | A kind of failure safe output method based on SAFEBus buses |
| CN108919636A (en) * | 2018-06-11 | 2018-11-30 | 北京三快在线科技有限公司 | Aircraft and its control method and computer readable storage medium |
| CN109358531A (en) * | 2018-09-04 | 2019-02-19 | 南宁学院 | A kind of field control system based on Time-sharing control handover control |
| CN109358531B (en) * | 2018-09-04 | 2021-06-29 | 南宁学院 | On-site control system based on time-sharing control handover control right |
| CN109508313A (en) * | 2018-09-28 | 2019-03-22 | 天津市英贝特航天科技有限公司 | A kind of dual redundant 1553B bus protocol module based on CPCI-E |
| CN111343386A (en) * | 2018-12-19 | 2020-06-26 | 北京小米移动软件有限公司 | Image signal processing method and device, electronic device and storage medium |
| CN111343386B (en) * | 2018-12-19 | 2022-03-25 | 北京小米移动软件有限公司 | Image signal processing method and device, electronic device and storage medium |
| CN111708291A (en) * | 2020-05-28 | 2020-09-25 | 漳州科华技术有限责任公司 | DSP information mutual transmission method for domestic chip |
| CN112510733A (en) * | 2021-02-04 | 2021-03-16 | 沈阳微控新能源技术有限公司 | Flywheel energy storage system, control method thereof and computer readable storage medium |
| CN115022159A (en) * | 2022-06-27 | 2022-09-06 | 汉中一零一航空电子设备有限公司 | Control equipment main controller redundancy backup system and method |
| CN115561992A (en) * | 2022-09-29 | 2023-01-03 | 西门子（中国）有限公司 | Power module control system, method, electronic device, and storage medium |
Also Published As
| Publication number | Publication date |
|---|---|
| CN103901772B (en) | 2016-04-13 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN103901772A (en) | Double-DSP redundancy inertial-platform controller | |
| CN104238435B (en) | Triple-redundancy control computer and fault-tolerant control system | |
| US11718331B2 (en) | Non-national standard turnout drive system based on double 2-vote-2 architecture | |
| CN111352338B (en) | Dual-redundancy flight control computer and redundancy management method | |
| CN102055633B (en) | Satellite-borne double-CAN (Controller Area Network) bus node failure self-restoration system | |
| CN104714406B (en) | Input/output module redundancy switching method | |
| CN106094789B (en) | A kind of the dual chip redundancy and fault-tolerant control system of automobile steering-by-wire | |
| CN101710376B (en) | Hardware platform of safe computer 2-out-of-3 voting method | |
| CN110794805B (en) | Robot safety circuit and control method thereof | |
| CN203643761U (en) | Triple redundancy concurrent control module | |
| CN107895937B (en) | Redundant protection circuit of motor controller and electronic equipment | |
| CN209911778U (en) | Engineering machinery vehicle-mounted controller based on functional safety | |
| CN103064368A (en) | Redundant controller of Profibus-decentralized periphery (DP) | |
| CN110442073A (en) | A kind of redundance Aircraft Management Computer MIO board channel fault logic judgment method | |
| US10317885B2 (en) | Safety circuit, back-up safety circuit and industrial robot safety control system | |
| CN102915778B (en) | Method for carrying out power loss analysis on digital instrument control system of nuclear power plant by utilizing functional group analysis method | |
| CN203338127U (en) | Dual-redundancy control system for AGV | |
| CN103793300B (en) | Fast active-standby switching device in hot-standby system and active-standby switching method | |
| CN210270871U (en) | Redundant fault-tolerant computer serial port gating device | |
| CN102968110B (en) | Multi-power-supply automatic transfer switch (ATS) signal processing system based on multiple processors and control method for multi-power-supply ATS signal processing system | |
| CN202583865U (en) | Dual-redundancy control circuit | |
| CN105573869B (en) | System controller fault tolerant control method based on I2C bus | |
| CN207557715U (en) | A kind of controller suitable for Complex spatial framework | |
| CN204138119U (en) | The safety protective circuit of a kind of escalator or moving sidewalk | |
| CN203097556U (en) | Door controller beside platform |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| TR01 | Transfer of patent right |
Effective date of registration: 20190612 Address after: 150000 Heilongjiang Harbin Dalian economic and Trade Zone, the North Road and Xingkai Road intersection Patentee after: Harbin University of Technology Robot Group Co., Ltd. Address before: 150001 No. 92 West straight street, Nangang District, Heilongjiang, Harbin Patentee before: Harbin Institute of Technology |
|
| TR01 | Transfer of patent right |