CN103887966B - Charge pump realizes circuit - Google Patents
Charge pump realizes circuit Download PDFInfo
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- CN103887966B CN103887966B CN201410112015.7A CN201410112015A CN103887966B CN 103887966 B CN103887966 B CN 103887966B CN 201410112015 A CN201410112015 A CN 201410112015A CN 103887966 B CN103887966 B CN 103887966B
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Classifications
-
- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M3/00—Conversion of dc power input into dc power output
- H02M3/02—Conversion of dc power input into dc power output without intermediate conversion into ac
- H02M3/04—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters
- H02M3/06—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using resistors or capacitors, e.g. potential divider
- H02M3/07—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using resistors or capacitors, e.g. potential divider using capacitors charged and discharged alternately by semiconductor devices with control electrode, e.g. charge pumps
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/08—Details of the phase-locked loop
- H03L7/085—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal
- H03L7/087—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal using at least two phase detectors or a frequency and phase detector in the loop
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/16—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop
- H03L7/22—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using more than one loop
- H03L7/23—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using more than one loop with pulse counters or frequency dividers
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- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
Abstract
What the embodiment of the present invention provided a kind of charge pump realizes circuit.The circuit includes：First current mirror, the second current mirror, first switch circuit, second switch circuit, connection circuit, the first unity gain amplifier, the second unity gain amplifier and pulse-generating circuit；Wherein, the first current mirror, the first voltage mirror image for VCO to be exported is the first electric current；Second current mirror, the second voltage mirror image for VCO to be exported is the second electric current；Pulse-generating circuit, for generating pulse signal according to reference clock signal, pulse signal is used to control the on off state of the first switch circuit and second switch circuit；First unity gain amplifier and the second unity gain amplifier, for when reference clock signal is low level, the drain voltage of the voltage of the output end of the first current mirror, the voltage of the output end of the second current mirror, the voltage of LPF inputs and first switch pipe is kept equal, so as to avoid producing Charge injection effect, the performance of PLL is improve.
Description
Technical field
The present embodiments relate to the communication technology, more particularly to a kind of charge pump realizes circuit.
Background technology
Half sampling type phaselocked loop as shown in Figure 1（Phase Locked Loop, hereinafter referred to as PLL）Job step such as
Under:Initially enter the FLL in Fig. 1（Frequency Locked Loop, hereinafter referred to as FLL）Pattern, makes PLL be locked in institute
The Frequency point of needs, then switches to core ring（Core Loop）, using half sampling type phase discriminator（Sub Sampling
Phase Detector, hereinafter referred to as SSPD）, PLL is locked in the phase of needs.In order that half sampling type phaselocked loop has
Preferable performance, then need a preferable charge pump（Charge Pump, hereinafter referred to as CP）To realize voltage to electric current
Conversion.
Existing CP's realizes the structure that structure can be as shown in Figure 2, by reference to clock（REF）Collection input is come in
Signal, and the differential signal that will be gathered（Vsam+With Vsam-Between voltage differential signal）Electric current Icp is converted into by CP.When sampling
When differential signal amplitude is zero, Iup=Idn, then the electric current of Icp is zero；Wherein, Iup is V in Fig. 2sam-By corresponding electricity
The current signal that stream mirror mirror image comes, Idn is V in Fig. 2sam+The current signal come by corresponding current mirror mirror image.Work as Icp
Electric current when being zero, the voltage of LPF keeps constant, so that voltage controlled oscillator（Voltage controlled
Oscillator, hereinafter referred to as VCO）Frequency of oscillation it is constant, PLL is in the lock state.When REF is low level, CP inputs
Signal is the oscillator signal of VCO（That is Vsam+With Vsam-Between voltage differential signal）, within a period of time, pulse signal Pul=0, this
The first way switch in on-off circuit on the left of sample Icp（The left side）Open, the second way switch is closed；Work as REF=1, and during Pul=1,
The second way switch in on-off circuit on the left of Icp（The right）Open.
But, in the prior art, when REF switches to high level from low level, have electric charge and be flowed into low pass by Icp
Wave filter（Low Pass Filter, hereinafter referred to as LPF）, i.e., electric charge can be produced shared and Charge injection effect, make on LPF
Voltage produces periodic ripple, causes LPF voltage changes, so as to influence the performance of PLL.
The content of the invention
What the embodiment of the present invention provided a kind of charge pump realizes circuit, is used to avoid what charge pump of the prior art was brought
Shared and Charge injection effect the problem of electric charge.
In a first aspect, the present invention provides a kind of circuit of realizing of charge pump, including：First current mirror, the second current mirror,
One on-off circuit, second switch circuit, connection circuit, the first unity gain amplifier, the second unity gain amplifier and pulse
Produce circuit；
Wherein, the output end of the output end of first current mirror and second current mirror is all connected with the first switch
The source electrode of the source electrode of circuit and the second switch circuit；The first end connection described first of first unity gain amplifier
The output end of the output end of current mirror and second current mirror, the second end connection of first unity gain amplifier is described
Connection circuit；The first end of second unity gain amplifier connects the input of the low pass filter LPF, described second
Second end of unity gain amplifier connects the connection circuit；The input of the LPF is connected to the second switch circuit
Drain electrode；The output end of the pulse-generating circuit is connected to the grid and the second switch circuit of the first switch circuit
Grid；
The connection circuit includes the first electric capacity and first switch pipe, for connecting first gain amplifier and described
Second gain amplifier；
First current mirror, the first voltage mirror image for voltage controlled oscillator VCO to be exported is the first electric current；
Second current mirror, the second voltage mirror image for the VCO to be exported is the second electric current；
The pulse-generating circuit, for generating pulse signal according to reference clock signal, the pulse signal is used to control
Make the on off state of the first switch circuit and the second switch circuit；
First unity gain amplifier and second unity gain amplifier, in the reference clock signal
During for low level, by the voltage of the output end of the first current mirror, voltage of the output end of second current mirror, described
The drain voltage of the voltage of LPF inputs and the first switch pipe keeps equal.
With reference in a first aspect, in the first possible implementation method of first aspect, first unit gain is amplified
The first end of device connects the output end of first current mirror and the output end of second current mirror, first unit gain
Second end of amplifier connects the connection circuit, including：
The first end of first unity gain amplifier is connected to first current mirror by the 3rd on-off circuit
Output end；
The first end of first unity gain amplifier is connected to second current mirror by the 4th on-off circuit
Output end；
Second end of first unity gain amplifier is connected to the drain electrode of the first switch pipe.
With reference in a first aspect, in second possible implementation method of first aspect, second unit gain is amplified
Second end of device connects the connection circuit, including：
Second end of second unity gain amplifier is connected to the drain electrode of the first switch pipe.
With reference in a first aspect, in the third possible implementation method of first aspect, the leakage of the first switch circuit
Pole passes through the second capacity earth.
Any one of the third possible implementation method with reference to first aspect to first aspect, the of first aspect
In four kinds of possible implementation methods, the pulse-generating circuit includes delay unit；The delay unit, it is fixed for producing
Delay time；
The then pulse-generating circuit, specifically for the delay time of the fixation according to produced by the delay unit
Enter line delay to the reference clock signal, and the reference clock signal after time delay is carried out with the reference clock signal before time delay
The pulse signal is produced after logic and operation.
With reference to the 4th kind of possible implementation method of first aspect, in the 5th kind of possible implementation method of first aspect
In, the delay unit includes the 3rd current mirror, second switch pipe, the 3rd switching tube, the 4th switching tube and the 3rd electric capacity；Its
In,
The output end of the 3rd current mirror is connected to the source electrode of the second switch pipe；The drain electrode of the second switch pipe
Drain electrode with the 3rd switching tube is connected, one end of the 3rd electric capacity and the drain electrode of the second switch pipe and described
The drain electrode of three switching tubes is connected, and the other end of the 3rd electric capacity is connected with the source electrode of the 4th switching tube；Described second
The grid of the grid of switching tube and the 3rd switching tube is connected to the output end of the reference clock；3rd switching tube
Source electrode is connected with the drain electrode of the 4th switching tube；Described 4th grid for opening the light pipe connects bias voltage output；
3rd current mirror, for being the 3rd electric current by the bias voltage mirror image of system, from the 3rd current mirror
Output end is exported.
Charge pump provided in an embodiment of the present invention realizes circuit, is increased by the first unity gain amplifier and second unit
Beneficial amplifier is by the input of the voltage of the output end of the first current mirror, the voltage of the output end of the second current mirror and LPF
Voltage keeps equal so that pulse signal is high level by low transition, and second switch circuit is switched to by closed mode and beaten
During open state, electric charge stream is not had and is entered in LPF, it is to avoid produce Charge injection effect, improve the performance of PLL.
Brief description of the drawings
In order to illustrate more clearly about the embodiment of the present invention or technical scheme of the prior art, below will be to embodiment or existing
The accompanying drawing to be used needed for having technology description is briefly described, it should be apparent that, drawings in the following description are this hairs
Some bright embodiments, for those of ordinary skill in the art, without having to pay creative labor, can be with
Other accompanying drawings are obtained according to these accompanying drawings.
The structural representation of the half sampling type phaselocked loop that Fig. 1 is provided for the present invention；
Fig. 2 is that charge pump of the prior art realizes circuit diagram；
The structural representation for realizing circuit embodiments one of the charge pump that Fig. 3 is provided for the present invention；
The structural representation of the pulse-generating circuit that Fig. 4 is provided for the present invention；
The electrical block diagram of the delay unit that Fig. 5 is provided for the present invention.
Brief description of the drawings：
10：First current mirror；11：Second current mirror；12：First switch circuit；
13：Second switch circuit；14：Connection circuit；15：First unity gain amplifier；
16：Second unity gain amplifier；17：Pulse-generating circuit；18：Low pass filter；
19：Voltage controlled oscillator；101：The output end of the first current mirror；
111：The output end of the second current mirror；151：The first end of the first unity gain amplifier；
152：Second end of the first unity gain amplifier；181：The input of low pass filter；
161：The first end of the second unity gain amplifier；131：The drain electrode of second switch circuit；
162：Second end of the second unity gain amplifier；
171：The output end of pulse-generating circuit；121：The grid of first switch circuit；
132：The grid of second switch circuit；141：First electric capacity；142：First switch pipe；
30：3rd on-off circuit；31：4th on-off circuit；
122：The source electrode of first switch circuit；133：The source electrode of second switch circuit；
123：The drain electrode of first switch circuit；143：Second electric capacity；
20：Delay unit；201：3rd current mirror；202：Second switch pipe；
203：3rd switching tube；204：3rd electric capacity；301：The output end of the 3rd current mirror；
302：The source electrode of second switch pipe；303：The drain electrode of second switch pipe；
304：The drain electrode of the 3rd switching tube；305：One end of 3rd electric capacity；
306：The other end of the 3rd electric capacity；307：The grid of second switch pipe；
308：The grid of the 3rd switching tube；309：The output end of reference clock；
310：The source electrode of the 3rd switching tube；311：4th switching tube；
312：The source electrode of the 4th switching tube；313：The drain electrode of the 4th switching tube；
314：4th grid for opening the light pipe；315：Bias voltage output.
Specific embodiment
To make the purpose, technical scheme and advantage of the embodiment of the present invention clearer, below in conjunction with the embodiment of the present invention
In accompanying drawing, the technical scheme in the embodiment of the present invention is clearly and completely described, it is clear that described embodiment is
A part of embodiment of the present invention, rather than whole embodiments.Based on the embodiment in the present invention, those of ordinary skill in the art
The every other embodiment obtained under the premise of creative work is not made, belongs to the scope of protection of the invention.
The structural representation for realizing circuit embodiments one of the charge pump that Fig. 3 is provided for the present invention.As shown in figure 3, the electricity
Road includes：First current mirror 10, the second current mirror 11, first switch circuit 12, second switch circuit 13, connection circuit 14, the
One unity gain amplifier 15, the second unity gain amplifier 16 and pulse-generating circuit 17.
Wherein, the output end 111 of the output end 101 of first current mirror 10 and second current mirror 11 is all connected with institute
State the source electrode 122 of first switch circuit 12 and the source electrode 133 of the second switch circuit 13；First unity gain amplifier
15 first end 151 connects the output end 101 of first current mirror 10 and the output end 111 of second current mirror 11, institute
The second end 152 for stating the first unity gain amplifier 15 connects the connection circuit 14；Second unity gain amplifier 16
First end 161 connect LPF18 input 181, the second end 162 of second unity gain amplifier 16 connects the company
Connect circuit 14；The input 181 of the LPF18 is connected to the drain electrode 131 of the second switch circuit 13；The pulses generation electricity
The output end 171 on road 17 is connected to the grid 121 of the first switch circuit 12 and the grid of the second switch circuit 13
132；The connection circuit 14 includes the first electric capacity 141 and first switch pipe 142, for connecting first gain amplifier 15
With second gain amplifier 16；First current mirror 10, the first voltage mirror image for VCO19 to be exported is the first electricity
Stream；Second current mirror 11, the second voltage mirror image for the VCO19 to be exported is the second electric current；The pulses generation
Circuit 17, for producing pulse signal according to reference clock signal generation, the pulse signal is for controlling the first switch
The on off state of circuit 12 and the second switch circuit 13；First unity gain amplifier 15 and second unit increase
Beneficial amplifier 16, for reference clock signal be low level when, by the voltage of the output end 101 of first current mirror 10,
The voltage of the output end 111 of second current mirror 11, the voltage of the input 181 of the LPF18 and the first switch
The drain voltage of pipe 142 keeps equal.
It should be noted that the first current mirror 10, the second current mirror 11, first switch circuit 12, second switch in Fig. 3
The method of the connection of circuit 13 and pulse-generating circuit 17 can have various, for example, may refer to the connected mode shown in Fig. 2,
The embodiment of the present invention be it is a kind of simple illustrate, as long as the two-way voltage difference mirror image for guaranteeing to export VCO19 be Iup or
Idn, and first switch circuit 12 and second switch circuit 13 are input to, and the pulse signal energy that pulse-generating circuit 17 is produced
Enough control the on off state of first switch circuit 12 and second switch circuit 13.In addition, first switch circuit 12 and second
On-off circuit is not shown in figure 3, is referred to the first switch circuit and second switch circuit marked in Fig. 2.
Specifically, referring to Fig. 3, VCO19 output first voltage and second voltage；Here first voltage can be Vsam+,
Can also be Vsam-；Second voltage can be Vsam+, or Vsam-.When first voltage is Vsam+When, second voltage is Vsam-；
When first voltage is Vsam-When, second voltage is Vsam+.In embodiments of the present invention, it is assumed that first voltage is Vsam+, second voltage
It is Vsam-.First voltage mirror image is Iup by the first current mirror 10, and second voltage mirror image is Idn by the second current mirror 11.Here
The output end 101 of the first current mirror 10 is actually the drain electrode of the first current mirror 10, i.e. the drain electrode of Iup from the first current mirror 10 is defeated
Go out；Accordingly, Idn is exported from the drain electrode of the second current mirror 11.
Pulse-generating circuit 17 shown in Fig. 3 is only logical circuitry, and its specific implementation may refer to shown in Fig. 4
（Delay unit 20 in Fig. 4 can be described behind the embodiment）.Pulse-generating circuit 17 can be according to reference clock signal
And after the reference clock signal after time delay carries out the operation of logical AND, form pulse signal（Pul）, the pulse signal can control
First switch circuit 12 processed and second switch circuit 13 open or close state.Here first switch circuit 12 and second is opened
The connected mode of two metal-oxide-semiconductors in powered-down road 13 is referred to prior art.Pulse signal is defeated through pulse-generating circuit 17
Go out the grid 121 and the grid 132 of second switch circuit 13 of the output of end 171 to first switch circuit 12, when the pulse signal
When level is low level, first switch circuit 12 is opened, and second switch circuit 13 is closed, at this moment the input of whole CP
Signal is the voltage difference between the oscillator signal of VCO19, i.e. first voltage and second voltage, and voltage difference treatment is continuous
The state of change.That is, first voltage and second voltage is unequal, is also not equal to the voltage of LPF18 inputs.That is, the
The voltage three of the input 181 of the drain voltage of one current mirror 10, the drain voltage of the second current mirror 11 and LPF18 is mutual not
It is equal.
In the prior art, because the drain voltage of the first current mirror 10, the drain voltage and LPF18 of the second current mirror 11
The voltage three of input 181 be not mutually equal, when the level of pulse signal is high level, second switch circuit 13 can be by original
The closed mode come switches to open mode.In the moment of the switching of second switch circuit 13, because first switch circuit 12 is opened
When, the voltage of the input 181 of the drain voltage of the first current mirror 10, the drain voltage of the second current mirror 11 and LPF18 by
In existing voltage difference before, therefore, have electric charge and be flowed into LPF18, cause electric charge shared or Charge injection effect, so that
So that producing periodic ripple on LPF18, the performance of PLL is influenceed.
But, in embodiments of the present invention, due to the output end 101 of the first current mirror 10（That is the leakage of the first current mirror 10
Pole）With the output end 111 of the second current mirror 11（That is the drain electrode of the second current mirror 11）With the of the first unity gain amplifier 15
One end 151 connects；Second end 152 of the first unity gain amplifier 15 connects with circuit 14 is connected.Due to the first unit gain
The effect of amplifier 15 so that the voltage in the first end 151 of the first unity gain amplifier 15 is put equal to the first unit gain
The voltage at the second end 152 of big device 15；Again because the second end 152 of the first unity gain amplifier 15 connects with circuit 14 is connected
Connect, so the voltage at the second end 152 of the first unity gain amplifier 15 is equal to the first switch pipe 142 in connection circuit 14
Drain voltage；That is, the drain electrode of the voltage of the first end 151 of the first unity gain amplifier 15 and first switch pipe 142
Voltage is equal, also, the current mirror 11 of output end 101 and second due to the first current mirror 10 the unit of output end 111 and first
The first end 151 of gain amplifier 15 is connected, therefore, the voltage of the output end 101 of the first current mirror 10 and the second current mirror 11
The voltage of output end 111 be also equal to the drain voltage of first switch pipe 142.
On the other hand, the input 181 of LPF18（That is the port where Icp）With the of the second unity gain amplifier 16
One end 161 is connected, and the first unity gain amplifier 15 is connected with the second unity gain amplifier 16 by connecting circuit 14, the
Second end 162 of two unity gain amplifiers 16 connects with circuit 14 is connected.Due to the effect of the second unity gain amplifier 16,
So that the voltage in the first end 161 of the second unity gain amplifier 16 is equal to the second end of the second unity gain amplifier 16
162 voltage；Again because the second end 162 of the second unity gain amplifier 16 connects with circuit 14 is connected, so the second unit
The voltage at the second end 162 of gain amplifier 16 is equal to the drain voltage of the first switch pipe 142 in connection circuit 14；Namely
Say, the voltage of the first end 161 of the second unity gain amplifier 16 is equal with the drain voltage of first switch pipe 142, also, by
In the first end 161 and the input 181 of LPF18 of the second unity gain amplifier 16（That is the port where Icp）Connection, because
This, the voltage of the input 181 of LPF18 is also equal to the drain voltage of first switch pipe 142
Therefore, the embodiment of the present invention can be by the first unity gain amplifier 15 and the second unity gain amplifier 16 by
The input 181 of the voltage of the output end 101 of one current mirror 10, the voltage of the output end 111 of the second current mirror 11 and LPF18
Voltage conversion is equal（I.e. so that this three is equal to the drain voltage of first switch pipe 142）, i.e., do not deposited between this three
In voltage difference, so as to when pulse signal is high level, second switch circuit 13 is switched to the wink of open mode by closed mode
Between, electric current is not had and flows into LPF18, i.e., electric charge is not had and is injected into LPF18 the insides, hereby it is ensured that the performance of PLL.
Charge pump provided in an embodiment of the present invention realizes circuit, is increased by the first unity gain amplifier and second unit
Beneficial amplifier is by the input of the voltage of the output end of the first current mirror, the voltage of the output end of the second current mirror and LPF
Voltage keeps equal so that pulse signal is high level by low transition, and second switch circuit is switched to by closed mode and beaten
During open state, electric charge stream is not had and is entered in LPF, it is to avoid produce Charge injection effect, improve the performance of PLL.
Further, with continued reference to Fig. 3, the first end 151 of above-mentioned first unity gain amplifier 15 connects described first
The output end 111 of the current mirror 11 of output end 101 and second of current mirror 10, is specifically as follows：First unity gain amplifier 15
First end 151 can be connected with the output end 101 of the first current mirror 10 by the 3rd on-off circuit 30, the first unit gain is put
The first end 151 of big device 15 can be connected by the 4th on-off circuit 31 with the output end 111 of the second current mirror 11, the first unit
Second end 152 of gain amplifier 15 connects the connection circuit 14.
Further, with continued reference to Fig. 3, the second end 152 and second of above-mentioned first unity gain amplifier 15 is single
Second end 162 of position gain amplifier 16 be connected circuit 14 connected, is specifically as follows：First unity gain amplifier 15
Second end 152 connects with the drain electrode for being connected first switch pipe 142 in circuit 14, the second end of the second unity gain amplifier 16
162 drain electrodes for being connected to first switch pipe 142, so as to realize the first unity gain amplifier 15 and the second unity gain amplifier
16 connection.In addition, the drain electrode 123 of above-mentioned first switch circuit 12 is grounded by the second electric capacity 143, the second electric capacity is in figure 3
It is not shown, may refer to the second electric capacity shown in Fig. 2.
Charge pump provided in an embodiment of the present invention realizes circuit, is increased by the first unity gain amplifier and second unit
Beneficial amplifier is by the input of the voltage of the output end of the first current mirror, the voltage of the output end of the second current mirror and LPF
Voltage keeps equal so that pulse signal is high level by low transition, and second switch circuit is switched to by closed mode and beaten
During open state, electric charge stream is not had and is entered in LPF, it is to avoid produce Charge injection effect, improve the performance of PLL.
In pulse-generating circuit 17 shown in above-mentioned Fig. 4, after the generation of pulse signal needs to refer to clock signal and time delay
Reference clock signal carry out logical AND operation, although pulse-generating circuit of the prior art 17 is also the connection using Fig. 4
Mode generates pulse signal, but the time delay of reference clock signal is to cascade to form by common phase inverter in the prior art,
At different technique, different voltage or different temperature, the time delay of phase inverter easily produces change, so that the arteries and veins for producing
The change width for rushing signal is very big, so as to the stability of the systematic parameter of whole PLL can be influenceed, and then influences the performance of PLL.But
It is that in embodiments of the present invention, the delay unit 20 shown in Fig. 4 can produce fixed delay time, and it is not with extraneous ring
The change in border and change, then above-mentioned pulse-generating circuit 17, the delay time of the fixation produced according to the delay unit 20 is to ginseng
Examine clock signal and enter line delay, and the reference clock signal before the reference clock signal after time delay and time delay is carried out into logical AND fortune
Pulse signal is produced after calculation.The circuit that implements of the delay unit 20 may refer to following Fig. 5.
As shown in figure 5, the delay unit 20 includes：3rd current mirror 201, second switch pipe 202, the 3rd switching tube 203,
4th switching tube 311 and the 3rd electric capacity 204；Wherein, the output end 301 of the 3rd current mirror 201 is connected to described second and opens
Close the source electrode 302 of pipe 202；The drain electrode 303 of the second switch pipe 202 is connected with the drain electrode 304 of the 3rd switching tube 203
Connect, one end 305 of the 3rd electric capacity 204 and the drain electrode 303 of the second switch pipe 202 and the 3rd switching tube 203
Drain electrode 304 is connected, and the other end 306 of the 3rd electric capacity 204 is connected with the source electrode 312 of the 4th switching tube 311；It is described
The grid 308 of the grid 307 of second switch pipe 202 and the 3rd switching tube 203 is connected to the output end of the reference clock
309；The source electrode 310 of the 3rd switching tube 203 is connected with the drain electrode 313 of the 4th switching tube 311；Described 4th opens the light pipe 311
Grid 314 connection bias voltage output 315；3rd current mirror 201, for being the by the bias voltage mirror image of system
Three electric currents, export from the output end 301 of the 3rd current mirror 201.
Specifically, circuit system can provide the bias voltage of a fixation, the bias voltage is through the mirror image of the 3rd current mirror 201
3rd electric current, from the output end 301 of the 3rd current mirror 201（That is the drain electrode of the 3rd current mirror 201）Output.Now, reference clock
Output end 309 export a reference clock signal（That is external reference clock）, when the reference clock signal is low level, second
Switching tube 202 is opened（The second switch pipe 202 is a PMOS）, the 3rd electric current is the 3rd electric capacity via second switch pipe 202
204 charge；When reference clock signal switches to high level, the 3rd switching tube 203 is opened（3rd switching tube 203 is one
NMOS tube）, the 3rd electric capacity 204 discharged for the 3rd switching tube 203 with the 4th switching tube 311（4th switching tube 311 is the 3rd
Electric capacity 204 provides constant electric current when discharging）.The discharge time is the delay time of the delay unit 20.Optionally, second
Switching tube 202 can also be NMOS tube, the 3rd switching tube 203 can also PMOS, simply the level of reference clock signal also should
Switched accordingly, i.e., the level of reference clock signal should be first height after it is low.It should be noted that shown in Fig. 5 two
The situation that individual delay unit 20 is cascaded.
Because above-mentioned bias voltage is fixed, therefore, the 3rd electric current is fixed, therefore the 3rd electric capacity 204 being preserved when charging
The quantity of electric charge fix；The 4th switching tube 311 can provide constant discharge current again, therefore, what the 3rd electric capacity 204 was discharged
Time is also just fixed, so that the delay time of the delay unit 20 is fixed, and then causes the arteries and veins produced by pulse-generating circuit 17
The mobility scale for rushing the width of signal reduces, that is, reduce the change width of pulse signal.
Charge pump provided in an embodiment of the present invention realizes circuit, is increased by the first unity gain amplifier and second unit
Beneficial amplifier is by the input of the voltage of the output end of the first current mirror, the voltage of the output end of the second current mirror and LPF
Voltage keeps equal so that pulse signal is high level by low transition, and second switch circuit is switched to by closed mode and beaten
During open state, electric charge stream is not had and is entered in LPF, it is to avoid produce Charge injection effect；In addition, producing fixation by delay unit
Delay time so that pulse-generating circuit output pulse signal width change reduce, it is ensured that pll system it is steady
It is fixed, improve the performance of PLL.
Finally it should be noted that：Various embodiments above is merely illustrative of the technical solution of the present invention, rather than its limitations；To the greatest extent
Pipe has been described in detail with reference to foregoing embodiments to the present invention, it will be understood by those within the art that：Its according to
The technical scheme described in foregoing embodiments can so be modified, or which part or all technical characteristic are entered
Row equivalent；And these modifications or replacement, the essence of appropriate technical solution is departed from various embodiments of the present invention technology
The scope of scheme.
Claims (6)
1. a kind of charge pump realizes circuit, it is characterised in that including：First current mirror, the second current mirror, first switch electricity
Road, second switch circuit, connection circuit, the first unity gain amplifier, the second unity gain amplifier and pulse-generating circuit；
Wherein, the output end of the output end of first current mirror and second current mirror is all connected with the first switch circuit
Source electrode and the second switch circuit source electrode；The first end of first unity gain amplifier connects first electric current
The output end of the output end of mirror and second current mirror, the second end of first unity gain amplifier connects the connection
Circuit；The input of the first end connection low pass filter LPF of second unity gain amplifier, second unit gain
Second end of amplifier connects the connection circuit；The input of the LPF is connected to the drain electrode of the second switch circuit；Institute
The output end for stating pulse-generating circuit is connected to the grid of the first switch circuit and the grid of the second switch circuit；
The connection circuit includes the first electric capacity and first switch pipe, for connecting first unity gain amplifier and described
Second unity gain amplifier；
First current mirror, the first voltage mirror image for voltage controlled oscillator VCO to be exported is the first electric current；
Second current mirror, the second voltage mirror image for the VCO to be exported is the second electric current；
The pulse-generating circuit, for generating pulse signal according to reference clock signal, the pulse signal is used to control institute
State the on off state of first switch circuit and the second switch circuit；
First unity gain amplifier and second unity gain amplifier, for being low in the reference clock signal
It is during level, the voltage of the output end of first current mirror, the voltage of the output end of second current mirror, the LPF is defeated
The drain voltage of the voltage and the first switch pipe that enter end keeps equal.
2. circuit according to claim 1, it is characterised in that the first end connection institute of first unity gain amplifier
The output end of the first current mirror and the output end of second current mirror are stated, the second end of first unity gain amplifier connects
The connection circuit is connect, including：
The first end of first unity gain amplifier is connected to the output of first current mirror by the 3rd on-off circuit
End；
The first end of first unity gain amplifier is connected to the output of second current mirror by the 4th on-off circuit
End；
Second end of first unity gain amplifier is connected to the drain electrode of the first switch pipe.
3. circuit according to claim 1, it is characterised in that the second end connection institute of second unity gain amplifier
Connection circuit is stated, including：
Second end of second unity gain amplifier is connected to the drain electrode of the first switch pipe.
4. circuit according to claim 1, it is characterised in that the drain electrode of the first switch circuit is connect by the second electric capacity
Ground.
5. the circuit according to claim any one of 1-4, it is characterised in that the pulse-generating circuit includes time delay list
Unit；The delay unit, for producing fixed delay time；
The then pulse-generating circuit, specifically for the fixation according to produced by the delay unit delay time to institute
State reference clock signal and enter line delay, and the reference clock signal before the reference clock signal after time delay and time delay is carried out into logic
With the pulse signal is produced after computing.
6. circuit according to claim 5, it is characterised in that the delay unit includes the 3rd current mirror, second switch
Pipe, the 3rd switching tube, the 4th switching tube and the 3rd electric capacity；Wherein,
The output end of the 3rd current mirror is connected to the source electrode of the second switch pipe；The drain electrode of the second switch pipe and institute
The drain electrode for stating the 3rd switching tube is connected, and one end and the drain electrode of the second switch pipe and the described 3rd of the 3rd electric capacity are opened
The drain electrode for closing pipe is connected, and the other end of the 3rd electric capacity is connected with the source electrode of the 4th switching tube；The second switch
The grid of the grid of pipe and the 3rd switching tube is connected to the output end of the reference clock；The source electrode of the 3rd switching tube
Drain electrode with the 4th switching tube is connected；Described 4th grid for opening the light pipe connects bias voltage output；
3rd current mirror, for being the 3rd electric current by the bias voltage mirror image of system, from the output of the 3rd current mirror
End output.
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201410112015.7A CN103887966B (en) | 2014-03-24 | 2014-03-24 | Charge pump realizes circuit |
| PCT/CN2015/073742 WO2015143980A1 (en) | 2014-03-24 | 2015-03-06 | Implementation circuit of charge pump |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201410112015.7A CN103887966B (en) | 2014-03-24 | 2014-03-24 | Charge pump realizes circuit |
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|---|---|
| CN103887966A CN103887966A (en) | 2014-06-25 |
| CN103887966B true CN103887966B (en) | 2017-06-20 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201410112015.7A Active CN103887966B (en) | 2014-03-24 | 2014-03-24 | Charge pump realizes circuit |
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| Country | Link |
|---|---|
| CN (1) | CN103887966B (en) |
| WO (1) | WO2015143980A1 (en) |
Families Citing this family (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103887966B (en) * | 2014-03-24 | 2017-06-20 | 华为技术有限公司 | Charge pump realizes circuit |
| US9184623B1 (en) * | 2015-04-23 | 2015-11-10 | Xilinx, Inc. | Circuits for and methods of implementing a charge/discharge switch in an integrated circuit |
| CN112073065B (en) * | 2020-08-12 | 2023-03-14 | 西安电子科技大学 | Millimeter wave sub-sampling DDS (direct digital synthesizer) mixing decimal frequency division phase-locked loop structure |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5963025A (en) * | 1997-12-19 | 1999-10-05 | Stmicroelectronics, Inc. | Switching voltage regulator having a charge pump circuit |
| CN101488710A (en) * | 2008-10-22 | 2009-07-22 | 成都国腾电子技术股份有限公司 | A charge pump circuit |
| CN202111620U (en) * | 2011-06-30 | 2012-01-11 | 四川和芯微电子股份有限公司 | Charge pump circuit |
| CN202167988U (en) * | 2011-06-10 | 2012-03-14 | 安凯(广州)微电子技术有限公司 | Charge pump circuit for phase-locked loop |
Family Cites Families (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH11274920A (en) * | 1998-03-26 | 1999-10-08 | Nec Corp | Charging pump circuit for pll |
| JP3583646B2 (en) * | 1999-03-30 | 2004-11-04 | 株式会社ルネサステクノロジ | Phase locked loop |
| US6611161B1 (en) * | 2001-11-06 | 2003-08-26 | National Semiconductor Corporation | Charge pump circuit for a high speed phase locked loop |
| FR2834396B1 (en) * | 2002-01-03 | 2004-02-27 | Cit Alcatel | VERY WIDE LOAD PUMP OUTPUT VOLTAGE RANGE |
| TW541801B (en) * | 2002-05-23 | 2003-07-11 | Ind Tech Res Inst | Charge-pump circuit for suppressing current sharing |
| CN103887966B (en) * | 2014-03-24 | 2017-06-20 | 华为技术有限公司 | Charge pump realizes circuit |
-
2014
- 2014-03-24 CN CN201410112015.7A patent/CN103887966B/en active Active
-
2015
- 2015-03-06 WO PCT/CN2015/073742 patent/WO2015143980A1/en active Application Filing
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5963025A (en) * | 1997-12-19 | 1999-10-05 | Stmicroelectronics, Inc. | Switching voltage regulator having a charge pump circuit |
| CN101488710A (en) * | 2008-10-22 | 2009-07-22 | 成都国腾电子技术股份有限公司 | A charge pump circuit |
| CN202167988U (en) * | 2011-06-10 | 2012-03-14 | 安凯(广州)微电子技术有限公司 | Charge pump circuit for phase-locked loop |
| CN202111620U (en) * | 2011-06-30 | 2012-01-11 | 四川和芯微电子股份有限公司 | Charge pump circuit |
Also Published As
| Publication number | Publication date |
|---|---|
| WO2015143980A1 (en) | 2015-10-01 |
| CN103887966A (en) | 2014-06-25 |
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