CN103885819B - A kind of priority resources sharing method area-optimized for FPGA - Google Patents
A kind of priority resources sharing method area-optimized for FPGA Download PDFInfo
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- CN103885819B CN103885819B CN201210564207.2A CN201210564207A CN103885819B CN 103885819 B CN103885819 B CN 103885819B CN 201210564207 A CN201210564207 A CN 201210564207A CN 103885819 B CN103885819 B CN 103885819B
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Abstract
The invention discloses a kind of priority resources sharing method area-optimized for FPGA, including：RTL synthesis intermediate data structure netlists are read, searches and collects the branch of all sequential mutual exclusions in netlist；The concrete operations in the branch of sequential mutual exclusion are analyzed, detects and collects identical arithmetical operation in the branch of sequential mutual exclusion；And preferentially the arithmetical operation for having identical output is shared, secondly the arithmetical operation for there was only public input port is shared, the finally arithmetical operation to no public port is shared.Utilize the present invention, by the identical arithmetical operation for detecting sequential mutual exclusion in HDL design documents, these arithmetical operations are shared successively according to the order of regulation, it is possible to reduce ALU (ALU Arithmetic Logic Unit), reach area-optimized effect.
Description
Technical field
It is more particularly to a kind of the present invention relates to field programmable gate array (FPGA) and EDA Technique field
For the area-optimized priority resources sharing methods of FPGA.
Background technology
Resource-sharing refers to what two or more arithmetical operations to sequential mutual exclusion were realized with an ALU
Process, it is one of key method of FPGA complex optimums.
FPGA eda tools include：Comprehensive (synthesis), mapping (mapping), layout (placing), wiring
(routing), code stream generation (bit gen) and code stream download several parts such as (download), it has also become one ten, FPGA fields
Divide crucial part.The quality of eda tool directly affects realization and the effect of design.
Comprehensive (synthesis) is one of key component in FPGA eda tools, is to enter the design document of HDL descriptions
Row translation and optimization, are converted to the netlist of gate leve, and optimize.Its Optimization Dept.'s subpackage contains for area, sequential and power consumption
Optimization, the result of optimization directly determine the quality of design result.
Resource-sharing is one of important method area-optimized in FPGA synthesis, and it can reduce the arithmetical logic list of complexity
The number of member, is realized area-optimized.
In existing RTL synthesis (Register Transfer Level Synthesis) technology, resource sharing algorithm is endless
It is kind, cause the optimization that is likely to occur not thorough, and the problem of data stream conflicts mistake.
The content of the invention
(1) technical problems to be solved
In view of this, it is a primary object of the present invention to provide a kind of priority resources area-optimized for FPGA to share
Method, to solve the problems, such as that in RTL is integrated the optimization that is likely to occur of resource-sharing is not thorough and data stream conflicts mistake.
(2) technical scheme
To reach above-mentioned purpose, the area-optimized priority resources sharing methods of FPGA are directed to the invention provides a kind of,
Including：RTL synthesis intermediate data structure netlists are read, searches and collects the branch of all sequential mutual exclusions in netlist；Analyze sequential
Concrete operations in the branch of mutual exclusion, detect and collect identical arithmetical operation in the branch of sequential mutual exclusion；And preferentially to having
The arithmetical operation of identical output is shared, and secondly the arithmetical operation for there was only public input port is shared, finally to not having
The arithmetical operation for having public port is shared.
In such scheme, the reading RTL integrates intermediate data structure netlist, searches and to collect all sequential in netlist mutual
In the step of branch of reprimand, at any time, at most only a branch performs for sequential mutual exclusion branch in every group, these branches bag
If, else branch and case different branches are included, and includes the different input branches of mux in structural level description.
In such scheme, the concrete operations in the branch of the analysis sequential mutual exclusion, detect and collect point of sequential mutual exclusion
In branch the step of identical arithmetical operation in, just for complexity arithmetical operation shared, do not consider logical operation.
It is described preferentially to there is the arithmetical operation of identical output to carry out in shared step in such scheme, it is preferentially to even
The arithmetical operation for being connected to same mux is shared, and shared concrete operations include：Every group of mutual exclusion branch can be merged first
Two or more arithmetical operation units merge into an arithmetical operation A；Secondly the identical arithmetic of every group of mutual exclusion branch is detected
Either with or without public input port between operation, public port is connected to an arithmetical operation A input；By output end
Mux moves to input, to select the drive signal of not common input port.
In such scheme, the arithmetical operation of described pair of only public input port carries out shared step, including：First will be every
Two or more arithmetical operation units that group mutual exclusion branch can merge merge into an arithmetical operation, and public port is connected
To an input of the arithmetical operation, another input adds a mux to select the driving of not common input port to believe
Number, output end then drives multiple modules.
In such scheme, the arithmetical operation of described pair of no public port carries out shared step, including：It is first mutual by every group
Two or more arithmetical operation units that reprimand branch can merge merge into an arithmetical operation, and two inputs add respectively
One mux selects drive signal, and output end then drives multiple modules.
(3) beneficial effect
It can be seen from the above technical proposal that the invention has the advantages that：
1st, the priority resources sharing method area-optimized for FPGA provided by the invention, is on the basis of resource-sharing
On improvement project, sharable resource is shared successively according to the priority orders of regulation.It can not only so avoid
Data stream conflicts mistake, but also can reduce the increased mux quantity of result.
2nd, the priority resources sharing method area-optimized for FPGA provided by the invention, first has to collect all sequential
The branch of mutual exclusion, it is sequential mutual exclusion between each group of different branches such as if, else branch and case branches, i.e., institute is sometimes
Carve at most only branch's execution.It so just can guarantee that shared is not in later signal conflict.Secondly, detect per component
Branch, marks the identical arithmetical operation of different branches, these arithmetical operations is shared according to the priority orders of regulation.
3rd, the priority resources sharing method area-optimized for FPGA provided by the invention, sharing operation reduce complexity
ALU number, realize area-optimized.This method is only shared to arithmetical operation, logical operation is not shared.Because
The Area comparison that ALU takes is big, total to know from experience reduction area although mux may be introduced.And to logic unit
Shared process is carried out, reduces logic unit, adds mux, as a result area is not necessarily reduced.
4th, the priority resources sharing method area-optimized for FPGA provided by the invention, on the basis of resource-sharing
It is improved, as a result while arithmetical operation number is reduced, also increased mux quantity is reduced, or even some situations are not
Mux can be increased；It would also avoid the error result that combined loop produces data stream conflicts occur during resource-sharing simultaneously.
Brief description of the drawings
Fig. 1 is the flow chart of the priority resources sharing method area-optimized for FPGA provided by the invention；
Fig. 2 is the schematic diagram that RLT integrates netlist Zhong Liangge mutual exclusions branch in Fig. 1；
Fig. 3 is the schematic diagram for marking identical arithmetical operation in Fig. 1 in RTL synthesis in mutual exclusion branch；
Fig. 4 be according to first embodiment of the invention hdl file description and do not use the netlist schematic diagram of resource-sharing；
Fig. 5 is the shared result signal of the resource share method for not using priority according to first embodiment of the invention
Figure；
Fig. 6 is the result schematic diagram shared using priority resources according to first embodiment of the invention；
Fig. 7 be according to second embodiment of the invention hdl file description and do not use the netlist schematic diagram of resource-sharing；
Fig. 8 is not use the shared shared result schematic diagram of priority resources according to second embodiment of the invention；
Fig. 9 is the result schematic diagram using priority resources sharing method according to second embodiment of the invention；
Figure 10 a are the schematic diagrames before two sequential mutual exclusion adder optimization；
Figure 10 b are the schematic diagrames that two sequential mutual exclusion adder resource-sharing steps are decomposed；
Figure 10 c are the result schematic diagrams after two sequential mutual exclusion adder optimization.
Embodiment
For the object, technical solutions and advantages of the present invention are more clearly understood, below in conjunction with specific embodiment, and reference
Accompanying drawing, the present invention is described in more detail.
As shown in figure 1, Fig. 1 is the flow of the priority resources sharing method area-optimized for FPGA provided by the invention
Figure, this method comprise the following steps：
Step S1, RTL synthesis intermediate data structure netlists are read, searches and collects point of all sequential mutual exclusions in netlist
Branch；
At any time, at most only a branches perform for sequential mutual exclusion branch in every group.These branches mainly include if,
Else branches and case different branches, mux different input branches in also being described including structural level, as shown in Fig. 2 two add
Method operation is one group of sequential mutual exclusion branch, and at most only an adder performs at any time.
Step S2, the concrete operations in the branch of sequential mutual exclusion are analyzed, detects and collects identical in the branch of sequential mutual exclusion
Arithmetical operation；
Present invention is only intended for the arithmetical operation of complexity to be shared, and does not consider logical operation.As shown in figure 3, mark two
Identical add operation between individual mutual exclusion branch.
Step S3, preferentially to there is identical output, the arithmetical operation for being attached to same mux is shared.
As shown in figure 4, the result of resource-sharing is not used in the first embodiment, comprising 3 adders ADD1, ADD2 and
ADD3, wherein ADD2 and ADD3 output are connected to same mux, and preferentially ADD2 and ADD3 are shared.
Shared concrete operations are divided into the following steps：(1) first can merge every group of mutual exclusion branch two or more
Individual arithmetical operation unit merges into an arithmetical operation A, as shown in Figure 10 a；(2) the identical calculation of every group of mutual exclusion branch is secondly detected
Either with or without public input port between art operation, public port is connected to an A input；(3) mux of output end is translated
To input, to select the drive signal of not common input port, as shown in fig. lob.Result after optimization is as shown in figure l0c.
Step S4, secondly the arithmetical operation of there was only public input port is shared, first can be with by every group of mutual exclusion branch
Two or more the arithmetical operation units merged merge into an arithmetical operation A, by public port be connected to one of A it is defeated
Enter, another input adds a mux to select the drive signal of not common input port, and output end then drives multiple moulds
Block.
Step S5, the arithmetical operation finally to no public port is shared, and first can merge every group of mutual exclusion branch
Two or more arithmetical operation units merge into an arithmetical operation A, two inputs add a mux to select respectively
Drive signal, output end then drive multiple modules.
Advantages of the present invention is as follows：
One compares with common resource-sharing, and the priority resources area-optimized for FPGA provided by the invention are shared
Method can reduce mux quantity.As shown in figure 4, include 3 additions without the result of resource-sharing in the first embodiment
Device, 1 mux；If not using the resource-sharing of priority approach, as shown in figure 5, ADD1 and ADD3 is carried out in the first embodiment
It is shared, as a result：2 adders and 3 mux；Using the resource share method of priority, as shown in fig. 6, in the first embodiment
ADD2 and ADD3 are shared, as a result only two adders and two mux, and being compared with Fig. 4 reduces an adder, and figure
5 compared to reducing a mux.
2nd, data stream conflicts mistake is avoided.The second embodiment of the present invention is not as shown in fig. 7, use the comprehensive of resource-sharing
Close result and contain 4 adders and 1 mux.If not using the resource share method of priority, as a result as shown in figure 8, this second
ADD1 and ADD4 share in embodiment, and ADD2 and ADD3 share, and can produce 2 adders and 5 mux, and combination occurs
Loop, produce the error result of data stream conflicts.Using the resource-sharing of priority, as a result as shown in figure 9, the second embodiment
Middle ADD2 and ADD4 share, and ADD1 and ADD3 share, and as a result containing 2 adders and 3 mux, being compared with Fig. 7 reduces 2
Adder, and be not in combined loop, being compared with Fig. 8 reduces 2 mux.
The priority resources sharing method area-optimized for FPGA provided by the invention, its result and common resource are total to
Enjoy and comparing, mux quantity can be reduced, preferably realize area-optimized；In some cases, while reducing mux, decrease
The series of mux delays, timing results are preferable.This method would also avoid data stream conflicts, prevent shared result from combined loop occur
Error result.
Particular embodiments described above, the purpose of the present invention, technical scheme and beneficial effect are carried out further in detail
Describe in detail it is bright, should be understood that the foregoing is only the present invention specific embodiment, be not intended to limit the invention, it is all
Within the spirit and principles in the present invention, any modification, equivalent substitution and improvements done etc., it should be included in the guarantor of the present invention
Within the scope of shield.
Claims (3)
- A kind of 1. priority resources sharing method area-optimized for FPGA, it is characterised in that including：RTL synthesis intermediate data structure netlists are read, searches and collects the branch of all sequential mutual exclusions in netlist；The concrete operations in the branch of sequential mutual exclusion are analyzed, detects and collects identical arithmetical operation in the branch of sequential mutual exclusion； AndPreferentially the arithmetical operation for having identical output is shared, secondly the arithmetical operation for there was only public input port is total to Enjoy, the finally arithmetical operation to no public port is shared；Wherein, it is described preferentially to there is the arithmetical operation of identical output to carry out in shared step, it is preferentially same to being connected to Mux arithmetical operation is shared, and shared concrete operations include：Every group of mutual exclusion branch can be merged first two or Multiple arithmetical operation units merge into an arithmetical operation A；Secondly have between the identical arithmetical operation of every group of mutual exclusion branch of detection There is no public input port, public port is connected to an A input；The mux of output end is moved into input, to select The drive signal of not common input port；The arithmetical operation of described pair of only public input port carries out shared step, including：First can be with by every group of mutual exclusion branch Two or more the arithmetical operation units merged merge into an arithmetical operation, and public port is connected into the arithmetical operation One input, another input add a mux to select the drive signal of not common input port, and output end then drives Multiple modules；The arithmetical operation of described pair of no public port carries out shared step, including：First every group of mutual exclusion branch can be merged Two or more arithmetical operation units merge into an arithmetical operation, two inputs add a mux to select respectively Drive signal, output end then drive multiple modules.
- 2. the priority resources sharing method area-optimized for FPGA according to claim 1, it is characterised in that described RTL synthesis intermediate data structure netlists are read, in the step of searching and collecting the branch of all sequential mutual exclusions in netlist, any At the moment, at most only a branches perform for sequential mutual exclusion branch in every group, and these branches include if, else branch and case not Same branch, and include the different input branches of mux in structural level description.
- 3. the priority resources sharing method area-optimized for FPGA according to claim 1, it is characterised in that described The concrete operations in the branch of sequential mutual exclusion are analyzed, the step of detecting and collect identical arithmetical operation in the branch of sequential mutual exclusion In, the arithmetical operation just for complexity is shared, and does not consider logical operation.
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| CN105930609B (en) * | 2016-05-04 | 2018-12-14 | 华中科技大学 | A kind of FPGA timing optimization method for coherent demodulation |
| CN111027267B (en) * | 2019-11-13 | 2021-01-19 | 广东高云半导体科技股份有限公司 | Method, device and system for realizing optimization of adder in FPGA (field programmable Gate array) logic synthesis |
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