CN103884931A - Testing and recording device for load characteristics of transformer substation bus - Google Patents

Abstract

The invention discloses a testing and recording device for load characteristics of a transformer substation bus. Three-phase voltage and three-phase current signals of a bus secondary cable are acquired through a signal conditioning module, the signals are conditioned, each path of signal is adjusted into a voltage range in which acquisition can be conducted by an analog-digital conversion module of the device, the signals are filtered through an anti-aliasing filter module to be input into the analog-digital conversion module, the analog-digital conversion module is controlled by a control module to sample the signals to obtain acquisition data of the three-phase voltage and a three-phase current, the acquisition data are forwarded to an upper computer, the upper computer conducts load parameter identification on a selected load module according to the acquisition data, and a load parameter identification result is stored and uploaded according to an instruction. According to the testing and recording device for load characteristics of the transformer substation bus, distributed computation of load parameter identification is achieved, and it is unnecessary to collect data by workers on site. Although the load parameter identification result will be uploaded, the data volume of the load parameter identification result is less than the data volume measured in real time, and data transmission pressure of a power private network is low.

Description

A kind of substation bus bar part throttle characteristics test record device

Technical field

The invention belongs to power system load parameter identification field, more specifically say, relate to a kind of substation bus bar load characteristic test record device.

Background technology

The various methods of operation of electric system and the emergency processing of accident all draw as basis take emulation, so be only improved the accuracy of emulation, make the physical system of simulation result and actual motion identical as far as possible, accident prevention better, makes system science operation.In the model of emulation, the four large key parameters that the most directly affect electric system simulation result comprise: generator parameter, parameters of excitation system, governing system parameter and load parameter, ensure that the accuracy of above four parameters is to guarantee the prerequisite of emulation accuracy.

In reality, the parameter of most grid equipments is all used the measured value before design load or putting equipment in service.But owing to there are differences between actual motion condition and design and operation condition, between the actual parameter of grid equipment and operation parameter, often there is very big-difference.Therefore, be necessary load parameter in electrical network to monitor in real time, regularly according to actual measurement load parameter correction artificial load parameter, thus the accuracy of raising grid simulation.

Existing power circuit parameter identification and method of estimation are divided into three major types: the one, and method is distinguished in the total body examination of load based on metric data, the 2nd, based on the Component Based of survey sampling, the 3rd, based on the fault simulation method of fault fitting.Current trend is that the above three kinds of methods of integrated application are carried out load modeling, particular importance or the load bus with typicalness are distinguished to method carries out long-term observation by total body examination, set up its model and parameter scope at times, the load bus of the whole network is classified as basis take Component Based again, thereby realize the parameter of typical load node is generalized to other load buses, finally utilize fault simulation method to check load model.Visible, it is basic that total body examination distinguishes that method plays a part in this process.Total body examination distinguishes that the basic thought of method is that load is regarded as to an entirety, utilizes the electric weight of data collector from collection in worksite load bus, then determines load model parameters according to system identification theory.

Existing load modeling based on metric data and parameter identification method are with based on PMU(Phasor Measurement Unit, synchronous phase measuring in power system device) metric data is main, carry out parameter identification in conjunction with multiple period metric data, influencing each other between distinct device parameter can be avoided, and the impact of error in measurement on Parameter Estimation Precision can be reduced.

As " power grid parameter identification based on WAMS/SCADA hybrid measurement and estimation " literary composition in the 32nd the 5th phase of volume " Automation of Electric Systems " in 2008, disclosed method is first based on WAMS(Wide Area Measurement System, wide area monitoring system) metric data calculates relative residual error, and then to whether existing parameter error tentatively to judge, then use WAMS/SCADA(Supervisory Control And Data Acquisition, data acquisition and supervisor control) hybrid measurement data calculate the measuring error of every branch road, thereby pick out the branch road that has parameter error problem, finally use intelligent optimization method to estimate the correct parameter of branch road based on WAMS/SCADA combined amount data.The shortcoming of the method is: metric data is not to calculate on the spot, but is uploaded to net dispatching center of company of province or by movable storage device, data is copied and return to carry out Data Post to scene by technician by Data special web.

For another example in the 34th the 1st phase of volume " Automation of Electric Systems " in 2010 " the transmission line parameter On-line Estimation method based on PMU measured data ", disclosed method is to utilize distribution parameter and the accurate equivalent parameters of the on-the-spot PMU measurement result computational scheme of settling.Its PMU metric data is similarly non-and calculates on the spot, need to be by Data special web or artificial on-site collection.If carry out regional power network load modeling, the PMU data of settling on all load buses are uploaded simultaneously and will certainly be caused great data transmission pressure to data network, it is that electric system cannot be allowed that other important control signal transmission delays that this is caused cause other serious consequences.Carrying out PMU Data Collection by technician to scene can be to the significant wastage of manpower and materials.

Summary of the invention

The object of the invention is to overcome the deficiencies in the prior art, a kind of substation bus bar load characteristic test record device is provided, automatically gather bus three-phase voltage and three-phase current data, directly carry out load parameter identification in this locality, carry out load parameter identification result according to the query statement at electrical network center and upload.

For achieving the above object, substation bus bar load characteristic test record device of the present invention, comprises signal condition module, anti-aliasing module, analog-to-digital conversion module, synchronizing signal source module, control module, host computer, wherein:

Signal condition module is for gathering three-phase voltage and the three-phase current signal of substation bus bar secondary cable under full operating mode, amount to 6 tunnel simulating signals, and be adjusted in the collectable voltage range of device analog-to-digital conversion module the 6 tunnel conditioned signal access anti-aliasing filter modules that obtain by the no-load voltage ratio Jiang Mei road signal designing;

Anti-aliasing filter module is for carrying out anti-aliasing filter to 6 tunnel conditioned signal of signal condition module output;

Analog-to-digital conversion module, under synchronous triggering clock and logic control signal control in control module output, is sampled to anti-aliasing filtered 6 road signals, by the image data input control module of three-phase voltage and three-phase current;

Synchronizing signal source module sends to control module for generation of synchronous clock source signal;

Control module, for generating synchronous triggering signal according to synchronous clock source signal, generates collection control signal and sends to together analog-to-digital conversion module, receives image data and is also transmitted to host computer;

Host computer is for receiving the image data of three-phase voltage and three-phase current, and select as required load model to carry out load parameter identification, by the load parameter identification result storage obtaining, start or stop and upload load parameter identification result according to the instruction at electrical network center.

Substation bus bar load characteristic test record device of the present invention, adopt signal condition module to gather three-phase voltage and the three-phase current signal of bus secondary cable, and signal is nursed one's health, Jiang Mei road signal is adjusted in the collectable voltage range of device analog-to-digital conversion module, signal is inputted to analog-to-digital conversion module after anti-aliasing filter module filtered, analog-to-digital conversion module is sampled and is obtained the image data of three-phase voltage and three-phase current signal under the control of control module, and be transmitted to host computer by control module, host computer carries out load parameter identification according to the load model of image data and selection, by the load parameter identification result storage obtaining and query interface power supply network center inquiry is provided, synchronizing signal source module is for generation of synchronous clock source signal, and is transmitted to analog-to-digital conversion module by control module.

Substation bus bar load characteristic test record device of the present invention, thus realize the Distributed Calculation of load parameter identification by integrated load parameter identification.The present invention is without artificial on-site collection data, use manpower and material resources sparingly, although can upload load parameter identification result, its data volume is fewer than real-time measurement data volume, and the parameter identification result private network data transmission pressure that can not increase electric power is too much being had access at electrical network center.

Accompanying drawing explanation

Fig. 1 is the hardware schematic diagram of substation bus bar load characteristic test record device of the present invention;

Fig. 2 is signal condition module diagram;

Fig. 3 is anti-aliasing module diagram;

Fig. 4 is analog-to-digital conversion module schematic diagram;

Fig. 5 is control module schematic diagram;

Fig. 6 is the application schematic diagram of substation bus bar load characteristic test record device of the present invention.

Embodiment

Below in conjunction with accompanying drawing, the specific embodiment of the present invention is described, so that those skilled in the art understands the present invention better.Requiring particular attention is that, in the following description, in the time that perhaps the detailed description of known function and design can desalinate main contents of the present invention, these are described in here and will be left in the basket.

Embodiment

Fig. 1 is the hardware schematic diagram of substation bus bar load characteristic test record device of the present invention.As shown in Figure 1, substation bus bar load characteristic test record device of the present invention comprises signal condition module 1, anti-aliasing module 2, analog-to-digital conversion module 3, synchronizing signal source module 4, control module 5, host computer 6.

Signal condition module 1 has built the signal path between substation bus bar secondary cable and apparatus of the present invention.Signal condition module 1 gathers three-phase voltage and the three-phase current signal of substation bus bar secondary cable under full operating mode, amount to 6 tunnel simulating signals, and be adjusted in the collectable voltage range of device analog-to-digital conversion module 3 the 6 tunnel conditioned signal access anti-aliasing filter modules 2 that obtain by the no-load voltage ratio Jiang Mei road signal designing.

Fig. 2 is signal condition module diagram.As shown in Figure 2, signal condition module 1 comprises voltage modulate circuit and current regulating circuit.The present embodiment adopts the electric current and voltage General mutual inductor of high precision (<0.05%) high linearity (<0.1%), voltage transformer (VT) 11 is for gathering three-phase voltage signal, connection is in phase line input end series limiting resistor, current transformer 12 is for gathering three-phase current signal, and connection is directly secondary cable punching to be accessed.Two mutual inductors are inputted respectively corresponding differential amplifier input stage 13 after collecting voltage/current signals, differential amplifier input stage 13 comprises two input stage amplifiers, the anode output of mutual inductor is linked into the first input stage amplifier negative terminal, is linked in analog the first input stage amplifier anode; Mutual inductor negative terminal output access the second input stage amplifier negative terminal, is linked into the second input stage amplifier anode in analog.Two input stage amplifiers are selected same model, with batch the amplifier of production, build thus the differential amplifier input stage of full symmetric.And the parameters such as the input noise of two input stage amplifiers, offset voltage and drift thereof, offset current and drift thereof, the bigoted electric current of input are all identical.Because input stage circuit has symmetry, mutual inductor output signal is inputted intergrade amplifier 14 after differential amplifier input stage 13 is amplified conditioning, the input stage amplifier noise carrying and power supply ripple are offset mutually after intergrade amplifier 14, ensure precision and the degree of stability of modulate circuit.Intergrade amplifier 14 output signal access voltage followers 15, in the present embodiment, intergrade amplifier 14 is selected accurate rail-to-rail operation amplifier.The input end of voltage follower 15 adopts clamper resist technology, ensures that the conditioned signal that signal condition module 1 is exported is no more than the maximum input range of analog-to-digital conversion module 3.Visible, the 6 tunnel conditioned signal that signal condition module 1 obtains are voltage signal.

In order to ensure modulate circuit high precision, resistance in the present embodiment in signal condition module 1 all adopts high precision (0.01%) noninductive resistance, and amplifier is selected high cmrr (150dB), high PSRR (145dB), low noise, low imbalance precision operational-amplifier.

Anti-aliasing module 2 adopts frequency overlapped-resistable filter, carries out anti-aliasing filter for the 6 tunnel conditioned signal that signal condition module 1 is exported, thereby effectively reduces high-frequency signal to fold into low-frequency range and the aliasing error that causes.Signal access analog-to-digital conversion module 3 after anti-aliasing filter.

Fig. 3 is anti-aliasing module diagram.As shown in Figure 3, in the present embodiment, anti-aliasing module 2 adopts the linear phase low-pass filter of the quadravalence Sallen-Key circuit topology of unity gain, and this wave filter major parameter index is: cutoff frequency 1Khz, ripple <0.01dB in band.

Analog-to-digital conversion module 3, under the synchronous triggering clock and logic control signal control exported in control module 5, is sampled to anti-aliasing filtered 6 tunnel isolation sampled signals, by the image data input control module 5 of three-phase voltage and three-phase current.

Fig. 4 is analog-to-digital conversion module schematic diagram.As shown in Figure 4, in the present embodiment, analog-to-digital conversion module 3 adopts ADI company specially for power circuit detects and the modulus conversion chip AD7606 that protects domain design, supports 6 tunnel synchronous true pole 5V simulating signals inputs; Input buffer analog input impedance 1M Europe; 16, sampling rate 4.8KSps.Control module 5 before analog to digital conversion, sends reset signal to analog-to-digital conversion module 3 and resets carrying out at every turn, and within the whole analog to digital conversion cycle, control module 5 sends the chip selection signal of low level (effectively) always to analog-to-digital conversion module 3.Analog-to-digital conversion module 3 is set to busy status signal high level (invalid) in the time carrying out analog to digital conversion, after converting, busy status signal is set to low level (invalid), but now reading out data at once, after the pending datas such as palpus are thoroughly set up and are stablized in analog-to-digital conversion module 3, data output signal is set to high level (effectively) by analog-to-digital conversion module 3, now control module 5 can be from analog-to-digital conversion module 3 reading out data.In the time that analog-to-digital conversion module 3 carries out analog to digital conversion, its synchronous triggering signal is provided by control module 5, and the synchronous triggering signal frequency adopting in the present embodiment is 4800Hz.

Synchronizing signal source module 4 sends to control module 5 for generation of synchronous clock source signal.The present embodiment comprises GPS synchronization module 41 and IRIG-B code synchronization module 42.The synchronizing clock signals that GPS synchronization module 41 is exported is GPZDA text, comprises that GPS_RXD(serial ports receives signal) signal, PPS(pps pulse per second signal) signal.IRIG-B code synchronization module 42 receives exterior I RIG-B coded signal and is converted into analog electrical signal, and re-quantization obtains the IRIG-B code synchronizing signal of Transistor-Transistor Logic level signal form.GPS synchronization module 41 is as main synchronization module, IRIG-B code synchronization module 42 is as assist in synchronization module, choice for use as required, in the situation that substation field conveniently sets up gps antenna using GPS pulse per second (PPS) and rs 232 serial interface signal as benchmark synchronous clock source, if substation field is not easy to set up gps antenna, using IRIG-B coded signal as benchmark synchronous clock source.

Control module 5, for generating synchronous triggering signal according to synchronous clock source signal, generates and gathers control signal, thereby send to together analog-to-digital conversion module 3 to control data acquisition, receives image data and is transmitted to host computer 6.Control module 5 in the present embodiment is based on FPGA(Field-Programmable Gate Array, i.e. field programmable gate array) realize.Fig. 5 is control module schematic diagram, as shown in Figure 5, control module 5 comprises synchronous clock source signal processing module 51, synchronisation source signal generation module 52, local clock module 53, synchronous triggering signal generation module 54, top layer top control module 55, analog to digital conversion steering logic module 56, data cache module 57, data upload module 58.

Synchronous clock source signal processing module 51, for receiving the synchronous clock source signal of synchronizing signal source module 4, therefrom extracts pulse per second (PPS) and temporal information.In the present embodiment, corresponding with synchronizing signal source module 4, the synchronous clock source signal processing module 51 of control module 5 comprises that two module: GPS resolve and pretreatment module 511 and IRIG-B decoder module 512.GPS resolves and the major function of pretreatment module 511 is to resolve from the GPZDA text of GPS synchronization module 41 to provide PPS signal (pulse per second (PPS)) and UTC(universal time for synchronisation source signal generation module 52) temporal information.The major function of IRIG-B decoder module 512 is to resolve the IRIG-B code text that receives quantization modules from optical fiber to provide pulse per second (PPS) and temporal information for synchronisation source signal generation module 52.

Synchronisation source signal generation module 52, for according to temporal information and pulse per second (PPS) rise time stamp and second synchronizing signal, sends to local clock module 53.

Local clock module 53, for local clock being revised according to timestamp and a second synchronizing signal, generates a second signal and exports synchronous triggering signal generation module 54 to.In the present embodiment, local clock module 53 is based on building based on 10MHz constant-temperature crystal oscillator, the frequency stability of constant-temperature crystal oscillator be 10 grades (

5.0 × e ^-10), can guarantee the precision of well keeping time.The correction of local clock module 53 is by real time synchronisation source signal generation module 52 timestamps and a second synchronizing signal being compared with local clock, when the two deviation is greater than level and smooth thresholding, local clock module 53 just adopts level and smooth correction algorithm to carry out level and smooth set correction to local clock.

Thereby the second signal that synchronous triggering signal generation module 54 is exported local clock module 53 carries out frequency multiplication generates the 4800Hz synchronous triggering signal that is synchronized with temporal information, input top layer top control module 55.

Top layer top control module 55 is for generated data acquisition instructions, and sends to analog to digital conversion steering logic module 56 together with the same trigger pip receiving.Conventionally adopt setting data collection period to carry out timing distributing data acquisition instructions.Top layer top control module 55 receives the image data that analog to digital conversion steering logic module 56 forwards and sends into data cache module 57 and store, in the time that data transmission condition meets, top layer top control module 55 takes out image data and sends to host computer 6 by data upload module 58 from data cache module 57.

Analog to digital conversion steering logic module 56 for sending and gather control signal to analog-to-digital conversion module 3 in the time receiving data acquisition instruction, and the image data that reads three-phase voltage and three-phase current after data acquisition completes is sent to top layer top control module 55, detailed process is: in the time receiving data acquisition instruction, send reset signal to analog-to-digital conversion module 3, and send effective chip selection signal and synchronous triggering signal to analog-to-digital conversion module 3 within the whole analog to digital conversion cycle, busy status signal and the data output signal of monitoring analog-to-digital conversion module 3, when the image data that busy status signal lost efficacy and data output signal reads three-phase voltage and three-phase current when effective is sent to top layer top control module 55.

Data cache module 57 is for the image data of buffer memory three-phase voltage and three-phase current.In the present embodiment, to adopt the degree of depth be 4Kbit FIFO(First Input First Output, First Input First Output) storer is as data cache module 57.Data transmission condition is FIFO storer and reaches half-full state.

Data upload module 58 is for being transmitted to host computer 6 by the image data of three-phase voltage and three-phase current.In the present embodiment, data upload module 58 adopts pci bus technology to carry out data transmission.

Host computer 6, for receiving the image data of three-phase voltage and three-phase current, carries out load parameter identification according to image data, by the load parameter identification result storage obtaining and query interface is provided.The concrete grammar of load parameter identification is:

The image data of the three-phase voltage once collecting and three-phase current is carried out to segmentation as required, adopt fast fourier transform from extracting corresponding voltage or current amplitude to every one piece of data successively, phase place and work frequency, and adopt correction algorithm according to the last period data amplitude and amplitude and the phase place of phase place to this segment data revise, correction formula adopts as the new algorithm that can suppress adaptively humorous wave interference being proposed in " the electric system phasor based on DFT and power measurement new algorithm " literary composition in the 29th the 2nd phase of volume " Automation of Electric Systems " in 2005.

Revised three-phase voltage u _a, u _b, u _cwith three-phase current I _a, I _b, I _cadopt respectively Park Transformation to obtain two phase voltage u under rotating coordinate system _d, u _qwith biphase current I _d, I _q, transformation for mula is:

$\left[\begin{array}{c}{u}_{\mathrm{\&alpha;}}\\ u_{\mathrm{\&beta;}}\end{array}\right]=\left[\begin{array}{ccc}1& -\frac{1}{2}& -\frac{1}{2}\\ 0& \frac{\sqrt{3}}{2}& -\frac{\sqrt{3}}{2}\end{array}\right]\left[\begin{array}{c}{u}_a\\ u_b\\ u_c\end{array}\right]$

$\left[\begin{array}{c}{u}_d\\ u_q\end{array}\right]=\left[\begin{array}{cc}\cos \mathrm{\&theta;}& \sin \mathrm{\&theta;}\\ -\sin & \cos \mathrm{\&theta;}\end{array}\right]\left[\begin{array}{c}{u}_{\mathrm{\&alpha;}}\\ u_{\mathrm{\&beta;}}\end{array}\right]$

$\left[\begin{array}{c}{i}_{\mathrm{\&alpha;}}\\ i_{\mathrm{\&beta;}}\end{array}\right]=\left[\begin{array}{ccc}1& -\frac{1}{2}& -\frac{1}{2}\\ 0& \frac{\sqrt{3}}{2}& -\frac{\sqrt{3}}{2}\end{array}\right]\left[\begin{array}{c}{i}_a\\ i_b\\ i_c\end{array}\right]$

$\left[\begin{array}{c}{i}_d\\ i_q\end{array}\right]=\left[\begin{array}{cc}\cos \mathrm{\&theta;}& \sin \mathrm{\&theta;}\\ -\sin \mathrm{\&theta;}& \cos \mathrm{\&theta;}\end{array}\right]\left[\begin{array}{c}{i}_{\mathrm{\&alpha;}}\\ i_{\mathrm{\&beta;}}\end{array}\right]$

Wherein, θ represents the phase angle of a phase voltage or electric current.

According to two phase voltage u _d, u _qand electric current I _d, I _qcalculate respectively dynamic active power P with work frequency _d, dynamic reactive power Q _d, static active-power P _s, static reactive power Q _s, computing formula is:

P _d＝u _dI _d+u _qI _q

Q _d＝u _qI _d+u _dI _q

$P_s=P_0[A_P{\left(\frac{U}{U_0}\right)}^2+B_P\left(\frac{U}{U_0}\right)+C_P](1+K_{\mathrm{PF}}\mathrm{\&Delta;f})$

$Q_s=Q_0[A_Q{\left(\frac{U}{U_0}\right)}^2+B_Q\left(\frac{U}{U_0}\right)+C_Q](1+K_{\mathrm{QF}}\mathrm{\&Delta;f})$

Wherein, Δ f is frequency departure, K _pFand K _qFrepresent respectively the frequency characteristic index of active power and reactive power.P ₀, Q ₀, U ₀active power, reactive power, busbar voltage that while representing steady-state operation respectively, static load consumes.Wherein A _p, B _p, C _prepresent active voltage parameter.A _q, B _q, C _qrepresent reactive voltage parameter.And meet following equation of constraint: A _p+ B _p+ C _p=1, A _q+ B _q+ C _q=1.

Select as required load model, by work frequency, busbar voltage, as mode input, by the dynamic active power P calculating _d, dynamic reactive power Q _d, static active-power P _s, static reactive power Q _sas output, the parameter in load model is carried out to identification.

The load model using in the present invention has three kinds:

The first becomes Adaptive synthesis load model while being, dynamic part adopts 3 rank electromechanical transient models, consider to suffer in the transient state process of disturbance at power distribution network, the voltage of each load point and frequency all can change, and under two cordic phase rotators, calculate and are subject to power distribution network frequency jitter to affect the transient potential e of larger induction-motor load model _d, e _qwith revolutional slip ω, state equation is:

$\left\{\begin{array}{c}\frac{\mathrm{d\&omega;}}{\mathrm{dt}}=-\frac{1}{2H}[({\mathrm{A\&omega;}}^2+{\mathrm{B\&omega;}}^2+C)T_0-(e_d{I}_d+e_q{I}_q)]\\ \frac{{\mathrm{de}}_q}{\mathrm{dt}}=-\frac{1}{T}[e_q-(x-x^{\&prime;})I_d]+(\mathrm{\&omega;}-1)e_d\\ \frac{{\mathrm{de}}_d}{\mathrm{dt}}=-\frac{1}{T}[e_d-(x-x^{\&prime;})I_q]+(\mathrm{\&omega;}-1)e_q\end{array}\right.$

Dynamic part output equation: T ₀

$\left\{\begin{array}{c}{I}_d=\frac{1}{{\mathrm{<figure-callout\; id="2"\; label="R\; s"\; filenames="HDA0000473351960000011.png"\; state="\{\{state\}\}">R</figure-callout>}}_s^{}+x^{\&prime;2}}[R_s(u_d-e_d)+x^{\&prime;}(u_q-e_q)]\\ I_q=\frac{1}{{\mathrm{<figure-callout\; id="2"\; label="R\; s"\; filenames="HDA0000473351960000011.png"\; state="\{\{state\}\}">R</figure-callout>}}_s^{}+x^{\&prime;2}}[R_s(u_q-e_q)-x^{\&prime;}(u_d-e_d)]\end{array}\right.$

In formula, H is inertia constant, is nominal torque, T=(x_r+x_m)/R_r, x=x_s+x_m, x '=x_s+ (x_mx_r)/(x_m+x_r), need the parameter of identification to have R _s: stator resistance, x_s: stator winding leakage reactance, x_m: excitation reactance, R_r: rotor resistance, x_r: rotor leakage reactance, A, B, C are electromechanics torque characteristics parameter, meet A+B+C=1 condition.Above-mentioned parameter is all the perunit value under induction motor base value.

$K_{\mathrm{pm}}=P_0^{\&prime;}/P_0$

$M_{\mathrm{lf}}=(P_0^{\&prime;}/S)/(U/U_{\mathrm{Base}})$

Wherein

for the initial active power of motor, P ₀for the initial active power of loading in power distribution network.K _pmrepresent initial active power scale-up factor, M _lffor initial load rate coefficient, S is motor rated capacity, and U is the voltage on the bus of load bus place, U _basefor base value voltage.

Static part adopts constant-impedance model in parallel, continuous current model, and permanent power module, is shown below:

$\frac{P}{P_0}=K_{\mathrm{PZ}}{\left(\frac{U}{U_0}\right)}^2+K_{\mathrm{PI}}\left(\frac{U}{U_0}\right)+K_{\mathrm{PP}}$

$\frac{Q}{Q_0}=K_{\mathrm{QZ}}{\left(\frac{U}{U_0}\right)}^2+K_{\mathrm{QI}}\left(\frac{U}{U_0}\right)+K_{\mathrm{QP}}$

In calculated load, being subject to the less constant impedance model of power distribution network medium frequency influence of fluctuations to need the static characteristics parameter of identification is K _pZ, K _pI, K _qZ, K _qImeet:

$\left\{\begin{array}{c}{K}_{\mathrm{PZ}}+K_{\mathrm{PI}}+K_{\mathrm{PP}}=1\\ K_{\mathrm{QZ}}+K_{\mathrm{QI}}+K_{\mathrm{QP}}=1\end{array}\right.$

The second is power back-off model, by the variation of d-q component in busbar voltage U to meritorious idle impact analysis, obtain dynamically meritorious, the reactive-load compensation link of load model:

$\left\{\begin{array}{c}\mathrm{\&Delta;P}=k_p*({\mathrm{\&Delta;U}}_d*I_d+{\mathrm{\&Delta;U}}_q*I_q)\\ \mathrm{\&Delta;Q}=k_q*({\mathrm{\&Delta;U}}_q*I_d-{\mathrm{\&Delta;U}}_d*I_q)\end{array}\right.$

Wherein: Δ P is meritorious compensation; Δ Q is reactive-load compensation.Δ U _dfor voltage U _dvariable quantity, Δ U _qfor voltage U _qvariable quantity.In voltage dynamic change, Δ U _dwith Δ U _qthere is significant change, make Δ P and Δ Q can play dynamic compensation effect, improve the dynamic property of load model.

The third is impact load model, impact load mainly concentrates on high energy-consuming enterprises, its capacity is large, the impact that electrical network is caused is also large, and impact load model is defined as: can describe the active power of load absorption and reactive power along with busbar voltage and frequency and self the power demand of loading change and the relational expression that changes.Its load model structure is as follows:

$T_p\frac{{\mathrm{dP}}_r}{\mathrm{dt}}+P_r=\frac{U^2\mathrm{<figure-callout\; id="2"\; label="R\; R"\; filenames="HDA0000473351960000011.png"\; state="\{\{state\}\}">R</figure-callout>}}{R^{}}-P_0{\left(\frac{U}{U_0}\right)}^{\mathrm{\&alpha;}}$

$T_q\frac{{\mathrm{dQ}}_r}{\mathrm{dt}}+Q_r=\frac{U^2\mathrm{<figure-callout\; id="2"\; label="R\; R"\; filenames="HDA0000473351960000011.png"\; state="\{\{state\}\}">R</figure-callout>}}{R^{}}-Q_0{\left(\frac{U}{U_0}\right)}^{\mathrm{\&beta;}}$

T _pand T _qrepresent respectively the time constant of meritorious and reactive requirement; P _r, P ₀represent respectively the meritorious demand of load and load stable state active power, Q _r, Q ₀be expressed as reactive load demand and load stable state reactive power, α, meritorious and without work index when β is respectively stable state.It is T that impact load module needs the parameter of identification _p, T _q, α and β.

The parameter identification of load model can adopt several data fitting technique to realize, and what in the present embodiment, adopt is particle cluster algorithm.

Host computer 6 in this locality, is waited for the data query instruction at electrical network center by parameter identification result store, in the time receiving data query instruction, encapsulates, transfers to electrical network center after the processing such as compression by parameter identification result.

Fig. 6 is the application schematic diagram of substation bus bar load characteristic test record device of the present invention.As shown in Figure 6, apparatus of the present invention input end is connected with bus secondary cable, output terminal access power private network.Each substation bus bar load characteristic test record device gathers after corresponding substation bus bar data, carries out, after load parameter identification, according to the instruction at electrical network center, load parameter identification result being uploaded in this locality.In Fig. 6, synchronizing signal is to obtain by gps signal, and is distributed to each substation bus bar load characteristic test record device by the fiber optic network of transformer station.

Although above the illustrative embodiment of the present invention is described; so that those skilled in the art understand the present invention; but should be clear; the invention is not restricted to the scope of embodiment; to those skilled in the art; as long as various variations appended claim limit and definite the spirit and scope of the present invention in, these variations are apparent, all utilize innovation and creation that the present invention conceives all at the row of protection.

Claims (7)

1. a substation bus bar load characteristic test record device, is characterized in that, comprises signal condition module, anti-aliasing module, analog-to-digital conversion module, synchronizing signal source module, control module, upper computer module, wherein:

Signal condition module is for gathering three-phase voltage and the three-phase current signal of substation bus bar secondary cable under full operating mode, amount to 6 tunnel simulating signals, and be adjusted in the collectable voltage range of device analog-to-digital conversion module the 6 tunnel conditioned signal access anti-aliasing filter modules that obtain by the no-load voltage ratio Jiang Mei road signal designing;

Anti-aliasing filter module is for carrying out anti-aliasing filter to 6 tunnel conditioned signal of signal condition module output;

Analog-to-digital conversion module, under synchronous triggering clock and logic control signal control in control module output, is sampled to anti-aliasing filtered 6 road signals, by the image data input control module of three-phase voltage and three-phase current;

Synchronizing signal source module sends to control module for generation of synchronous clock source signal;

Central Control Module, for generating synchronous triggering signal according to synchronous clock source signal, generates collection control signal and sends to together analog-to-digital conversion module, receives image data and is also transmitted to host computer;

Host computer is for receiving the image data of three-phase voltage and three-phase current, and select as required load model to carry out load parameter identification, by the load parameter identification result storage obtaining, start or stop and upload load parameter identification result according to the instruction at electrical network center.

2. substation bus bar load characteristic test record device according to claim 1, it is characterized in that, described signal condition module comprises voltage transformer (VT), current transformer, differential amplifier input stage, intergrade amplifier, voltage follower, wherein: voltage transformer (VT) is used for gathering three-phase voltage signal, current transformer is used for gathering three-phase current signal, voltage transformer (VT) summation current transformer amplifies differential amplifier input stage corresponding to signal input collecting respectively, send into again intergrade amplifier and offset differential amplifier input stage noise and power supply ripple, send into again voltage follower and obtain final conditioned signal, the input end of voltage follower adopts clamper resist technology, make the conditioned signal of signal output be no more than the maximum input range of analog-to-digital conversion module.

3. substation bus bar load record device according to claim 1, is characterized in that, described anti-aliasing filter module adopts the linear phase low-pass filter of the quadravalence Sallen-Key circuit topology of unity gain.

4. substation bus bar load characteristic test record device according to claim 1, is characterized in that, described synchronizing signal source module is GPS module or IRIG-B code synchronization module.

5. substation bus bar load characteristic test record device according to claim 1, it is characterized in that, described control module comprises synchronous clock source signal processing module, synchronisation source signal generation module, local clock module, synchronous triggering signal generation module, top layer top control module, analog to digital conversion steering logic module, data cache module, data upload module, wherein:

Synchronous clock source signal processing module, for receiving the synchronous clock source signal of synchronizing signal source module, therefrom extracts pulse per second (PPS) and temporal information, sends to synchronisation source signal generation module;

Synchronisation source signal generation module, for according to temporal information and pulse per second (PPS) rise time stamp and second synchronizing signal, sends to local clock module;

Local clock module, for local clock being revised according to timestamp and a second synchronizing signal, generates a second signal and exports synchronous triggering signal generation module to;

Thereby synchronous triggering signal generation module generates for the second signal of local clock module output is carried out to frequency multiplication the synchronous triggering signal that is synchronized with temporal information, sends to top layer top control module;

Top layer top control module is used for generated data acquisition instructions, and sends to analog to digital conversion steering logic module together with the same trigger pip receiving; Receive the image data of analog to digital conversion steering logic module forwards and send into data cache module storage, in the time that data transmission condition meets, top layer top control module takes out image data and sends to host computer by data upload module from data cache module;

Analog to digital conversion steering logic module is for sending and gather control signal to analog-to-digital conversion module in the time receiving data acquisition instruction, and the image data that reads three-phase voltage and three-phase current after data acquisition completes is sent to top layer top control module;

Data cache module is for the image data of buffer memory three-phase voltage and three-phase current;

Data upload module is for being transmitted to host computer by the image data of three-phase voltage and three-phase current.

6. substation bus bar load characteristic test record device according to claim 1, is characterized in that, the concrete grammar of described load parameter identification is:

S1: the image data of the three-phase voltage once collecting and three-phase current is carried out to segmentation as required, adopt fast fourier transform from extracting corresponding voltage or current amplitude, phase place and work frequency to every one piece of data successively, and adopt correction algorithm according to the last period data amplitude and amplitude and the phase place of phase place to this segment data revise;

S2: revised three-phase voltage u _a, u _b, u _cwith three-phase current I _a, I _b, I _cadopt respectively Park Transformation to obtain two phase voltage u under rotating coordinate system _d, u _qwith biphase current I _d, I _q;

S3: the two phase voltage u that obtain according to the work frequency obtaining in step 1 and step 2 _d, u _qand electric current I _d, I _qcalculate respectively dynamic active power P _d, dynamic reactive power Q _d, static active-power P _s, static reactive power Q _s;

S4: select load model, using work frequency, two phase voltages and biphase current as mode input, by the dynamic active power P calculating _d, dynamic reactive power Q _d, static active-power P _s, static reactive power Q _sas output, the parameter in load model is carried out to identification.

7. substation bus bar load characteristic test record device according to claim 1, is characterized in that, adopts particle cluster algorithm to carry out parameter identification in described step S4.

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