CN103872905A - Power supply control device - Google Patents
Power supply control device Download PDFInfo
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- CN103872905A CN103872905A CN201210542241.XA CN201210542241A CN103872905A CN 103872905 A CN103872905 A CN 103872905A CN 201210542241 A CN201210542241 A CN 201210542241A CN 103872905 A CN103872905 A CN 103872905A
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- circuit
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- voltage
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- reduction voltage
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Abstract
The invention relates to a power supply control device, comprising a voltage reduction circuit, a power supply unit, a peak value detecting circuit and a buffer circuit, wherein the power supply unit is used for supplying direct current to the voltage reduction circuit; the peak value detecting circuit is used for detecting a load voltage of the voltage reduction circuit; and the buffer circuit is connected to the voltage reduction circuit, so as to prevent the voltage reduction circuit from damage in an overload power supply state. The power supply control device also comprises a logic circuit connected to the peak value detecting circuit and the buffer circuit, wherein the buffer circuit is selectively connected to the voltage reduction circuit through the logic circuit; the logic circuit determines whether the voltage reduction circuit is in the overload state or not according to the load voltage detected by the peak value detecting circuit and connects the buffer circuit to the voltage reduction circuit when the voltage reduction circuit is in the overload state and accordingly, disconnects the buffer circuit from the voltage reduction circuit when the voltage reduction circuit is in a light load state.
Description
Technical field
The present invention relates to a kind of power supply control apparatus, relate in particular to a kind of power supply control apparatus with buffer circuit.
Background technology
The current power supply control apparatus such as notebook computer, server generally includes power-supply unit (Power supply unit, and reduction voltage circuit PSU), described PSU is in order to being converted to direct current from the alternating current of external world's access, described reduction voltage circuit, in order to by extremely default magnitude of voltage of the galvanic lower voltage of PSU conversion, is supplied to the receiving ends such as server system.Existing reduction voltage circuit generally includes pulse width modulation (Pulse-Width Modulation, PWM) controller such as chip, be serially connected with the first switch between PSU and ground, second switch successively, be connected in parallel to mutually outputting inductance and the storage capacitor of second switch opposite end after serial connection, the receiving ends such as server system are connected in parallel to the opposite end of storage capacitor, and become default voltage to be supplied to receiving end the voltage transitions of PSU output by the first switch described in controller control and second switch successively conducting or disconnection.But, when described power supply control apparatus exports the voltage of load to when higher (this reduction voltage circuit is in heavy condition), switch to the moment of off-state from conducting state at described second switch, voltage on this second switch may increase suddenly because of the effect of the voltage of PSU supply, thereby burns out described second switch.To this, existing operating type is the buffer circuit that serial connection is made up of resistance and electric capacity between second switch and outputting inductance, the too high phenomenon of transient voltage while disconnection to suppress described second switch.But; although above-mentioned buffer circuit can effectively prevent that second switch is burned in heavy duty when (voltage of output is higher) at power supply control apparatus; but this buffer circuit, can leave unused and increases the power loss of this power supply control apparatus under light condition and without protection when second switch at power supply control apparatus.
Summary of the invention
In view of above content, be necessary to provide a kind of power supply control apparatus, in order to receiving end is powered, this power supply control apparatus comprises reduction voltage circuit, power-supply unit and buffer circuit, described power-supply unit is in order to supply direct current to described reduction voltage circuit, this reduction voltage circuit becomes a default voltage to be supplied to receiving end described galvanic voltage transitions, and described buffer circuit is connected to reduction voltage circuit, impaired when preventing that described reduction voltage circuit from working under heavily loaded power supply state.
This power supply control apparatus also comprises peak sensing circuit and logical circuit, described peak sensing circuit is in order to detect the load voltage of reduction voltage circuit, described logical circuit one end is connected to peak sensing circuit and the other end is connected to buffer circuit, described buffer circuit is connected with reduction voltage circuit, described logical circuit judges that according to the load voltage of peak sensing electric circuit inspection whether reduction voltage circuit is in heavy condition, in the time judging reduction voltage circuit in heavy condition, described logical circuit control buffer circuit is in running order and this buffer circuit is protected reduction voltage circuit; In the time judging reduction voltage circuit in light condition, described logical circuit control buffer circuit is in off position.
Described power supply control apparatus may be impaired time, controlled described buffer circuit and is connected to reduction voltage circuit, effectively to protect this reduction voltage circuit in heavy condition in described reduction voltage circuit; And can not damage and provide when protection without buffer circuit in light condition when reduction voltage circuit; described power supply control apparatus disconnects being connected of described buffer circuit and reduction voltage circuit; the power loss producing to eliminate this buffer circuit, makes the power supplying efficiency of this power supply control apparatus higher.
Accompanying drawing explanation
Fig. 1 is the circuit theory diagrams of power supply control apparatus of the present invention to receiving end power supply.
Fig. 2 is the circuit theory diagrams of the peak sensing circuit of the power supply control apparatus of Fig. 1.
Main element symbol description
| Power |
100 |
| |
10 |
| |
11 |
| Power- |
12 |
| |
13 |
| The first switch | Q1 |
| Second switch | Q2 |
| Outputting inductance | L |
| Storage capacitor | C1 |
| Peak |
30 |
| |
31 |
| |
32 |
| |
33 |
| |
50 |
| Resistance | R |
| Buffer capacitor | C2 |
| |
70 |
| |
71 |
| |
73 |
| Receiving |
200 |
| |
301 |
| |
302 |
| |
701 |
| The |
702 |
| |
703 |
| Controlled |
731 |
| The |
732 |
| The |
733 |
Following embodiment further illustrates the present invention in connection with above-mentioned accompanying drawing.
Embodiment
Below in conjunction with accompanying drawing and preferred embodiments, the present invention is described in further detail:
See also Fig. 1 and Fig. 2, power supply control apparatus 100 of the present invention is in order to power to the receiving ends such as server system 200.This power supply control apparatus 100 comprises power-supply unit 12, reduction voltage circuit 10, peak sensing circuit 30, buffer circuit 50 and logical circuit 70.Described power-supply unit provides supply voltage Vin to reduction voltage circuit 10.Described reduction voltage circuit 10 provides stable operating voltage to receiving end 200 by this controller 11, and this operating voltage is the required voltage of the normal work of receiving end 200.Described peak sensing circuit 30 is connected to reduction voltage circuit 10 and logical circuit 70.Described peak sensing circuit 30 is in order to the load voltage Vx of detecting real-time reduction voltage circuit 10, and this load voltage Vx is the voltage that reduction voltage circuit 10 offers receiving end 200 loads.Described load voltage Vx follows the variation of receiving end 200 loads and changes.Described buffer circuit 50 is connected with described reduction voltage circuit 10.Described logical circuit 70 is also connected to buffer circuit 50, in order to the load voltage Vx that detects according to peak sensing circuit 30 and the default reference voltage value of logical circuit 70 compare and according to buffer circuit 50 described in comparative result output control in work or off position.
When this peak sensing circuit 30 detects load voltage Vx that reduction voltage circuit 10 exports when higher, this logical circuit 70 judges that described reduction voltage circuit 10, in heavy condition, controls described buffer circuit 50 in running order, to protect this reduction voltage circuit 10; When this peak sensing circuit 30 detects load voltage Vx that reduction voltage circuit 10 exports hour; this logical circuit 70 judges described reduction voltage circuit 10 under light condition and during without this reduction voltage circuit 10 of protection; control described buffer circuit 50 in off position, eliminate the power loss that this buffer circuit 50 produces.
Described reduction voltage circuit 10 comprises controller 11, the first switch Q1, second switch Q2, outputting inductance L and storage capacitor C1.Described controller 11 is connected to the first switch Q1 and second switch Q2, controls successively described the first switch Q1 and second switch Q2 conducting or disconnection in order to the magnitude of voltage that exports receiving end 200 according to this reduction voltage circuit 10 to.In embodiment of the present invention, described controller 11 is a pulse width modulation chip, and recently regulate the conducting duration of described the first switch Q1 and second switch Q2, the size of the magnitude of voltage that this reduction voltage circuit 10 of corresponding adjusting is exported by the duty that adjusting is sent to the pulse width modulating signal of the first switch Q1 and second switch Q2.
Described the first switch Q1 and second switch Q2 are serially connected with between power-supply unit and ground successively, produce the load voltage end 13 of described load voltage Vx between the first switch Q1 and second switch Q2, after described outputting inductance L and storage capacitor C1 contact mutually, the other end of storage capacitor C1 is connected between the first switch Q1 and second switch Q2, the other end ground connection of outputting inductance L.Described receiving end 200 is connected in parallel to the opposite end of storage capacitor C1.So, in the time of described controller 11 conducting the first switch Q1, disconnection second switch Q2, the electric energy that the output Vin of power-supply unit 12 provides will be supplied to receiving end 200 and storage capacitor C1 from the first switch Q1, outputting inductance L, to pass through storage capacitor C1 storage of electrical energy in the time that receiving end 200 is powered; In the time that described controller 11 disconnects the first switch Q1, power-supply unit stops this reduction voltage circuit 10 to power, and the energy that is discharged its storage by storage capacitor C1 is powered to receiving end 200.In embodiment of the present invention, described the first switch Q1 and second switch Q2 are a field effect transistor, and the grid of described the first switch Q1 is connected to controller 11, and drain electrode is connected with power-supply unit 12, and source electrode is connected to the drain electrode of second switch Q2.The grid of described second switch Q2 is connected to controller 11, source ground.
The connected node of the drain electrode of the source electrode of described the first switch Q1 and second switch Q2 has formed the load voltage end 13 of this reduction voltage circuit 10, and the voltage of this load voltage end 13 is this load voltage Vx.And due to the cut-off of this first switch Q1 alternate conduction, making the voltage transitions that power-supply unit 12 is exported is pulse-width signal as shown in Figure 2.
Described peak sensing circuit 30 includes sense terminal 301 and output 302, and this sense terminal 301 is connected to the load voltage end 13 of reduction voltage circuit 10, for detecting this load voltage Vx.This output 302 is connected to logical circuit 70.Described peak sensing circuit 30 is regular voltage-sawtooth Vout in order to the irregular waveform voltage transitions that sense terminal 301 is detected and exports by output 302.In the present embodiment, the difference of the peak value of this voltage-sawtooth Vout is very little, is equivalent to a constant voltage.; described peak sensing circuit 30 is direct voltage by the voltage transitions of detecting; the size of the sawtooth voltage Vout that described in this, peak sensing circuit 30 is changed is directly proportional to the peak value of this load voltage Vx, thereby in the time that the peak value of load voltage Vx becomes large, this sawtooth voltage Vout also increases.It is in heavy condition or light condition that the sawtooth voltage Vout of what described logical circuit 70 was exported peak sensing circuit 30 be similar to direct voltage and a reference voltage V ref relatively detect described reduction voltage circuit 10.
As shown in Figure 2, described peak sensing circuit 30 comprises a follower 31, an amplifier 32 and a RC circuit 33.Described RC circuit 33 is composed in parallel by resistance R a and capacitor C a, is an integrating circuit.The load voltage Vx that described follower 31 is followed the square wave form of the reduction voltage circuit 10 that peak sensing circuit 30 detects, exports this sawtooth voltage Vout that is similar to direct voltage to logical circuit 70 by RC circuit 33 integrations.
As shown in Figure 1, described logical circuit 70 comprises comparator 71 and logic switch 73.Described comparator 71 comprises first input end 701, the second input 702 and output 703.Described logic switch 73 comprises controlled end 731, the first conduction terminal 732 and the second conduction terminal 733.Output 302, the second inputs 702 that the first input end 701 of this comparator 71 is electrically connected to peak sensing circuit 30 are electrically connected to reference voltage V ref, and output 703 is connected to the controlled end 731 of logic switch 73.The first conduction terminal 732 of described logic switch 73 is connected to buffer capacitor C2, the second conduction terminal 733 ground connection.
Described buffer circuit 50 comprises a resistance R and a buffer capacitor C2, and described resistance R and buffer capacitor C2 are series between second switch Q2 and outputting inductance L, and the other end is by logical circuit 70 ground connection.
Voltage and this reference voltage V ref that described comparator 71 is relatively exported at peak sensing circuit 30; when this comparator 71 voltage that relatively this peak sensing circuit 30 is exported is greater than this reference voltage V ref; control this logic switch 73 conductings, thereby the current branch conducting at buffer circuit 50 places is made buffer circuit 50 in running order and protect this reduction voltage circuit 10.When this comparator 71 voltage that relatively this peak sensing circuit 30 is exported is less than this reference voltage V ref, control logic switch 73 ends, thereby makes buffer circuit in off position the current branch at buffer circuit 50 places, thereby has avoided power loss.
In the present embodiment, the first input end 701 of this comparator 71 is normal phase input end, and the second input 702 is inverting input, and this logic switch 73 is a high level actuating switch, is specially a NMOS pipe.When this comparator 71 voltage that relatively this peak sensing circuit 30 is exported is greater than this reference voltage V ref, export high level signal and control this logic switch 73 conductings, output low level signal when the voltage that relatively this peak sensing circuit 30 is exported is less than this reference voltage Vref and control this logic switch 73 and end.
Thereby, in the time that this logical circuit 70 detects described reduction voltage circuit 10 in heavy condition, buffer circuit 50 place branch road conductings and in running order; In the time that this logical circuit 70 detects described reduction voltage circuit 10 in light condition, buffer circuit 50 place branch roads disconnect and in off position.In embodiment of the present invention, the reference voltage V ref that described comparator 71 connects for presetting, for example, provides by this power-supply unit 12 in advance.If described reduction voltage circuit 10 is in heavy condition, the magnitude of voltage that this peak sensing circuit 30 exports logical circuit 70 to exceeds default reference voltage V ref, and comparator 71 magnitude of voltage that relatively this peak sensing circuit 30 is exported is greater than this reference voltage V ref.If described reduction voltage circuit 10 is in light condition, the magnitude of voltage that peak sensing circuit 30 exports logical circuit 70 to is lower than default reference voltage V ref, and comparator 71 magnitude of voltage that relatively this peak sensing circuit 30 is exported is less than this reference voltage.
Therefore, power supply control apparatus 100 of the present invention is in described reduction voltage circuit 10 during in heavy condition, control described buffer circuit 50 in running order, excessive and be burned to prevent that second switch Q2 from switching to the transient voltage of off-state by conducting, effectively protect this reduction voltage circuit 10; This reduction voltage circuit 10 is in the time of light condition; second switch Q2 can be when just not disconnecting voltage excessive and impaired and while providing protection without buffer circuit 50; described power supply control apparatus 100 is controlled described buffer circuit 50 in off position; eliminate the power loss that this buffer circuit 50 produces, make the power supplying efficiency of this power supply control apparatus 100 higher.
To those skilled in the art, can make other corresponding changes or adjustment in conjunction with the actual needs of producing according to scheme of the invention of the present invention and inventive concept, and these changes and adjustment all should belong to the protection range of the claims in the present invention.
Claims (10)
1. a power supply control apparatus, in order to receiving end is powered, this power supply control apparatus comprises reduction voltage circuit, power-supply unit and buffer circuit, described power-supply unit is in order to supply direct current to described reduction voltage circuit, this reduction voltage circuit becomes a default voltage to be supplied to receiving end described galvanic voltage transitions, described buffer circuit is connected to reduction voltage circuit, impaired when preventing that described reduction voltage circuit from working under heavily loaded power supply state, it is characterized in that:
This power supply control apparatus also comprises peak sensing circuit and logical circuit, described peak sensing circuit is in order to detect the load voltage of reduction voltage circuit, described logical circuit one end is connected to peak sensing circuit and the other end is connected to buffer circuit, described buffer circuit is connected with reduction voltage circuit, described logical circuit judges that according to the load voltage of peak sensing electric circuit inspection whether reduction voltage circuit is in heavy condition, in the time judging reduction voltage circuit in heavy condition, described logical circuit control buffer circuit is in running order and this buffer circuit is protected reduction voltage circuit; In the time judging reduction voltage circuit in light condition, described logical circuit control buffer circuit is in off position.
2. power supply control apparatus as claimed in claim 1, is characterized in that: described peak sensing circuit is in order to be converted to regular sawtooth voltage by the square-wave voltage of detecting.
3. power supply control apparatus as claimed in claim 2, it is characterized in that: described peak sensing circuit comprises a follower, an amplifier and a RC circuit, described RC circuit is composed in parallel by resistance R and capacitor C, it is an integrating circuit, described follower is followed the load voltage of the reduction voltage circuit of peak sensing circuit detecting, exports sawtooth voltage to logical circuit by RC circuit integration.
4. power supply control apparatus as claimed in claim 1, it is characterized in that: described logical circuit is preset a reference voltage, and whether the load voltage that judges described peak sensing electric circuit inspection reduction voltage circuit exceeds described default reference voltage, if exceeding default reference voltage, the load voltage of described reduction voltage circuit judges that described reduction voltage circuit is in heavy condition, if the load voltage of described reduction voltage circuit judges that lower than default reference voltage described reduction voltage circuit is in light condition.
5. power supply control apparatus as claimed in claim 2, it is characterized in that: described logical circuit is preset a reference voltage, described logical circuit comprises comparator and logic switch, described logical circuit is connected to buffer circuit by logic switch, described comparator is sawtooth voltage and a reference voltage of the output of peak value circuit for detecting relatively, and according to conducting or the disconnection of comparative result control logic switch, correspondingly control described buffer circuit in running order, or control described buffer circuit in off position.
6. power supply control apparatus as claimed in claim 5, it is characterized in that: described comparator comprises first input end, the second input and output, described logic switch comprises controlled end, the first conduction terminal and the second conduction terminal, the first input end of this comparator is electrically connected to the output of peak sensing circuit, the second input is electrically connected to reference voltage, output is connected to the controlled end of logic switch, the first conduction terminal of described logic switch is connected to buffer circuit, the second conduction terminal ground connection.
7. power supply control apparatus as claimed in claim 5, is characterized in that: described buffer circuit comprises a resistance and a buffer capacitor, and described buffer circuit is connected to logic switch by buffer capacitor, and is connected to reduction voltage circuit by resistance.
8. power supply control apparatus as claimed in claim 1, it is characterized in that: described reduction voltage circuit comprises controller, the first switch, second switch, outputting inductance and storage capacitor, described controller is connected to the first switch Q1 and second switch Q2, control successively described the first switch Q1 and second switch Q2 conducting or disconnection in order to export the magnitude of voltage of receiving end to according to this reduction voltage circuit, described the first switch Q1 and second switch Q2 are serially connected with between power-supply unit and ground successively, node between described the first switch Q1 and second switch Q2 forms load voltage end and exports this load voltage, after described outputting inductance and storage capacitor are contacted mutually, the other end of storage capacitor is connected between the first switch Q1 and second switch Q2, the other end ground connection of outputting inductance, described receiving end is connected in parallel to the opposite end of storage capacitor.
9. power supply control apparatus as claimed in claim 8, it is characterized in that: described controller is a pulse width modulation chip, and recently regulate the conducting duration of described the first switch Q1 and second switch Q2, the size of the magnitude of voltage of this reduction voltage circuit output of corresponding adjusting by the duty that adjusting is sent to the pulse width modulating signal of the first switch Q1 and second switch Q2.
10. power supply control apparatus as claimed in claim 8, it is characterized in that: in the time of described controller conducting the first switch Q1, disconnection second switch Q2, the electric energy that the output of power-supply unit provides will be supplied to receiving end and storage capacitor from the first switch Q1, outputting inductance, to pass through storage capacitor storage of electrical energy in the time that receiving end is powered; In the time that described controller disconnects the first switch Q1, power-supply unit stops the power supply of this reduction voltage circuit, and by the energy that storage capacitor C1 discharges its storage, receiving end is powered.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201210542241.XA CN103872905A (en) | 2012-12-14 | 2012-12-14 | Power supply control device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201210542241.XA CN103872905A (en) | 2012-12-14 | 2012-12-14 | Power supply control device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN103872905A true CN103872905A (en) | 2014-06-18 |
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201210542241.XA Pending CN103872905A (en) | 2012-12-14 | 2012-12-14 | Power supply control device |
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Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104201865A (en) * | 2014-08-06 | 2014-12-10 | 青岛歌尔声学科技有限公司 | Electronic system and noise reduction method thereof and voltage switching circuit |
| CN105790551A (en) * | 2016-04-11 | 2016-07-20 | 联想(北京)有限公司 | Voltage-reduced circuit and electronic device |
| CN109873399A (en) * | 2019-04-15 | 2019-06-11 | 苏州浪潮智能科技有限公司 | A kind of power protecting circuit and apparatus for protecting power supply |
| CN111684701A (en) * | 2018-02-07 | 2020-09-18 | 沃思电子埃索斯有限责任两合公司 | Device for obtaining electric energy and energy generator comprising such a device |
| CN112234822A (en) * | 2020-09-16 | 2021-01-15 | 苏州浪潮智能科技有限公司 | Power supply control circuit and method |
| CN112532039A (en) * | 2020-10-30 | 2021-03-19 | 苏州浪潮智能科技有限公司 | Intelligent control method and circuit for reducing electromagnetic radiation of switching power supply |
-
2012
- 2012-12-14 CN CN201210542241.XA patent/CN103872905A/en active Pending
Cited By (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104201865A (en) * | 2014-08-06 | 2014-12-10 | 青岛歌尔声学科技有限公司 | Electronic system and noise reduction method thereof and voltage switching circuit |
| CN104201865B (en) * | 2014-08-06 | 2017-02-15 | 歌尔科技有限公司 | Electronic system and noise reduction method thereof and voltage switching circuit |
| CN105790551A (en) * | 2016-04-11 | 2016-07-20 | 联想(北京)有限公司 | Voltage-reduced circuit and electronic device |
| CN105790551B (en) * | 2016-04-11 | 2019-02-05 | 联想(北京)有限公司 | Reduction voltage circuit and electronic equipment |
| CN111684701A (en) * | 2018-02-07 | 2020-09-18 | 沃思电子埃索斯有限责任两合公司 | Device for obtaining electric energy and energy generator comprising such a device |
| CN109873399A (en) * | 2019-04-15 | 2019-06-11 | 苏州浪潮智能科技有限公司 | A kind of power protecting circuit and apparatus for protecting power supply |
| CN112234822A (en) * | 2020-09-16 | 2021-01-15 | 苏州浪潮智能科技有限公司 | Power supply control circuit and method |
| CN112532039A (en) * | 2020-10-30 | 2021-03-19 | 苏州浪潮智能科技有限公司 | Intelligent control method and circuit for reducing electromagnetic radiation of switching power supply |
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Application publication date: 20140618 |