CN103853220B - A kind of feed circuit, electronic equipment and correlation method - Google Patents
A kind of feed circuit, electronic equipment and correlation method Download PDFInfo
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- CN103853220B CN103853220B CN201210528454.7A CN201210528454A CN103853220B CN 103853220 B CN103853220 B CN 103853220B CN 201210528454 A CN201210528454 A CN 201210528454A CN 103853220 B CN103853220 B CN 103853220B
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Abstract
The present invention relates to a kind of feed circuit, electronic equipment and correlation method.Such as, embodiments of the invention provide a kind of feed circuit, these feed circuit comprise: the first chip, there is the first terminal, second terminal and power managing signal circuit for generating, wherein the operation of power managing signal circuit for generating produces corresponding analog control signal with the logic state according to the digital signal in the common lead be connected to the first terminal, and export analog control signal through the second terminal, wherein common lead is connected with the first terminal of the first chip, and operation is can connect to the corresponding the first terminal of at least one the second chip, and wherein the second chip has or does not have corresponding second terminal, and power management module, there is control terminal and power supply terminal, and operation is to receive analog control signal from control terminal, and controls based on the output voltage of analog control signal to power supply terminal.Also disclose corresponding electronic equipment and method.
Description
Technical field
Embodiments of the invention relate generally to circuit field, more specifically, relate to the feed circuit of shared power management module, electronic equipment and correlation method.
Background technology
In modern circuits, be responsible for control objectives equipment (such as, light emitting diode LED) chip usually need the driving voltage of the target device regulating it to control by means of power management module (such as, stepup transformer boost, reducing transformer buck or buck-boost device buck-boost).Usually, chip is connected with power management module, and controls the operation of power management module by control signal.Power management module then be connected to target device.In common configuration, also set up between target device and chip and have backfeed loop, for the information such as current voltage are returned to chip.As fruit chip by backfeed loop the current voltage of information determination target device that is fed to too high or too low, the driving voltage that it can correspondingly utilize control signal to control power management module to promote or reduce equipment.
In the prior art, common circuit structure is for each chip is equipped with a special power management module.Can guarantee that each chip can the voltage of accurately control objectives equipment like this.But be understandable that, this will cause higher cost.And each chip must have the pin (pin) for being connected with power management module.For the chip that some pin is less, this may be inconvenient.
Because the problems referred to above, in this area, need a kind of solution supporting to be shared by multiple chip same power management module.
Summary of the invention
In order to the problem solved the aforementioned problems in the prior and other are potential, embodiments of the invention provide a kind of feed circuit of shared power management module, electronic equipment and correlation method.
In one aspect of the invention, a kind of feed circuit are provided.These feed circuit comprise: the first chip, there is the first terminal, second terminal and power managing signal circuit for generating, wherein said power managing signal circuit for generating operation produces corresponding analog control signal with the logic state according to the digital signal in the common lead be connected to described the first terminal, and export described analog control signal through described second terminal, wherein said common lead is connected with the first terminal of described first chip, and operation is can connect to the corresponding the first terminal of at least one the second chip, and wherein said second chip has or does not have corresponding second terminal, and power management module, there is control terminal and power supply terminal, and operation is to receive described analog control signal from described control terminal, and controls based on the output voltage of described analog control signal to described power supply terminal.
In another aspect of this invention, a kind of electronic equipment is provided.This electronic equipment comprises: multiple chip, each described chip has respective the first terminal, and operation can provide digital signal independently on respective the first terminal, and a selected chip in wherein said multiple chip also has the second terminal and power managing signal circuit for generating; , a common lead, is connected with described multiple chip the first terminal separately; And power management module, there is power supply terminal and control terminal, described power supply terminal is connected to the target device be associated with described multiple chip, described control terminal is connected to described second terminal of described selected chip, and the described power managing signal circuit for generating operation of wherein said selected chip is with the output voltage controlling described power management module according to the described digital signal in described common lead via described second terminal.
In still another aspect of the invention, a kind of method of supplying power to is provided.This method of supplying power to comprises: in the first chip, detect the logic state of the digital signal on the first terminal of described first chip, the first terminal of wherein said first chip is connected with a common lead, and described common lead operation is also to connect to the corresponding the first terminal of at least one the second chip; In described first chip, based on the logic state of described digital signal, produce corresponding analog control signal, and export described analog control signal through the second terminal of described first chip; And in a power management module, receive described analog control signal, to control accordingly the output voltage of described power management module.
Will be understood that by hereafter describing, utilize embodiments of the invention, multiple chip can share a power management module effectively.Each chip operation regulates the output voltage of power management module with the digital signal exporting particular logic state to public lead-in wire, thus realizes the adjustment to target device operating voltage.
Accompanying drawing explanation
By reference to accompanying drawing reading detailed description hereafter, above-mentioned and other objects of the embodiment of the present invention, feature and advantage will become easy to understand.In the accompanying drawings, show some embodiments of the present invention by way of example, and not by way of limitation, wherein:
Fig. 1 shows the schematic block diagram of the electronic equipment of the feed circuit comprised according to an illustrative embodiment of the invention;
Fig. 2 shows the schematic block diagram of the electronic equipment of the feed circuit comprised according to an illustrative embodiment of the invention;
Fig. 3 and Fig. 4 shows the schematic block diagram of the chip the first terminal according to exemplary embodiment of the present invention;
Fig. 5 shows the exemplary operations sequential chart of the feed circuit that composition graphs 2 describes; And
Fig. 6 shows the indicative flowchart of method of supplying power to according to an illustrative embodiment of the invention.
Embodiment
Some exemplary embodiments below with reference to the accompanying drawings describe principle of the present invention and spirit.Should be appreciated that providing these embodiments is only used to enable those skilled in the art understand better and then realize the present invention, and not limit the scope of the invention by any way.
First with reference to figure 1, it illustrates the schematic diagram of the electronic equipment of the feed circuit comprised according to an illustrative embodiment of the invention.As shown in Figure 1, electronic equipment comprises feed circuit 100, and feed circuit 100 comprise the first chip 103 and power management module 108.First chip 103 has the first terminal 106, second terminal 114 and power managing signal circuit for generating 115.The first terminal 106 is connected with a common lead 107, and this common lead 107 operates to be connected to the corresponding the first terminal 104,105 of at least one in electronic equipment second chip 101,102.First chip 103 and the second chip 101,102 can be any special or general chips developed known or future at present, and its operation is with the operating voltage controlling corresponding target device.Target device such as can comprise multi-group light-emitting diode, often organizes light emitting diode and is associated with in chip 101,102 and 103.
In operation, each in first chip 103 and the second chip 101,102 all can via its corresponding the first terminal independently to lead-in wire 107 output digit signals (or claiming numerical control word), thus the control realized target device operating voltage, this will be explained below.Although note that and illustrate only two the second chips 101 and 102 in the drawings, this is only schematic.The second chip of arbitrary number can be comprised according to the electronic equipment of the embodiment of the present invention.
Especially, according to embodiments of the invention, the second chip 101,102 can comprise the second terminal and also can not comprise the second terminal.Specifically, the second chip 101,102 can be the chip identical with the first chip 103, that is, comprise the first terminal and the second terminal simultaneously.In this case, any one in multiple chips 101,102,103 of comprising of electronic equipment can be selected to serve as the first chip.Alternatively, the second chip 101,102 also can not have the second terminal, but the chip more simple for the first chip 103, cost is lower.
Feed circuit 100 also comprise power management module 108, for powering for each target device and regulating the operating voltage of target device.As shown in the figure, power management module 108 has control terminal 109 and power supply terminal 110.Power supply terminal 110 be connected to be associated with chip 101,102 ..., 103 respectively target device 111,112 ..., 113.Be appreciated that these target devices 111, output voltage that 112 ..., 113 are provided by power management module 108 drives.In other words, the output voltage of power management module 108 can be considered to target device 111,112 ..., 113 operating voltage.
The control terminal 109 of power management module 108 is connected to the second terminal 114 of the first chip 103.According to embodiments of the invention, first chip 103 operates to produce corresponding analog control signal according to the logic state of the digital signal on lead-in wire 107, and export this analog control signal via the second terminal 114 to power management module 108, to regulate the output voltage of power management module 108.Correspondingly, power management module operation is to control based on the output voltage of analog control signal to power supply terminal 110 place.
In addition, between the chip that each target device is associated with it, backfeed loop (not illustrating in the drawings) can be had, the operating voltage of this target device is fed back to chip.This feedback can be in real time, termly or in response to the request of chip, scope of the present invention is unrestricted in this regard.
In operation, if the first chip 103 or any one the second chip 101,102 detect that the operating voltage of the target device of associated does not meet predetermined condition (normally lower than predetermined threshold voltage), then this chip can produce the digital signal of a particular logic state and export this digital signal via the first terminal to lead-in wire 107, wishes the operating voltage regulating target device to indicate it.Power managing signal circuit for generating in first chip 103 and power management module 108 in response to the digital controlled signal this particular logic state being detected on lead-in wire 107, and can correspondingly promote or reduce the operating voltage of target device.Concrete regulative mode also will be explained below.
If all chips 101,102 ..., 103 the operating voltage of associated objects equipment all conform to a predetermined condition (such as, all higher than predetermined threshold voltage), then lead-in wire 107 can not exist the digital signal of the particular logic state of instruction booster tension.In this case, according to some embodiment of the present invention, the power managing signal circuit for generating 115 of the first chip 103 operates to control the output voltage that power management module 108 reduces power supply terminal 110 place, that is, reduce the output voltage outputting to target device.Do like this be conducive to energy-conservation.Once the output voltage of power management module 108 reduces under the normal working voltage of certain target device, corresponding chip will detect this situation and indicate booster tension.In such embodiments, the first chip 103 such as can control the output voltage that power management module 108 regularly reduces power supply terminal 110.Such as, power management module 108 can regularly reduce the output voltage of power supply terminal 110 based on the cycle of 320ms.This is only exemplary, and other any suitable cycles all likely.
And according to some embodiment of the present invention, the speed that power management module 108 reduces the output voltage of power supply terminal 110 is slower than the speed of booster tension.In other words, when all chips all do not indicate booster tension, power management module 108 operates the output voltage reducing power supply terminal 110 lentamente.But if detect that on lead-in wire 107 any chip sends the digital signal for booster tension, then the first chip 103 operates to control the output voltage that power management module 108 promptly promotes power supply terminal 110.
Below with reference to Fig. 2, it illustrates the schematic block diagram of the electronic equipment of the feed circuit comprised according to an illustrative embodiment of the invention.Be appreciated that the feed circuit that composition graphs 2 describes are above with reference to the exemplary specific implementation of one of the feed circuit of figure 1 description.
As shown in Figure 2, in this embodiment, electronic equipment comprises at least one resistor 201, and it is connected to the first chip 103 via lead-in wire 107 and between each second chip 101,102 and power supply (VDD).Resistor 201 can be called " pull-up resistor ".In the embodiment shown in Figure 2, the first terminal of each chip can be the pin of open drain, such as, realize by means of device such as MOS (metal oxide) transistor, diode etc.Such as, in the embodiment shown in Figure 2, the first terminal can adopt N-type MOS (NMOS) transistor to realize, and this is not necessarily certainly.Fig. 3 shows the schematic diagram of the first terminal of each chip in the first chip 103 and the second chip 101,102, and this first terminal utilizes N-type MOS transistor 301 to realize.Fig. 3 also illustrate in detail the annexation of N-type MOS transistor 301 and lead-in wire 107 and pullup resistor 201.Be appreciated that in such embodiments, the logic state of the digital signal in common lead 107 is the "AND" of the logic state signal that chip 101-103 exports to lead-in wire 107.In one example in which, the digital signal to the particular logic state of lead-in wire 107 output can be logic low or zero-signal (e.g., low level signal).Usually, the resistance value of resistor 201 is fully greater than the resistance value of the first terminal of chip.Such as, in certain embodiments, the resistance value of resistor 201 can be about 100 kilo-ohms, and this is only exemplary certainly.
In the embodiment shown in Figure 2, each chip 101,102 ..., 103 operation with the operating voltage in response to the target device be associated with this chip higher than predetermined threshold not to described lead-in wire output digit signals.It will be appreciated by those skilled in the art that, in this case, in fact be in electric blocking state between chip and lead-in wire 107, and the digital signal gone between on 107 due to resistor 201 pulling efficient should and be in logic high (such as, logical one) state.
When the first chip 103 detects logic high signal on lead-in wire 107, it can determine that all chips all do not indicate the output voltage promoting power management module 108.Now, according to some embodiment, power managing signal circuit for generating 115 in first chip 103 and power management module 108 operate the digital signal of the particular logic state instruction booster tension not detected in common lead 107, keep the output voltage of power supply terminal 110 constant.Alternatively, as mentioned above, power managing signal circuit for generating 115 and power management module 108 also operate the digital signal of the particular logic state instruction booster tension not detected in common lead 107, reduce the output voltage of power supply terminal 110.Such as, power managing signal circuit for generating 115 and power management module 108 operate the output voltage regularly slowly to reduce power supply terminal 110 in this case, thus reach energy-conservation object.
On the other hand, if any chip detection in the first chip 103 and the second chip 101,102 to the operating voltage of the target device of associated lower than predetermined threshold voltage, then this chip operation is with to lead-in wire 107 output low level signal, namely drags down the signal logic of lead-in wire 107.It will be understood by those skilled in the art that the signal on whole lead-in wire 107 will be in logic low (such as, logical zero) state when any one chip is to lead-in wire 107 output logic low signal.Correspondingly, the first chip 103 operates and promotes output voltage to control power management module 108 in response to logic low signal being detected on lead-in wire 107.Especially, for the reduction of certain target device operating voltage, power management module 108 more promptly can promote the output voltage of power supply terminal 110.
Specifically, in the embodiment shown in Figure 2, the power management module 108 in feed circuit comprises resistor 202,205 and 206, amplifier 203 and electric power management circuit 204.Electric power management circuit 204 can be such as one of following: stepup transformer, reducing transformer and buck-boost device.In operation, when the first chip 103 determines according to the logic state of the digital signal on lead-in wire 107 output voltage needing to improve power management module 108, operate to produce the analog control signal lower than reference signal (in figure " ref ").Such as, power managing signal circuit for generating 115 can comprise voltage digital analog converter (DAC) and/or capacitive element (not shown), its operation is with by particular logic state (such as, digital signal 0-31) is converted to corresponding analog control signal (such as, 0-250mA).Thus, power managing signal circuit for generating 115 operates to produce the analog control signal lower than reference signal ref.Digital-to-analog conversion technology is known in the art, does not repeat them here its details.Analog control signal exports via the control terminal 109 of the second terminal 114 to power management module 108, and is fed to the inverting input of amplifier 203 after flowing through resistor 202.Amplifier 203 is exported via output terminal is supplied to electric power management circuit 204, with the output voltage making electric power management circuit 204 promote supply node 110.According to embodiments of the invention, the adjustment that electric power management circuit 204 can realize output voltage by the parameter such as pulsed modulation width (PWM), dutycycle of control voltage, these are known in the art.
Otherwise, when the first chip 103 determines the output voltage without the need to improving power management module 108, power managing signal circuit for generating 115 operates to produce the analog control signal being not less than reference signal ref, keeps or reduce output voltage to make voltage management circuitry.
Should be appreciated that to be only a kind of possible embodiments of power management module 108 shown in Fig. 2, be not intended to limit scope of the present invention.Such as, in an alternative embodiment, the analog control signal that the first chip 103 exports can be fed to the normal phase input end of amplifier 203, and reference signal is then fed to the inverting input of amplifier 203.Now, when the first chip 103 is determined to need to promote output voltage, power managing signal generating means 115 operates to produce the analog control signal higher than reference signal; Vice versa.
In addition, embodiments of the invention are not limited to use N-type MOS transistor as the first terminal of the first chip and each second chip, and N-type MOS transistor is applicable equally.Such as, Fig. 4 shows an embodiment utilizing N-type MOS transistor 401 to serve as the first terminal of the first chip and each second chip.Fig. 4 illustrate in detail the feasible annexation of one of N-type MOS transistor 401 and power vd D, resistor 402 (can be described as " pull-down-resistor ") and ground VSS.Be appreciated that in such embodiments, the signal logic in common lead 107 is the "or" of the logic state signal that each chip exports to common lead.In one example in which, the digital signal of particular logic state exported to lead-in wire 107 can be high or one signal (e.g., high level signal) of logic.Correspondingly, when any one chip in the first chip 103 and the second chip 101,102 wishes the operating voltage promoting its target device, the digital signal of the particular logic state that this chip exports to lead-in wire 107 is a high level signal.
Should also be understood that above-described is only the exemplary embodiment of power management module 108.Any circuit that can realize voltage-regulation that is known or that develop in the future or device at present all can be combined with embodiments of the invention, and scope of the present invention is unrestricted in this regard.
With reference to figure 5, it illustrates the time sequential routine figure of the feed circuit that composition graphs 2 above describes.As shown in the figure, line 501-503 represents the waveform of the digital signal that the chip 101,102 and 103 shown in Fig. 2 exports to lead-in wire 107 respectively, line 504 represents the logic state of the digital signal on lead-in wire 107, and line 505 represents the output voltage waveforms of power management module 108.Be appreciated that in the circuit shown in Fig. 2, when the first terminal adopting NMOS as chip, the signal logic on lead-in wire 107 is the logical "and" of the signal that each chip is applied to lead-in wire application 107.
As shown in Figure 5, before moment T1, chip 101-103 all detects that the operating voltage of its corresponding target device is lower than threshold voltage, and therefore chip 101-103 is to lead-in wire 107 output logic low signal (line 501-503).Signal logic on lead-in wire 107 is dragged down (line 504).Responsively, the first chip (being chip 103 in this instance) operation promotes its output voltage (line 505) to control power management module 108.
Next, at moment T1, chip 101 detects that the operating voltage of its target device reaches predetermined threshold, and therefore it stops outputing signal to lead-in wire 107.In other words, after moment T1, chip 101 is in electric blocking state (line 501) with lead-in wire 107.But because chip 102 and 103 is still to lead-in wire 107 output logic low signal (line 502 and 503), therefore the signal logic on lead-in wire 107 is still low (line 504), and continuation control power management module 108 is promoted output voltage (line 505) by the first chip.
Subsequently at moment T2, the operating voltage of the target device be associated with chip 103 also reaches predetermined threshold, and chip 103 breaks (line 503) with lead-in wire 107 resistance thereupon.Similarly, at moment T3, after the operating voltage of the target device of chip 102 is also higher than predetermined threshold voltage, chip 102 and lead-in wire 107 resistance disconnected (line 502).Now, all chips are not all to lead-in wire applied logic low signal, and the signal logic of lead-in wire 107 becomes height (line 504), thus make the first chip power management module 108 of ceasing and desisting order promote output voltage (line 505).
Especially, as mentioned above, in certain embodiments, when all chips all do not indicate lifting output voltage, power management module 108 periodically can reduce its output voltage (line 505).In the example depicted in fig. 5, the output voltage of voltage management module 108 drops at moment T4 under the operating voltage needed for target device of chip 102.In response to this, chip 102 again drags down the signal logic (line 502 and 504) of lead-in wire 107 from moment T4, controls supercharging module 108 again promote its output voltage (line 505) to make the first chip 103.At moment T5 subsequently, the operating voltage of the target device of chip 102 returns to the proper level on threshold voltage.Correspondingly, chip 102 stops dragging down lead-in wire 107 (line 502) again, makes the signal logic of lead-in wire 107 become height (line 504).Thus, power management module 108 stops promoting output voltage (line 505) from moment T5.Follow-up sequential by that analogy.
Below with reference to Fig. 6, it illustrates the indicative flowchart of method of supplying power to according to an illustrative embodiment of the invention.
After method starts, in step S601, the logic state of the digital signal on the first terminal of described first chip is detected in the first chip, the first terminal of wherein said first chip is connected with a common lead, and described common lead operation is also to connect to the corresponding the first terminal of at least one the second chip.
Next, in step S602, the logic state based on described digital signal in described first chip produces corresponding analog control signal, and exports described analog control signal through the second terminal of described first chip.According to some embodiment, be in a particular logic state in response to described digital signal, described analog control signal makes the output voltage of described power management module be raised.Alternatively or additionally, be not in a particular logic state in response to described digital signal, described analog control signal makes the output voltage of described power management module be lowered.And according to some embodiment of the present invention, be not in a particular logic state in response to described digital signal, described analog control signal makes the output voltage of described power management module regularly be reduced.
Method proceeds to step S603 then, at this, in a power management module, receives described analog control signal, to control accordingly the output voltage of described power management module.
Method terminates after step S603.Be appreciated that the feed circuit that method that composition graphs 6 describes describes based on composition graphs 1-Fig. 5 above and respective electronic equipment and realize.Thus, each feature that composition graphs 1-Fig. 5 describes above is equally applicable to the method that composition graphs 6 describes, and does not repeat them here.
Be hereinbefore described some embodiments of the invention.Can see, utilize embodiments of the invention, multiple chip can share a power management module effectively.Each chip can send to public lead-in wire the output voltage that logical signal regulates power management module, thus realizes the adjustment to target device operating voltage.
Note, term is only not intended as restriction disclosure to describe specific embodiment as used herein.Such as, express unless context separately has, singulative "/a kind of " and " being somebody's turn to do " are intended to also comprise plural form as used herein.Also by understand word " comprise " to specify when being used in this instructions there is statement feature, one integral piece, step, operation, unit and/or parts and do not get rid of and there is or add one or more other features, one integral piece, step, operation, unit, parts and/or its combination.
Although some embodiments of the present invention have been described with reference to the drawings above, should be appreciated that, the present invention has been not limited to disclosed specific embodiment.The present invention is intended to contain the interior included various amendment of spirit and scope and the equivalent arrangements of claims.The scope of claims meets the most wide in range explanation, thus comprises all such amendments and equivalent structure and function.
Claims (20)
1. feed circuit, comprising:
First chip, there is the first terminal, the second terminal and power managing signal circuit for generating, wherein said power managing signal circuit for generating operation produces corresponding analog control signal with the logic state according to the digital signal in the common lead be connected to described the first terminal, and export described analog control signal through described second terminal
Wherein said common lead is connected with the first terminal of described first chip, and can connect to the corresponding the first terminal of at least one the second chip, and wherein said second chip has or do not have corresponding second terminal; And
Power management module, has control terminal and power supply terminal, and operation is to receive described analog control signal from described control terminal, and controls based on the output voltage of described analog control signal to described power supply terminal.
2. feed circuit according to claim 1, each in wherein said first chip and at least one second chip described all operates with in the digital signal producing a particular logic state described in hope when power management module boosted output voltages on the corresponding the first terminal of this chip; And
Wherein said power managing signal circuit for generating and the operation of described power management module are to raise the output voltage of described power supply terminal in response to the digital signal described particular logic state being detected in described common lead.
3. feed circuit according to claim 2, the corresponding the first terminal of each in wherein said first chip and at least one second chip described comprises the source electrode of a N-type metal-oxide-semiconductor, and the digital signal of described particular logic state is a low level signal.
4. feed circuit according to claim 2, the corresponding the first terminal of each in wherein said first chip and at least one second chip described comprises the drain electrode of a P type metal-oxide-semiconductor, and the digital signal of described particular logic state is a high level signal.
5. feed circuit according to claim 2, wherein said power managing signal circuit for generating and described power management module also operate the output voltage to reduce described power supply terminal when the digital signal described particular logic state not detected in described common lead.
6. feed circuit according to claim 2, wherein said power managing signal circuit for generating and described power management module also operate the output voltage regularly to reduce described power supply terminal when the digital signal described particular logic state not detected in described common lead.
7. feed circuit according to any one of claim 1 to 6, wherein said power managing signal circuit for generating comprises a voltage digital analog converter.
8. feed circuit according to any one of claim 1 to 6, wherein said power managing signal circuit for generating comprises a capacitive element.
9. feed circuit according to any one of claim 1 to 6, wherein said power management module comprises one of following: stepup transformer, reducing transformer and buck-boost device.
10. an electronic equipment, comprising:
Multiple chip, each described chip has respective the first terminal, and on respective the first terminal, can provide digital signal independently, and a selected chip in wherein said multiple chip also has the second terminal and power managing signal circuit for generating;
, a common lead, is connected with described multiple chip the first terminal separately; And
Power management module, there is power supply terminal and control terminal, described power supply terminal is connected to the target device be associated with described multiple chip, described control terminal is connected to described second terminal of described selected chip, and the described power managing signal circuit for generating operation of wherein said selected chip is with the output voltage controlling described power management module according to the described digital signal in described common lead via described second terminal.
11. electronic equipments according to claim 10, wherein each described chip operation does not export the digital signal of particular logic state to described common lead higher than predetermined threshold with the operating voltage in response to the target device be associated with this chip.
12. electronic equipments according to claim 10, wherein each described chip operation exports the digital signal of particular logic state to described common lead lower than predetermined threshold with the operating voltage in response to the target device be associated with this chip.
13. electronic equipments according to claim 12, wherein said selected chip operation with in response to the digital signal described particular logic state being detected in described common lead, and raises described output voltage via power management module described in described second Terminal control.
14. electronic equipments according to claim 12, wherein said selected chip operation with in response to the digital signal described particular logic state not detected in described common lead, and reduces described output voltage via power management module described in described second Terminal control.
15. electronic equipments according to claim 12, wherein said selected chip operation with in response to the digital signal described particular logic state not detected in described common lead, and regularly reduces described output voltage via power management module described in described second Terminal control.
16. according to claim 12 to the electronic equipment according to any one of 15, and wherein said target device comprises multi-group light-emitting diode, often organizes described light emitting diode and is associated with in described multiple chip.
17. 1 kinds of method of supplying power to, comprising:
In the first chip, detect the logic state of the digital signal on the first terminal of described first chip, the first terminal of wherein said first chip is connected with a common lead, and described common lead operation is also to connect to the corresponding the first terminal of at least one the second chip;
In described first chip, based on the logic state of described digital signal, produce corresponding analog control signal, and export described analog control signal through the second terminal of described first chip; And
In a power management module, receive described analog control signal, to control accordingly the output voltage of described power management module.
18. methods according to claim 17, are wherein in a particular logic state in response to described digital signal, and described analog control signal makes the output voltage of described power management module be raised.
19. methods according to claim 17, are not wherein in a particular logic state in response to described digital signal, and described analog control signal makes the output voltage of described power management module be lowered.
20. methods according to claim 17, are not wherein in a particular logic state in response to described digital signal, and described analog control signal makes the output voltage of described power management module regularly be reduced.
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| CN113177386B (en) * | 2021-04-27 | 2023-09-22 | 北京百度网讯科技有限公司 | Integrated circuit and electronic device |
| CN114675698B (en) * | 2022-03-17 | 2023-09-29 | 北京芯格诺微电子有限公司 | Voltage regulation method of multi-load system based on single bus communication |
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Address after: 300457, room 2, building 19, No. 2701-2 West Ring Road, Tianjin economic and Technological Development Zone, Tianjin, Tanggu Patentee after: Dai Luo lattice integrated circuit (Tianjin) Co. Ltd. Address before: 300457, room 2, building 19, No. 2701-2 West Ring Road, Tianjin economic and Technological Development Zone, Tianjin, Tanggu Patentee before: Eyre watt integrated circuit technology (Tianjin) Co., Ltd. |