CN103840841A

CN103840841A - Method for designing PTCM+8PSK codec capable of overcoming seven kinds of phase ambiguity

Info

Publication number: CN103840841A
Application number: CN201410047110.3A
Authority: CN
Inventors: 郭勇; 何军; 陈艳玲
Original assignee: Individual
Current assignee: Individual
Priority date: 2014-02-11
Filing date: 2014-02-11
Publication date: 2014-06-04

Abstract

The invention discloses a method for designing a PTCM+8PSK codec capable of overcoming seven kinds of phase ambiguity. The method is combined with coded modulation mapping to generate an 8PSK modulating signal. A decoder designed with method can overcome seven kinds of phase ambiguity which are 45 degrees, 90 degrees, 135 degrees, 180 degrees, 225 degrees, 270 degrees and 315 degrees respectively. Under the low SNR and the narrow bandwidth, the low error rate which is required by a practical communication system can be obtained. The designed modules comprises the control module, the differential coding and decoding module, the convolution coder module, the codec module capable of overcoming phase ambiguity, the soft-decision Viterbi decoder module, the branch matrix, the section value rotating module, the ROM list storing module, the normalization rate monitoring circuit and the like. By means of the design method, under the extremely few hardware resources and the low SNR, the satisfying BER can be obtained and at the same time, the good error correction performance can be achieved on the seven kinds of phase ambiguity by means of the method for designing the PTCM+8PSK codec capable of overcoming the seven kinds of phase ambiguity.

Description

A kind of method for designing of the PTCM+8PSK coder that overcomes 7 kinds of phase ambiguities

Technical field

The invention belongs to modulation, encoding and decoding decoding technique field, belong to the technical field of radio communication, relate to the designing technique of 8PSK digital modulation technique and TCM coder etc.

Background technology

Coding and modulation are separated consideration by traditional digital communication, for all limited channels of power and bandwidth, the gain that is difficult to improve coding.TCM (Trellis Coded Modulation) Trellis-coded modulation is that coding and modulation are done to as a whole design, this technology can not increase signal bandwidth, do not reduce in the situation of effective information transmission rate, obtain obvious coding gain.

Summary of the invention

The technical problem that the present invention solves is: in 8PSK modulation mode, have 7 kinds of phase ambiguities, current technology can only solve the problem of part phase ambiguity, and can not solve all phase ambiguity.Technical scheme of the present invention is as follows:

PTCM+8PSK coder module, the parallel data [α, β] of two-way are carried out differential coding, convolutional encoding, are overcome phase ambiguity encoder etc., generate the parallel data [ENC2, ENC1, ENC0] in 3 tunnels, are sent in 8PSK modulation mapper.

Two-phase differential encoder module, the value of source data din and register D is carried out mould 2 and is added namely XOR of computing, and operation result is output on the one hand, is sent in register on the one hand, for computing is next time prepared.

Two-phase differential decoderl module, the data of sending in data and the register of decoder are done XOR, operation result output, former input data are sent into register simultaneously, for computing is next time prepared.

Overcome phase ambiguity coder module, this module operation principle, in the time of ENCC1=0, source data α, from the input of u passage, first carries out differential coding, then exports, and the data of v channel register keep initial value constant; In the time of ENCC1=1, source data α, from the input of v passage, first carries out differential coding, then exports, and the data of u channel register keep initial value constant.

Overcome phase ambiguity decoder module, this module operation principle, in the time of Code_1=0, source data β, from the input of u passage, first carries out differential decoding, then exports, and the data of v channel register keep initial value constant; In the time of Code_1=1, source data β, from the input of v passage, first carries out differential decoding, then exports, and the data of u channel register keep initial value constant.

8PSK modulation mapping output, in the time that three-channel parallel data [ENCC2, ENCC1, ENCC0] are exported, every three parallel bits are selected an initial phase of 8PSK carrier (boc) modulated signals.As shown in Figure 6, if value is 001 o'clock, initial phase is π/4, if value is 011 o'clock, initial phase is pi/2, and the rest may be inferred.

PTCM+8PSK design of encoder principle, is divided into 3 steps, the first step, and the I receiving, Q two paths of signals change into the phase point on planisphere, inquire about the Euclidean distance BM00 of

phase point distance

00,01,10,11 by the phase value of signaling point, BM01, BM10, BM11.Then the soft-decision Viterbi decoder of four distance values should putting being sent into standard.ROM shows each unit and has stored the BM11 of signaling point, BM10, BM01, BM00 and Sector (sector value).

Send into two-phase differential decoderl translates low-order bit (sending into PTCM+8PSK encoder) to the bit that Viterbi decoder translates on the one hand, the bit being translated by Viterbi decoder passes through (2 again, 1,7) convolution coder, the high position output bit associating Sector value of this encoder translates sends into the bit that overcomes phase ambiguity encoder, overcome again phase ambiguity decoding, translate high order bit.Decoding principle figure as shown in Figure 7.

Branch's matrix and sector value rotary module, in the time of decoder step-out, OUTSYNC uprises, and this signal enters D toggle flipflop, produces Synching signal.When Synching signal is while being high, BM ₀₀=BM ₁₀, BM ₁₀=BM ₁₁, BM ₁₁=BM ₀₁, BM ₀₁=BM ₀₀, at this moment sector value SN=SN+1, that is to say, while rotation, and SN=0, after rotating, SN=1, if SN=7, after rotating, SN=0.If do not rotated, BM ₀₀=BM ₀₀, BM ₀₁=BM ₀₁, BM ₁₀=BM ₁₀, BM ₁₁=BM ₁₁, SN=SN.

Normalizing rate supervisory circuit module, cnt_en reset N counter and T counter while reset, load initial value at every turn, and the initial value of T counter is 0, and full value is 255, and clock is decoding clock clk, and the initial value of N counter is 0, and full value is 12, and clock is also clk.In the time that any one counter first reaches peak, cnt_en uprises at the rising edge of next clock, then resets, if N counter now uprises, through D toggle flipflop, Rotate_EN signal is uprised, make branch's matrix and sector value matrix rotation circuit working.

Brief description of the drawings

Fig. 1 is PTCM+8PSK coder structure schematic diagram

Fig. 2 is two-phase differential encoder structural representation

Fig. 3 is two-phase differential decoderl structural representation

Fig. 4 is for overcoming phase ambiguity coder structure schematic diagram

Fig. 5 is for overcoming phase ambiguity decoder architecture schematic diagram

Fig. 6 is PTCM coding and 8PSK modulation output mapping signal

Fig. 7 is PTCM+8PSK decoder architecture schematic diagram

Fig. 8 is branch's matrix rotation and sector value rotation schematic diagram

Fig. 9 is normalizing rate supervisory circuit schematic diagram

Figure 10 is branch's matrix rotation circuit and Viterbi decoder connection diagram

Figure 11 is (2,1,7) convolution coder structural representation

Figure 12 is PTCM+8PSK decoder error-correcting performance curve chart under different SNR conditions

Embodiment

As shown in Figure 1, the present invention proposes a kind of PTCM+8PSK encoder, comprise with lower module: differential coding module, (2,1,7) convolutional encoding module, overcomes phase ambiguity coder module and 8PSK modulation mapping block.

As shown in Figure 2, establish D register initial value and be made as 0, D=0; Dout=D^din; D=dout, cycle calculations can obtain the value of differential coding.

As shown in figure 11, establish register state=[000_000]; If the rising edge of each clock input data are din, the each output dout[1 in I road]=din^state[5] ^state[4] ^state[3] ^state[0];

The output dout[0 on Q road]=din^state[4] ^state[3] ^state[1] ^state[0]; State={din, state[5:1]).

Adopt this algorithm, can obtain the parallel Output rusults dout[1:0 of two-way of (2,1,7) convolution coder].

As shown in Figure 3, for two-phase differential decoderl, establish D register initial value and be made as 0, D=0; Dout=D^din; D=din, cycle calculations can obtain the value of differential decoding.

As shown in Figure 4, for overcoming phase ambiguity encoder, establish α ₁road is u road, α ₀road is v road, and temp_u is the register of u road differential encoder, and temp_v is the register of v road differential encoder, and calculation procedure is as follows:

Adopt the algorithm of the present invention's introduction, can overcome the output valve of phase ambiguity encoder.

As shown in Figure 4, for overcoming phase ambiguity decoder, establish β ₁road is u road, β ₀road is v road, and temp_u is the register of u road differential decoderl, and temp_v is the register of v road differential decoderl, and calculation procedure is as follows:

Adopt the algorithm of the present invention's introduction, can overcome the output valve of phase ambiguity decoder.

As shown in Figure 9, for the design of normalizing rate monitoring module, in Viterbi decoder, in the time that all state matrixs (State Metric) all reach a particular value, inner matrix normalization circuit will deduct this particular value and prevent from overflowing from all state matrixs.Viterbi-IP core has the output signal Normaliz[7..0 of 8], Viterbi decoder often carries out normalization operation, Normaliz[7..0] value adds 1.When received signal points occurs 45 °, 135 °, 225 °, when 315 ° of phase place deflection, State Metric advances the speed and uprises abnormally,, within very short time, will carry out a normalization and operate to prevent from overflowing.Therefore, within one given period, set a thresholding, if normalized number of times does not reach this threshold value, when Rotate_EN=0, we think that Viterbi decoder is in synchronous regime, and branch's matrix circuit does not rotate; In the time that N counter exceedes threshold value, Rotate_EN=1, we think that Viterbi decoder is in desynchronizing state, and at this moment, branch's matrix and sector value matrix circuit rotate, and in this article, the value that the value of T counter is made as 255, N counter is made as 12.

The design of ROM look-up table, Important Circuit of PTCM decoder is exactly the design of ROM table, the storage of ROM table be that distance between point on planisphere and adjacent four signaling points is BM11, BM10, BM01, the Euclidean distance value of BM00.Q1900 has provided the conversion table to Branch Metric according to phase angle value, how to realize this ROM table but do not introduce.Provide concrete implementation method herein.I road and Q road always have four quadrants.Constellation radius of graph is 1, represents with 8 bits, and 1 is sign bit, and 7 is data bit.1 is quantized into 127, and 1111111, establish 4 quadrantal points and be respectively (0.5,0.6), (0.5,0.6), (0.5 ,-0.6), (0.5 ,-0.6) 0.5 is quantized into 1000000, because 0.5 be positive number, is shown 01000000 with 8 bit tables.0.6 is quantized into 1001100, because be positive number, is shown 01001100 with 8 bit tables.

look into conversion table and can obtain BM11=3, BM10=7, BM01=0, BM00=4, Sector=1.ROM table represents i.e. [I, Q] by 16 bit address, so the value of address [01000000,01001100] corresponding (0.5,0.6) storage is [011,111,000,100,001].What be that ROM shows that each address location stores successively is the value of [BM11, BM10, BM01, BM00].-0.5 use complement representation, to 01000000 negate, then adds 1, obtains 11000000.

-0.6 use complement representation is: 10110100.The angle value of (0.5,0.6) is 180-50.2=129.8 degree, looks into conversion table and obtains BM11=3, BM10=0, BM01=7, BM00=4, Sector=2.So the value of address [11000000,1001100] storage is [011,000,111,100,010].The rest may be inferred, can obtain, and the angle value of (0.5 ,-0.6) is θ=230.2 degree, table look-up: BM11=3, BM10=7, BM01=0, BM00=4, Sector=5, [11000000,10110100] content of address storage is [011,111,000,100,101]..The rest may be inferred, can obtain [00000000,00000000] to [11111111,11111111] value of totally 65536 address location storages, in Matlab, coding generates roml.mif file, imports in the ROM core of Quartus, can obtain the ROM table that we need.The ROM generating shows as shown in figure 11:

The method for designing of the Viterbi-IP core based on TCM work pattern, on the generation interface of Viterbi-IP core, the first step, at the sub-interface of Architecture, select Parallel item (walking abreast), on Optimization hurdle, select Continuous item (continuously); At the sub-interface of Code Sets, Mode selects T (being TCM pattern), and generator polynomial GA is that 133, GB is 171, N=2, constraint length L=7, in the sub-interface of Parameters, Traceback (traceback depth)=42, Softbits=3, be that soft-decision quantizing bit number number is 3, Frequency (MHz)=50, centre carrier frequency is 50MHZ; At the sub-interface of Test Data, keep default value constant, then order is clicked next step, can generate the Viterbi-IP core of the TCM mode of operation of the present invention's needs.

As shown in Figure 6, in the time that 7 kinds of phase ambiguity occurs 8 possible phase points, the skew of signaling point is in table 1.

Table 1.8PSK signal phase deflection table

As shown in Table 2, adopt the PTCM+8PSK decoder of the present invention's design to have good error correcting capability to 7 kinds of phase ambiguities.

The error-correcting performance table of comparisons of PTCM decoder when out of phase deflection occurs table 2.

Phase place deflected	Error bit sum	Error bit number after error correction	BER after error correction
				45 ° of deflections	131288	5+3＝8	3.81×10 ^-5
90 ° of deflections	262674	15+12＝27	1.28×10 ^-4
				135 ° of deflections	183832	2+0＝2	9.53×10 ^-6
180 ° of deflections	105000	2+0＝2	9.53×10 ^-6
				225 ° of deflections	183712	5+3＝8	3.81×10 ^-5
270 ° of deflections	262326	14+12＝26	1.24×10 ^-4
				315 ° of deflections	131168	0	0

[0035]as shown in Table 2, for 45 ° of deflections, 90 °, 135 °, 180 °, 225 °, 270 °, 315 ° of 7 kinds of phase place deflections, the PTCM+8PSK decoder of the present invention's design has good error correcting capability.As shown in Figure 11, the PTCM+8PSK of the present invention's design is in the situation that SNR is lower, and error-correcting performance is fine, in the time of SNR > 8.5dB, there is no error code.Therefore the designed PTCM decoder of the present invention has good novelty and good service behaviour.

The unspecified part of the present invention belongs to general knowledge as well known to those skilled in the art.

Claims

This PTCM+8PSK coder that overcomes 7 kinds of phase ambiguities comprises with lower module, control module, differential coding and decoding module, convolution coder module, overcome phase ambiguity coder module, overcome phase ambiguity decoder module, soft-decision Viterbi decoder module, branch's matrix and sector value rotation circuit module, ROM show memory module, the design of normalizing rate supervisory circuit etc.Method for designing disclosed in this invention has following characteristics: comprising:

1. described in, overcome phase ambiguity coder module, refer to that two-way source coded data Yi road is through differential coding, carry out again convolutional encoding, another road source coded data and overcome phase ambiguity encoder through the data of convolutional encoding through what be made up of mixer and splitter and differential encoder, generates altogether 3 road parallel outputs.Use this module can overcome 90 °, 180 °, the phase ambiguity of 270 °.
2. described in, overcoming phase ambiguity decoder module, is the contrary module of encoder, and two-phase differential encoder module is wherein replaced by two-phase differential decoderl module.This module is for PTCM+8PSK decoder, the decoding that enters ambiguous encoding device for a road.
3. branch's matrix rotation and sector value rotary module described in, be exactly the BM11 to input, BM10, and BM01, BM00 and Sector value are carried out deflection.This circuit is for overcoming 45 °, 135 °, and 225 °, a part for 315 ° of phase ambiguity circuit.
4. described in, ROM table memory module, is phase place storage BM11, BM10, BM01, BM00 and the Sector value according to phase point in a memory cell.Wherein BM11, BM10, BM01, the value of BM00 is sent in soft-decision Viterbi decoder, translates low-order bit.Sector value translates high order bit in conjunction with the value that overcomes phase ambiguity decoder.
5. the design of normalization supervisory circuit described in, in the time that all state matrixs (State Metric) all reach a particular value, this matrix normalization circuit will deduct this particular value and overflow preventing from all states.Viterbi-IP core has the output signal Normaliz[7..0 of 8], Viterbi decoder often carries out normalization operation, Normaliz[7..0] value adds 1.When received signal points occurs 45 °, 135 °, 225 °, when 315 ° of phase place deflection, State Metric speedup uprises singularly,, within very short time, will carry out normalization operation.The normalizing rate supervisory circuit of design has two counters, T counter and N counter herein.T counter calculates the testing time, and N counter calculates normalized number of times.The threshold value that the threshold value of T counter is made as 255, N counter is made as 12.Within the one given period (T clock cycle), if N does not reach this threshold value 12, when Rotate_EN=0, Viterbi decoder is in synchronous regime, and branch's matrix circuit does not rotate; In the time that N counter exceedes threshold value, Rotate_EN=1, Viterbi decoder is in desynchronizing state, and at this moment, branch's matrix and sector value matrix circuit rotate.
6. soft-decision Viterbi decoder described in, is to adopt IP kernel, adopts the method for parameter setting, is configured to the soft-decision Viterbi decoder of PTCM mode.
7. control module described in, refers to the control signal that produces each submodule, controls the timing coordination work according to the rules of each submodule, completes the coding and decoding work of PTCM+8PSK.