CN103824834B - A kind of semiconductor device with modified model encapsulating structure and manufacture method thereof - Google Patents
A kind of semiconductor device with modified model encapsulating structure and manufacture method thereof Download PDFInfo
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- CN103824834B CN103824834B CN201410075114.2A CN201410075114A CN103824834B CN 103824834 B CN103824834 B CN 103824834B CN 201410075114 A CN201410075114 A CN 201410075114A CN 103824834 B CN103824834 B CN 103824834B
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- H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
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- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
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Abstract
The invention discloses a kind of semiconductor device with modified model encapsulating structure and manufacture method thereof, described semiconductor device includes semiconductor chip, lead frame and potting resin. Semiconductor chip is positioned at the slide glass Ji Dao district of lead frame, and described lead frame includes pin area, and wherein the second upper end, pin area is connected with the second bonding region. It is connected by metal lead wire electricity between semiconductor chip and the second bonding region. Described second bonding region is bigger relative to prior art area, so that it is guaranteed that low chip is when encapsulation, the maximum blowout current limited by metal lead wire can effectively promote, and the conducting resistance of device declines, thus playing chip actual current ability to greatest extent. The present invention is applicable to MOSFET element and IGBT device.
Description
Technical field
The present invention relates to the semiconductor device through encapsulating and manufacture method, especially a kind of power MOSFET device with modified model encapsulating structure or IGBT device and manufacture method thereof, belong to the technical field of semiconductor device.
Background technology
Semiconductor device can final utilization in PCB, be typically passed through chip manufacturing and chip package two parts course of processing, therefore, the characteristic of chip self and the quality of encapsulation technology all directly determine the performance that a device products is final. Continuous lifting along with chip manufacture Integration ofTechnology degree with fineness, the performance of chip self has been obtained for significant progress, many times, encapsulation technology has become the bottleneck of the actually used performance of limits product, and this point is especially embodied on the semiconductor power device of some electric currents high-power, big.
The semiconductor power device commonly used at present includes MOSFET(MOS memory) and IGBT(insulated gate bipolar transistor), this two big class device is all the three-end electrode device of voltage driven type, MOSFET includes grid, source electrode and drain electrode, wherein grid and source electrode are usually located at the front of chip, and drain electrode is usually located at the back side of chip; IGBT includes grid, emitter stage and colelctor electrode, and wherein grid and emitter stage are usually located at the front of chip, and colelctor electrode is usually located at the back side of chip. By existing traditional encapsulation process technology, MOSFET chip or igbt chip are encapsulated into that now widely used three pins are direct insertion or in paster type encapsulation framework, three pin electrodes respectively grid (G) of final finished device, drain electrode (D), source electrode (S) or grid (G), colelctor electrode (C), emitter stage (E), as shown in Fig. 1-a and Fig. 1-b.
Why the pin of above-mentioned MOSFET or IGBT device is to arrange according to G-D-S or G-C-E, is determined by the structure of existing conventional package lead frame. For MOSFET chip, for currently used relatively broad TO-220 encapsulating lead, as shown in Fig. 2-a and Fig. 2-b, this lead frame includes frame body district, slide glass Ji Daoqu and pin area, wherein slide glass Ji Dao district is the platform adhering to and loading chip, and provide chip to the electrically and thermally passage of wiring board, pin area be for connect chip to encapsulation outside electric path, pin area includes three pins, wherein the first pin and the 3rd pin are not attached to slide glass Ji Dao district, and the second pin is connected with slide glass Ji Dao district.The back side of chip adheres to and is loaded into surface, slide glass Ji Dao district, and so, the drain electrode being positioned at chip back is just connected with the second pin electricity; The bonding region on the grid of chip front side, source electrode and the first pin and the 3rd pin top carries out bonding by metal lead wire and connects. Owing to grid needs the electric current of circulation to be far smaller than the electric current of source electrode circulation, therefore, top has the first pin of less bonding region area as grid leading foot, and top has the 3rd pin of bigger bonding region area as source electrode leading foot, thus ultimately forming the pin arrangement of G-D-S.
Owing to being equally spaced between three pins, and the 3rd pin is positioned at side, it is limited to the area of the first pin top bonding region and the position of the second pin, the Area comparison of the 3rd pin top bonding region is limited, it is possible to metal lead wire quantity and wire diameter at the 3rd pin top bonding region surface bond can be subject to bigger restriction, when the maximum current that the maximum current that chip allows to flow through allows to flow through more than source metal lead-in wire, encapsulation just becomes the bottleneck of limits product performance and lifting. Current tradition TO-220 the 3rd pin top bonding region can be bonded the upper limit of aluminum steel quantity and wire diameter and be generally the aluminum steel of 3 20mil or the aluminum steel of 4 15mil, or the aluminium strip of 1 80mil*10mil, corresponding maximum blowout current ability is approximately 120A, so, when chip current ability is more than 120A, the maximum of finally packaged finished device can be limited in 120A by electric current. Device maximum by " Packagelimit " parameter in electric current and product specification.
In addition, source metal number of leads and wire diameter owing to being bonded are limited, so these metal lead wires can be influenced by limit with the bonding area on chip source electrode surface, so can cause that metal lead wire becomes big with the contact resistance of chip surface, thus increasing the conducting resistance that device is overall, and the MOSFET element of a larger current, the conducting resistance of its device itself is just very little, if introducing this part contact resistance above-mentioned, the conducting resistance that it is total is still had a significant impact, with a groove-shaped 80V, the MOSFET of 80A is example, when adopting 2 20mil aluminum wire bondings, its conducting resistance is approximately 6.5m Ω, if using 4 20mil aluminum wire bondings instead, then its conducting resistance can reduce to 5.8m Ω, the range of decrease is more than 10%. " Rdson " parameter in the conducting resistance of device and product specification.
For IGBT device, also there is similar situation. Grid on tradition igbt chip the first interarea and the colelctor electrode on emitter stage and the second interarea; The maximum current of its emitting stage can be subject to the metal lead wire quantity of the 3rd corresponding pin top bonding region surface bond and the restriction of wire diameter, and affects the conducting resistance of device.
Summary of the invention
It is an object of the invention to overcome the deficiencies in the prior art, a kind of semiconductor device with modified model encapsulating structure and manufacture method thereof are provided, for MOFET chip and igbt chip, its source electrode or emitter stage pin have greater area of metal lead wire bonding region, thus the maximum current that boost device allows, reduce the conducting resistance of device, play chip actual current ability to greatest extent.
Technical scheme is as follows:
A kind of semiconductor device with modified model encapsulating structure, including semiconductor chip, lead frame and potting resin;
Described semiconductor chip has the first corresponding interarea and the second interarea, three electrodes respectively first pole of described semiconductor chip, the second pole and the 3rd pole;Described first interarea is provided with the first pole and second pole of semiconductor chip, described second interarea is provided with the 3rd pole of semiconductor chip;
Described lead frame includes the pin area of the frame body district on top, middle slide glass Ji Daoqu and bottom; Described pin area comprise three laid out in parallel and mutually disjunct first pin, the second pin, the 3rd pin, described second pin is positioned in the middle of the first pin and the 3rd pin; Described first pin top is provided with the first bonding region, and the second pin top is provided with the second bonding region, and the area of described second bonding region is more than the area of the first bonding region; Described frame body district is connected with slide glass Ji Dao district, and described slide glass Ji Daoqu is connected with the 3rd pin of pin area; Second interarea of described semiconductor chip adheres to and is mounted on surface, slide glass Ji Dao district;
It is connected by metal lead wire electricity between the first pole and the first bonding region on described semiconductor chip the first interarea, is connected by metal lead wire electricity between the second pole and the second bonding region on described semiconductor chip the first interarea; The 3rd pole on described second interarea is connected with slide glass Ji Dao district and the 3rd pin electricity;
Described potting resin parcel semiconductor chip, the first bonding region, the second bonding region, the 3rd pin top and metal lead wire;
For MOSFET semiconductor chip, the grid of the first of described semiconductor chip extremely MOSFET chip; The source electrode of the second of described semiconductor chip extremely MOSFET chip; The drain electrode of the 3rd of described semiconductor chip extremely MOSFET chip;
For IGBT semiconductor chip, the grid of the first of described semiconductor chip extremely igbt chip; The emitter stage of the second of described semiconductor chip extremely igbt chip; The colelctor electrode of the 3rd of described semiconductor chip extremely igbt chip.
Its further technical scheme is: described non-encapsulated resin parcel pin area in the first pin and the spacing of the second pin and the spacing of the second pin and the 3rd pin equal on same cross section.
Its further technical scheme is: the area of described second bonding region is more than 1.1 times of the first bonding region area, and the shape of described second bonding region and the shape of the first bonding region include being sequentially connected with, by line segment or curve head and the tail, any enclosed figure formed.
Its further technical scheme is: exchange can be exchanged in the position of described first pin and the 3rd pin.
A kind of manufacture method of the semiconductor device with modified model encapsulating structure, the method includes:
A. provide and there is the semiconductor chip of two opposing main faces, the first pole that described semiconductor chip includes being positioned on the first interarea and the second pole and the 3rd pole being positioned on the second interarea;
B., row lead wire framework is provided, described row lead wire framework comprises multiple lead frame connecting arrangement arranged side by side, wherein each lead frame comprises frame body district, slide glass Ji Dao district, pin area and framework bonding pad, described frame body district, slide glass Ji Daoqu and pin area constitute the agent structure of single lead frame, framework bonding pad is for linking together each lead frame, described pin area comprises the first pin, second pin and the 3rd pin, described first pin top is provided with the first bonding region, described second pin top is provided with the second bonding region, described 3rd pin top is connected with corresponding slide glass Ji Dao district,
C. being coated with the silver slurry of liquid in the slide glass Ji Dao district of each lead frame in described row lead wire framework, the slide glass Ji Dao district area covered by silver slurry coating is less than the area in whole slide glass Ji Dao district;
D. being pasted by described semiconductor chip above the slide glass Ji Dao district being placed on above-mentioned coated silver slurry, the second interarea of described chip contacts with silver slurry and is connected;
E. the described row lead wire framework being pasted with chip is placed under low temperature nitrogen environment and carries out the solidification that silver is starched;
F. the first surface, pole on described chip the first interarea and the first bonding region surface bond metal lead wire in corresponding lead frame, thus being connected the first pole with the first pin electricity; The second surface, pole on described semiconductor chip the first interarea and the second bonding region surface bond metal lead wire in corresponding lead frame, thus being connected the second pole with the second pin electricity;
G. described row lead wire framework potting resin being carried out injection moulding and encapsulating, described potting resin wraps up the top of the semiconductor chip above slide glass Ji Dao district, metal lead wire, the first bonding region, the second bonding region and the 3rd pin;
H. the described row lead wire framework being enclosed with potting resin is packaged the hot setting of resin;
I. by the redundancy potting resin in the region of non-encapsulated resin parcel on described row lead wire framework, namely flash is removed;
J. the lead frame of non-encapsulated resin parcel on described row lead wire framework being electroplated, the metal material that described plating uses includes stannum;
K., the lead frame that in described row lead wire framework each passes through encapsulating carries out Trim Molding, the framework bonding pad on lead frame is removed in cutting, several device cells being originally fastened on row lead wire framework are made to be cut into multiple independent device cell, simultaneously, as required the first pin of each device, the second pin and the 3rd pin are bent to the shape specified so that it is pin shapes is suitable for final finished device installation requirements of straight cutting or paster on pcb board;
L., above-mentioned each independent device cell carries out specifying the test of parameter, and the device meeting test specification requirement is carried out laser typewriting on its potting resin surface.
For MOSFET semiconductor chip, the grid of the first of described semiconductor chip extremely MOSFET chip; The source electrode of the second of described semiconductor chip extremely MOSFET chip; The drain electrode of the 3rd of described semiconductor chip extremely MOSFET chip;
For IGBT semiconductor chip, the grid of the first of described semiconductor chip extremely igbt chip; The emitter stage of the second of described semiconductor chip extremely igbt chip; The colelctor electrode of the 3rd of described semiconductor chip extremely igbt chip.
Its further technical scheme is: the material of described row lead wire framework includes copper.
Its further technical scheme is: the material of described metal lead wire includes aluminum or copper or gold.
Its further technical scheme is: the shape of described metal lead wire includes thread or banding.
Its further technical scheme is: the shape of described pin includes the patch-type pin of vertical unbent direct plugging-in pin or bending.
Useful the having the technical effect that of the present invention
One, in lead frame, the first pin and the centre of the 3rd pin it is positioned at due to the second pin, second bonding region on the second pin top can to the abundant extending in both sides around, the area making its second bonding region increases as much as possible, therefore, the wire diameter of the metal lead wire being bonded on the second bonding region can increase, radical can increase, device is made to allow the maximum blowout current passed through to increase, by encapsulating this process, the restriction of chip maximum current is eliminated, make the parameter of device reach the parameter limit of chip itself.
Two, the second bonding region in present configuration can be bonded that wire diameter is bigger, the more metal lead wire of radical, metal lead wire is increased with chip contact area, thus reducing the conducting resistance of device itself, semiconductor device for big electric current, conducting resistance is inherently very low, the conducting resistance reduced further will account for larger proportion in the conducting resistance numerical value of itself, and the lifting for the overall performance of semiconductor device can clearly.
Three, in present configuration in the encapsulating structure of semiconductor device, second pin is between the first pin and the 3rd pin, it is in the underface in slide glass Ji Dao district, the metal lead wire connecting chip and the second pin has the shortest air line distance, so can reduce the resistance of stray inductance that metal lead wire brings and metal lead wire, and lead-in wire needs the angle reversed when can effectively reduce bonding source metal lead-in wire, prevent from metal lead wire to be torn in twist process to pull apart, thus improving stability and the reliability of bonding technology.
Accompanying drawing explanation
Fig. 1-a is MOSFET element profile and the pin electrode schematic diagram of existing tradition TO-220 encapsulating structure.
Fig. 1-b is IGBT device profile and the pin electrode schematic diagram of existing tradition TO-220 encapsulating structure.
Fig. 2-a is the single lead frame front plan view of existing tradition TO-220 encapsulating structure.
Fig. 2-b is the front plan view after the single lead frame metal lead wire bonding of existing tradition TO-220 encapsulating structure.
Fig. 3 is the MOSFET element three-dimensional perspective of the TO-220 encapsulating structure of embodiment 1.
Fig. 4 is the MOSFET element three-dimensional perspective of the TO-263 encapsulating structure of embodiment 2.
Fig. 5 to Figure 13 is that concrete technology step of the present invention implements schematic diagram, wherein:
Fig. 5 is MOSFET chip three-dimensional side view.
Fig. 6 is row lead wire framework front and back top view.
Fig. 7 is the top view in slide glass Ji Dao district after silver coating slurry.
Fig. 8 is the top view in slide glass Ji Dao district after adhesion loading MOSFET chip.
Fig. 9-a is the top view in embodiment 1 after metal lead wire bonding.
Fig. 9-b is the three-dimensional side view in embodiment 1 after metal lead wire bonding.
Figure 10-a is the top view in embodiment 2 after metal lead wire bonding.
Figure 10-b is the three-dimensional side view in embodiment 2 after metal lead wire bonding.
Figure 11-a is the three-dimensional perspective schematic side view that in embodiment 1, potting resin encapsulating is later.
Figure 11-b is the three-dimensional perspective schematic side view that in embodiment 2, potting resin encapsulating is later.
Figure 12 is the three-dimensional perspective in embodiment 1 after MOSFET element pin Trim Molding.
Figure 13 is the three-dimensional perspective in embodiment 2 after MOSFET element pin Trim Molding.
Detailed description of the invention
Below in conjunction with concrete drawings and Examples, the invention will be further described.
Embodiment 1:
As it is shown on figure 3, on the three-dimensional perspective of described semiconductor device, including MOSFET chip, TO-220 lead frame and TO-220 potting resin. Described MOSFET chip has two corresponding interareas, respectively the first interarea and the second interarea, wherein has grid and the source electrode of MOSFET chip on the first interarea, and source region, much larger than area of grid, the second interarea has the drain electrode of MOSFET chip; Described TO-220 lead frame includes the pin area being positioned at slide glass Ji Dao district and lead frame bottom in the middle part of the frame body district on lead frame top, lead frame, and three regions interconnect; Second interarea of described MOSFET chip adheres to and is mounted on above slide glass Ji Dao district; Described pin area comprises the first pin, the second pin and the 3rd pin, and described second pin is positioned at the first pin and the centre of the 3rd pin; Described first pin top is provided with the first bonding region, and described second pin top is provided with the second bonding region, and the area of the second bonding region is much larger than the area of the first bonding region; Described 3rd pin top is connected with slide glass Ji Dao district, and described first pin and the second pin are not connected with slide glass Ji Dao district; Being provided with the grid aluminium wire of 1 5mil diameter between grid and first bonding region of described MOSFET chip, two ends connect at the surface bond of grid and the first bonding region respectively, thus grid and the first pin electricity being connected; Being provided with the source electrode aluminium wire of 4 20mil diameters between source electrode and second bonding region of described MOSFET chip, the two ends of source electrode aluminium wire connect at source electrode and the second bonding region surface bond respectively, thus source electrode and the second pin electricity being connected; The drain electrode of described MOSFET chip is connected with the 3rd pin electricity by slide glass Ji Dao district;MOSFET chip, slide glass Ji Dao district, the first bonding region, the second bonding region, the 3rd pin top, grid aluminium wire and source electrode aluminium wire parcel is covered by described potting resin.
Embodiment 2:
As shown in Figure 4, on the three-dimensional perspective of described semiconductor device, including MOSFET chip, TO-263 lead frame and TO-263 potting resin. Described MOSFET chip has two corresponding interareas, respectively the first interarea and the second interarea, wherein has grid and the source electrode of MOSFET chip on the first interarea, and source region, much larger than area of grid, the second interarea has the drain electrode of MOSFET chip; Described TO-263 lead frame includes the pin area being positioned at slide glass Ji Dao district and lead frame bottom in the middle part of the frame body district on lead frame top, lead frame, and three regions interconnect; Second interarea of described MOSFET chip adheres to and is mounted on above slide glass Ji Dao district; Described pin area comprises the first pin, the second pin and the 3rd pin, and described second pin is positioned at the first pin and the centre of the 3rd pin; Described first pin top is provided with the first bonding region, and described second pin top is provided with the second bonding region, and the area of the second bonding region is much larger than the area of the first bonding region; Described 3rd pin top is connected with slide glass Ji Dao district, and described first pin and the second pin are not connected with slide glass Ji Dao district; Being provided with the grid aluminium wire of 1 5mil diameter between grid and first bonding region of described MOSFET chip, two ends connect at the surface bond of grid and the first bonding region respectively, thus grid and the first pin electricity being connected; Being provided with the source electrode aluminium strip of 2 80mil*8mil between source electrode and second bonding region of described MOSFET chip, the two ends of source electrode aluminium strip connect at source electrode and the second bonding region surface bond respectively, thus by source electrode and the second pin electricity phase; The drain electrode of described MOSFET chip is connected with the 3rd pin electricity by slide glass Ji Dao district; MOSFET chip, slide glass Ji Daoqu, a bonding region, the second bonding region, the 3rd pin top, grid aluminium wire and source electrode aluminium strip parcel is covered by described potting resin.
The above-mentioned MOSFET element through encapsulation, is realized by following processing step:
A. provide and there is the semiconductor MOS fet chip of two opposing main faces, grid and source electrode that described MOSFET chip includes being positioned on the first interarea and be positioned at the drain electrode on the second interarea, as shown in Figure 5;
B. providing TO-220 row lead wire framework, described row lead wire framework comprises multiple TO-220 lead frame connecting arrangement arranged side by side, and wherein each TO-220 lead frame comprises frame body district, slide glass Ji Daoqu, pin area and framework bonding pad; Described frame body district, slide glass Ji Daoqu and pin area constitute the agent structure of single lead frame, and framework bonding pad is for linking together each lead frame; Described pin area comprises the first pin, the second pin and the 3rd pin, described first pin top is provided with the first bonding region, described second pin top is provided with the second bonding region, and described 3rd pin top is connected with corresponding slide glass Ji Dao district, as shown in Figure 6;
When adopting the structure of embodiment 2, the row lead wire framework of described TO-263 is consistent with the row lead wire framework of TO-220;
C. being coated with the silver slurry of liquid in the slide glass Ji Dao district of each lead frame in described TO-220 row lead wire framework, the slide glass Ji Dao district area covered by silver slurry coating is less than the area in whole slide glass Ji Dao district, as shown in Figure 7;
D. being pasted by described MOSFET chip above the slide glass Ji Dao district being placed on above-mentioned coated silver slurry, the second interarea of described MOSFET chip contacts with silver slurry and is connected, as shown in Figure 8;
E. the row lead wire framework of the described MOSFET of being pasted with chip is placed under low temperature nitrogen environment and carries out the solidification that silver is starched;
F. the grid aluminium wire of a 5mil diameter it is bonded between the grid on described MOSFET chip the first interarea and the first bonding region in corresponding lead frame, the two ends of described grid aluminium wire are bonded respectively and are connected to grid and the first bonding region surface, thus grid and the first pin electricity are connected, simultaneously, the source electrode aluminium wire of four 20mil diameters it is bonded between source electrode and the second bonding region in corresponding lead frame on described MOSFET chip the first interarea, the two ends of described source electrode aluminium wire are bonded respectively and are connected to source electrode and the second bonding region surface, thus source electrode and the second pin electricity are connected, as shown in Fig. 9-a and Fig. 9-b,
When adopting the structure of embodiment 2, the source electrode aluminium strip of two 80mil*8mil it is bonded between source electrode and the second bonding region in corresponding lead frame on described MOSFET chip the first interarea, the two ends of described source electrode aluminium strip are bonded respectively and are connected to source electrode and the second bonding region surface, thus source electrode and the second pin electricity are connected, as shown in Figure 10-a and Figure 10-b;
G. described TO-220 row lead wire framework potting resin is carried out injection moulding and encapsulating, described potting resin wraps up the top of the MOSFET chip above slide glass Ji Dao district, grid aluminium wire, source electrode aluminium wire/the first bonding region, the second bonding region and the 3rd pin, as shown in Figure 11-a and Figure 11-b;
H. the described TO-220 row lead wire framework being enclosed with potting resin is packaged the hot setting of resin;
I. by the redundancy potting resin in the region of non-encapsulated resin parcel on described TO-220 row lead wire framework, namely flash is removed;
J. the lead frame of non-encapsulated resin parcel on described TO-220 row lead wire framework being electroplated, the electroplating metal material used includes stannum;
K. each the lead frame passing through encapsulating in described TO-220 row lead wire framework is carried out Trim Molding, the framework bonding pad on lead frame is removed in cutting, several device cells being originally fastened on row lead wire framework are made to be cut into multiple independent TO-220 device cell, as shown in Figure 12 and Fig. 3;
When adopting the structure of embodiment 2, the framework bonding pad on lead frame is removed in cutting, several device cells being originally fastened on row lead wire framework are made to be cut into multiple independent TO-263 device cell, simultaneously, part frame body zone is removed in cutting, and three pins are cut bend fixing so that it is meet the requirement that paster is installed on pcb board of final finished device, as shown in Figure 13 and Fig. 4;
L., above-mentioned each independent device cell carries out specifying the test of parameter, and the device meeting test specification requirement is carried out laser typewriting on its potting resin surface.
The present invention has the semiconductor device of modified model encapsulating structure, for MOSFET element, the source electrode of MOSFET element connects the second pin being positioned in the middle of three pins, the first pin connecting grid and the 3rd pin connecting drain electrode are positioned at both sides, because gate drive current is generally very little compared to source current, gate metal lead-in wire is generally 1 aluminium wire thick for 5mil, therefore the first bonding region area on the first top, pin area need not be very big, again because the 3rd pin connecting slide glass Ji Dao district is positioned at avris, so the second bonding region being positioned at the second pin top can be fully extending transversely to its both sides, as much as possible by the enlarged areas of the second bonding region, so, wire diameter and the radical of the source metal lead-in wire can being bonded above the second bonding region just can promote effectively, thus MOSFET element is allowed to flow through source metal lead-in wire maximum current and blowout current be significantly increased.As shown in Fig. 2-a and Fig. 2-b, compared to original avris that MOSFET element source lead is arranged on three pins, the second bonding region area for being bonded source metal lead-in wire in present configuration increases above 40%, the aluminium wire of 20mil wire diameter can be promoted to by original maximum bondings 3 can be bonded 5, the aluminium strip of 80mil*8mil can be promoted to by original maximum bondings 1 can be bonded 2, and the maximum blowout current amplification of MOSFET element is more than 50%.
MOSFET element for big electric current, generally its chip area is sufficiently large, chip surface is also sufficiently large for the source region being bonded source metal lead-in wire, present configuration solves the bottleneck being bonded source metal lead-in wire on the bonding region of lead frame pin top, therefore, the source metal lead-in wire of more can also be bonded in chip surface source region, so can effectively reduce the contact resistance of source metal lead-in wire and chip, and for the MOSFET element of big electric current, the total device on-resistance of this part contact resistance accounting is of a relatively high, so device architecture of the present invention can be effectively reduced the conducting resistance that device is total, the current characteristics of boost device, reduce the temperature rise in device use procedure.
In present configuration, source metal lead-in wire can be bonded, from chip surface, the second bonding region being connected to the second pin top vertically downward, without being connected to the pin top bonding region of avris as original structure to tilt certain angle bonding, reduce the length of metal lead wire so on the one hand, reduce the stray inductance of lead-in wire, going back high degree avoids the Splitting that metal lead wire causes in bonding process because corner is excessive on the other hand, improves the reliability and stability of encapsulation bonding technology.
Above-described is only the preferred embodiment of the present invention, the invention is not restricted to above example. It is appreciated that the oher improvements and changes that those skilled in the art directly derive without departing from the spirit and concept in the present invention or associate, is all considered as being included within protection scope of the present invention.
Claims (9)
1. a semiconductor device with modified model encapsulating structure, it is characterised in that: include semiconductor chip, lead frame and potting resin;
Described semiconductor chip has the first corresponding interarea and the second interarea, three electrodes respectively first pole of described semiconductor chip, the second pole and the 3rd pole; Described first interarea is provided with the first pole and second pole of semiconductor chip, described second interarea is provided with the 3rd pole of semiconductor chip;
Described lead frame includes the pin area of the frame body district on top, middle slide glass Ji Daoqu and bottom; Described pin area comprise three laid out in parallel and mutually disjunct first pin, the second pin, the 3rd pin, described second pin is positioned in the middle of the first pin and the 3rd pin; Described first pin top is provided with the first bonding region, and the second pin top is provided with the second bonding region, and the area of described second bonding region is more than the area of the first bonding region; Described frame body district is connected with slide glass Ji Dao district, and described slide glass Ji Daoqu is connected with the 3rd pin of pin area; Second interarea of described semiconductor chip adheres to and is mounted on surface, slide glass Ji Dao district;
It is connected by metal lead wire electricity between the first pole and the first bonding region on described semiconductor chip the first interarea, is connected by metal lead wire electricity between the second pole and the second bonding region on described semiconductor chip the first interarea;The 3rd pole on described second interarea is connected with slide glass Ji Dao district and the 3rd pin electricity;
Described potting resin parcel semiconductor chip, the first bonding region, the second bonding region, the 3rd pin top and metal lead wire;
For MOSFET semiconductor chip, the grid of the first of described semiconductor chip extremely MOSFET chip; The source electrode of the second of described semiconductor chip extremely MOSFET chip; The drain electrode of the 3rd of described semiconductor chip extremely MOSFET chip;
For IGBT semiconductor chip, the grid of the first of described semiconductor chip extremely igbt chip; The emitter stage of the second of described semiconductor chip extremely igbt chip; The colelctor electrode of the 3rd of described semiconductor chip extremely igbt chip.
2. there is the semiconductor device of modified model encapsulating structure according to claim 1, it is characterised in that: non-encapsulated resin parcel pin area in the first pin and the spacing of the second pin and the spacing of the second pin and the 3rd pin equal on same cross section.
3. there is the semiconductor device of modified model encapsulating structure according to claim 1, it is characterized in that: the area of described second bonding region is more than 1.1 times of the first bonding region area, the shape of described second bonding region and the shape of the first bonding region include being sequentially connected with, by line segment or curve head and the tail, any enclosed figure formed.
4. there is the semiconductor device of modified model encapsulating structure according to claim 1, it is characterised in that: exchange can be exchanged in the position of described first pin and the 3rd pin.
5. the manufacture method of a semiconductor device with modified model encapsulating structure, it is characterised in that: the method includes:
A. provide and there is the semiconductor chip of two opposing main faces, the first pole that described semiconductor chip includes being positioned on the first interarea and the second pole and the 3rd pole being positioned on the second interarea;
B., row lead wire framework is provided, described row lead wire framework comprises multiple lead frame connecting arrangement arranged side by side, wherein each lead frame comprises frame body district, slide glass Ji Dao district, pin area and framework bonding pad, described frame body district, slide glass Ji Daoqu and pin area constitute the agent structure of single lead frame, framework bonding pad is for linking together each lead frame, described pin area comprises the first pin, second pin and the 3rd pin, described first pin top is provided with the first bonding region, described second pin top is provided with the second bonding region, described 3rd pin top is connected with corresponding slide glass Ji Dao district,
C. being coated with the silver slurry of liquid in the slide glass Ji Dao district of each lead frame in described row lead wire framework, the slide glass Ji Dao district area covered by silver slurry coating is less than the area in whole slide glass Ji Dao district;
D., by described surface mounting of semiconductor chips on the slide glass Ji Dao district of above-mentioned coated silver slurry, the second interarea of described chip contacts with silver slurry and is connected;
E. the described row lead wire framework being pasted with chip is placed under low temperature nitrogen environment and carries out the solidification that silver is starched;
F. the first surface, pole on described chip the first interarea and the first bonding region surface bond metal lead wire in corresponding lead frame, thus being connected the first pole with the first pin electricity; The second surface, pole on described semiconductor chip the first interarea and the second bonding region surface bond metal lead wire in corresponding lead frame, thus being connected the second pole with the second pin electricity;
G. described row lead wire framework potting resin being carried out injection moulding and encapsulating, described potting resin wraps up the top of the semiconductor chip above slide glass Ji Dao district, metal lead wire, the first bonding region, the second bonding region and the 3rd pin;
H. the described row lead wire framework being enclosed with potting resin is packaged the hot setting of resin;
I. by the redundancy potting resin in the region of non-encapsulated resin parcel on described row lead wire framework, namely flash is removed;
J. the lead frame of non-encapsulated resin parcel on described row lead wire framework being electroplated, the metal material that described plating uses includes stannum;
K., the lead frame that in described row lead wire framework each passes through encapsulating carries out Trim Molding, the framework bonding pad on lead frame is removed in cutting, several device cells being originally fastened on row lead wire framework are made to be cut into multiple independent device cell, simultaneously, as required the first pin of each device, the second pin and the 3rd pin are bent to the shape specified so that it is pin shapes is suitable for final finished device installation requirements of straight cutting or paster on pcb board;
L., above-mentioned each independent device cell carries out specifying the test of parameter, and the device meeting test specification requirement is carried out laser typewriting on its potting resin surface;
For MOSFET semiconductor chip, the grid of the first of described semiconductor chip extremely MOSFET chip; The source electrode of the second of described semiconductor chip extremely MOSFET chip; The drain electrode of the 3rd of described semiconductor chip extremely MOSFET chip;
For IGBT semiconductor chip, the grid of the first of described semiconductor chip extremely igbt chip; The emitter stage of the second of described semiconductor chip extremely igbt chip; The colelctor electrode of the 3rd of described semiconductor chip extremely igbt chip.
6. there is the manufacture method of the semiconductor device of modified model encapsulating structure according to claim 5, it is characterised in that: the material of described row lead wire framework includes copper.
7. there is the manufacture method of the semiconductor device of modified model encapsulating structure according to claim 5, it is characterised in that: the material of described metal lead wire includes aluminum or copper or gold.
8. there is the manufacture method of the semiconductor device of modified model encapsulating structure according to claim 5, it is characterised in that: the shape of described metal lead wire includes thread or banding.
9. there is the manufacture method of the semiconductor device of modified model encapsulating structure according to claim 5, it is characterised in that: the shape of described pin includes the patch-type pin of vertical unbent direct plugging-in pin or bending.
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| CN111081671A (en) * | 2018-10-19 | 2020-04-28 | 珠海格力电器股份有限公司 | Low-stress semiconductor chip fixing structure, semiconductor device and manufacturing method thereof |
| KR20200051303A (en) * | 2018-11-05 | 2020-05-13 | 에스케이하이닉스 주식회사 | Termination circuit and semiconductor apparatus using the same |
| CN110010577A (en) * | 2019-04-08 | 2019-07-12 | 深圳市鹏源电子有限公司 | Direct insertion power device, semiconductor subassembly, In-wheel motor driving device or bus drive and new-energy automobile |
| CN109967872B (en) * | 2019-04-23 | 2021-05-07 | 苏州福唐智能科技有限公司 | Semiconductor laser welding method and welding structure thereof |
| CN110164831A (en) * | 2019-05-31 | 2019-08-23 | 无锡电基集成科技有限公司 | Conducive to the high-current semiconductor power device and its manufacturing method of welding |
| CN110581105B (en) * | 2019-07-30 | 2020-12-04 | 泉州台商投资区嘉尚网络科技有限公司 | Metal oxide semiconductor bonding light-blocking sliding-preventing field effect transistor |
| CN112885804B (en) * | 2021-03-08 | 2023-09-05 | 重庆平伟实业股份有限公司 | Surface mount photovoltaic bypass module and packaging process thereof |
| CN114760756B (en) * | 2022-06-14 | 2022-09-06 | 四川明泰微电子有限公司 | High-frequency integrated packaging module and packaging method thereof |
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