CN103812643A

CN103812643A - ARM-based AXI (advanced extensible interface) SHA3 (secure hash algorithm 3) IP (internet protocol) core design

Info

Publication number: CN103812643A
Application number: CN201410039933.1A
Authority: CN
Inventors: 韩永飞; 王宏金
Original assignee: XIAMEN DENSE PRINCIPAL INFORMATION TECHNOLOGY CO LTD
Current assignee: XIAMEN DENSE PRINCIPAL INFORMATION TECHNOLOGY CO LTD
Priority date: 2014-01-26
Filing date: 2014-01-26
Publication date: 2014-05-21

Abstract

The invention belongs to ARM-based AXI (advanced extensible interface) SHA3 (secure hash algorithm 3) IP (internet protocol) core design. An SHA3 IP core is designed according to characteristics of a Keccak module and an AXI Slave module, an AXI module is connected with the Keccak module, and the IP core has the advantages of low power consumption and less resource occupation and can be conveniently integrated into SoC design.

Description

The SHA3 IP kernel design of the AXI interface based on ARM

Technical field:

The present invention is directed to the feature of Keccak module and AXI Slave module, design state machine, realize reading out data from the RAM of AXI Slave and given Keccak processing, then the result of handling has been write in the RAM of AXI Slave, finally realized the Keccak IP design with AXI interface.

Background technology:

SHA (Secure Hash Algorithm, SHA) be a kind of DEA of being issued in 1993 by National Institute of Standards and Technology (National Institute of Standards and Technology, NIST).Its main thought is the eap-message digest that the message maps of variable-length is become to regular length, is widely used in the information security fields [1] such as cryptoguard, message discriminating, data integrity checking and digital signature.AXI interface is the up-to-date bus of ARM company, and this bus possesses high bandwidth, low delay, and the features such as flexible design, have become the most widely used on-chip bus standard [2] in SoC at present.Herein design the SHA3IP core based on AXI interface based on Keccak project [3] and the AXI project [4] of increasing income of increasing income.The design has low-power consumption, and the feature that resource occupation is less is applicable in the SoC design of portable equipment.

Summary of the invention:

1, realized being connected of AXI module and Keccak module, be convenient to designer and control and access Keccak module with unified interface.

2, for the independent operation of convenient read-write, the design has splitted into two a RAM in AXI Slave, and one of them is responsible for cushioning the output of AXI and the input of Keccak, and another one is responsible for the input of the AXI of the output that cushions Keccak.

Accompanying drawing explanation:

Fig. 1: project entirety interface schema

Fig. 2: local state figure

Embodiment:

1, read-write operation step is as follows:

(1) reset initialization enters IDLE state, waits for that AXI writes data to RAM_A and completes with Keccak and be ready to input data.

(2) carry out read states, what state machine control generated RAM_A reads address and control signal, data in RAM_A are read out successively and send a Keccak to process, if Keccak module occurs that busy state cannot receive data in the process of reading, enter Wait state, wait for that after Keccak is ready to, continuing reading out data send a Keccak again.After data in RAM_A have all read, state machine again enters Wait state and waits for that data processing finishes.

(3) enter WR state, the input that state machine calculated address and control signal are handled Keccak is written in RAM_B and cushions, in data writing, when the data processed if there is Keccak are also unripe, enter Wait state, wait for after data processing well and continue again data writing.

2, for convenience of the read-write of data, we have also defined the function of RAM_A and RAM_B home address:

When user needs deal with data, first needing data length to be processed to write the 0x1 address of RAM_A, then data to be processed need are started to write successively RAM_A from 0x02 address, after data write, write 0x01 toward 0x00, represent that data have write end and allowed state machine enter RD state.State machine first reads the length of input data in the time of RD state from 0x01, then generate control signal and address, starts reading out data give Keccak processing from 0x02 address.When detecting, state machine plays card after Keccak handles data, state machine enters WR state, first the data length of handling is write to the 0x01 address of RAM_B, then generate the data of control signal and address Keccak being handled and start to write successively RAM_B from 0x02 address, after data write, 0x00 address is write to 0x01, represent that these data of handling are effective.In the time that user detects that the 0x00 address of RAM_B is 0x01, start to read from 0x02 address the data of handling, after having read, RAM_A and RAM_B are resetted, the value of all addresses is all set to 0x00, then wait for data processing next time.

Claims

1. utilize the Keccak module of ARM and the feature of AXI Slave module design SHA3IP core, realize being connected of AXI module and Keccak module, this IP kernel has low-power consumption, and the feature that resource occupation is less can easily be incorporated into during SoC designs.

2. realize following functions based on AXI interface SHA3IP core design: (1) has realized being connected of AXI module and Keccak module, control and access Keccak module with unified interface.(2) realized reading out data from the RAM of AXI Slave and given Keccak processing, and then the result of handling has been write in the RAM of AXI Slave.