CN103795395A - Analog circuit device for anti-shake time slot synchronization - Google Patents
Analog circuit device for anti-shake time slot synchronization Download PDFInfo
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Abstract
The invention provides an analog circuit device for anti-shake time slot synchronization. The device comprises a coupling circuit, a detecting circuit, a waveshaping circuit, a hysteresis comparison circuit and a voltage controlled attenuator, wherein the coupling circuit is used for coupling radio-frequency signals from a radio-frequency closed circuit to the detecting circuit, the detecting circuit is used for converting the radio-frequency signals to voltage time-domain signals and then sending the voltage time-domain signals to the waveshaping circuit, the waveshaping circuit is used for converting the voltage time-domain signals to triangular wave voltage time-domain signals and sending the triangular wave voltage time-domain signals to the hysteresis comparison circuit, the hysteresis comparison circuit is used for outputting a comparison result to the voltage controlled attenuator to control the voltage controlled attenuator to conduct attenuation operation when the triangular wave voltage time-domain signals are higher than a set threshold value. According to the analog circuit device, synchronization of anti-shake time slot signals is achieved through the hardware circuit only; due to the fact that the hardware circuit is better than the digital method in real-time performance, the analog circuit device not only can prevent shaking, but also is high in response speed and good in real-time performance.
Description
Technical field
The present invention relates to Technology of Time Slot field, particularly a kind of mould electric installation for anti-shake slot synchronization.
Background technology
In prior art, in order to guarantee that reception and the first frame that analog to digital converter ADC is good do not lose, require has certain signal to noise ratio in the time guaranteeing the lower signal of received power, and in the time of the stronger signal of received power, can not produce again too large distorted signal.Therefore, require the power of ADC input signal to be no more than-20dBm.But for received signal strength indicator device (RSSI, Received Signal Strength Indicator) easily calculates, so electrically controlled attenuator control only has two grades, the thresholding that exceedes setting is opened attenuator, otherwise turns off attenuator.
At present, in prior art, be all to realize synchronous time domain signal by digital form, for example synchronization module based on FPGA.Coupling needs synchronous signal, after ADC conversion, sends into FPGA, and FPGA carries out processing such as the collection of data, data-optimized, data demodulates and carries out slot synchronization afterwards again.
But the shortcoming that digital form carries out slot synchronization is: anti-shake property is poor; And react slow, need to carry out after software calculates judgement moving again, real-time is poor.The poor direct result of real-time can make ADC obliterated data exactly.Therefore, need to provide a kind of device of anti-shake slot synchronization, real-time is higher, prevents the loss of data.
Summary of the invention
The technical problem to be solved in the present invention is to provide a kind of mould electric installation for anti-shake slot synchronization, can carry out quickly slot synchronization, prevents the loss of data.
The embodiment of the present invention provides a kind of mould electric installation of anti-shake slot synchronization, comprising: coupling circuit, testing circuit, shaping circuit, hysteresis comparison circuit and voltage-controlled attenuator;
Described coupling circuit, for the radiofrequency signal that is coupled from radio frequency path to described testing circuit;
Described testing circuit, sends to described shaping circuit for described radiofrequency signal is converted to voltage time-domain signal;
Described shaping circuit, sends to described hysteresis comparison circuit for described voltage time-domain signal is converted to triangle wave voltage time-domain signal;
Described hysteresis comparison circuit, for more described triangle wave voltage time-domain signal, higher than setting when threshold value, output comparative result is given described voltage-controlled attenuator, controls voltage-controlled attenuator and carries out decay work.
Preferably, also comprise: filter circuit;
Described filter circuit is connected to the output of described testing circuit;
Described filter circuit, for carrying out the voltage time-domain signal of described testing circuit output to send to described shaping circuit after filtering.
Preferably, described filter circuit is RC filter circuit, comprising: the 11 resistance and the 11 electric capacity;
One end of described the 11 resistance connects the output of described testing circuit, the other end ground connection of described the 11 resistance;
One end of described the 11 electric capacity connects the output of described testing circuit, the other end ground connection of described the 11 electric capacity.
Preferably, described shaping circuit comprises: the first electric capacity, the second electric capacity, the first resistance, the second resistance and operational amplifier;
The first end of described the first electric capacity connects the output of described testing circuit, and the second end of described the first electric capacity connects the first end of the second electric capacity, and the second end of the second electric capacity connects the normal phase input end of described operational amplifier;
One end of described the first resistance connects the normal phase input end of described operational amplifier, the other end ground connection of described the first resistance;
One end of described the second resistance connects the inverting input of described operational amplifier, and the other end of described the second resistance connects the second end of described the first electric capacity;
The inverting input of the output concatenation operation amplifier of described operational amplifier.
Preferably, described shaping circuit also comprises: the 3rd electric capacity and the 4th electric capacity;
One end of described the 3rd electric capacity connects the working power end of described operational amplifier, the other end ground connection of described the 3rd electric capacity;
One end of described the 4th electric capacity connects the working power end of described operational amplifier, the other end ground connection of described the 4th electric capacity.
Preferably, described hysteresis comparison circuit comprises: the 3rd resistance, the 4th resistance, the 5th resistance and hysteresis loop comparator;
One end of described the 4th resistance connects the output of described shaping circuit, and the other end of described the 4th resistance connects the normal phase input end of described hysteresis loop comparator;
The normal phase input end of described hysteresis loop comparator is by described the 5th grounding through resistance;
The output of described hysteresis loop comparator connects the normal phase input end of described hysteresis loop comparator by described the 3rd resistance;
The inverting input of described hysteresis loop comparator connects the working power end of hysteresis loop comparator by adjustable resistance.
Preferably, described hysteresis comparison circuit also comprises: the 5th electric capacity and the 6th electric capacity;
One end of described the 5th electric capacity connects the working power end of described hysteresis loop comparator, the other end ground connection of described the 5th electric capacity;
One end of described the 6th electric capacity connects the working power end of described hysteresis loop comparator, the other end ground connection of described the 6th electric capacity.
Preferably, described setting threshold value comprises threshold ones and wealthy family's limit value;
Described threshold ones is 0.05V, and described wealthy family limit value is 0.85V.
Preferably, described the 3rd resistance is 60 kilohms;
Described the 4th resistance is 15 kilohms;
Described the 5th resistance is 90 kilohms.
Preferably, described coupling circuit comprises coupling capacitance;
One end of described coupling capacitance connects described radio frequency path, and the other end of described coupling capacitance connects the input of described testing circuit.
Compared with prior art, the present invention has the following advantages:
The mould electric installation for anti-shake slot synchronization that the present embodiment provides, by coupling circuit from the radio frequency path radiofrequency signal that is coupled, the radiofrequency signal of coupling is converted to voltage time-domain signal to be processed, for the mistake that prevents that shake from causing, voltage time-domain signal is changed again for triangle wave voltage time-domain signal, by hysteresis comparison circuit, triangle wave voltage time-domain signal is compared with setting threshold value, whether work thereby control voltage-controlled attenuator.This mould electric installation that the embodiment of the present invention provides has been realized the synchronous of anti-shake time slot signal by hardware circuit completely, because hardware circuit itself is just higher than the real-time of digital form, therefore, mould electric installation provided by the invention not only can be anti-shake, and reaction speed is fast, real-time is high.
Accompanying drawing explanation
In order to be illustrated more clearly in the embodiment of the present invention or technical scheme of the prior art, to the accompanying drawing of required use in embodiment or description of the Prior Art be briefly described below, apparently, accompanying drawing in the following describes is only some embodiments of the present invention, for those of ordinary skills, do not paying under the prerequisite of creative work, can also obtain according to these accompanying drawings other accompanying drawing.
Fig. 1 is mould electric installation embodiment mono-schematic diagram for anti-shake slot synchronization provided by the invention;
Fig. 2 is mould electric installation embodiment bis-schematic diagrames for anti-shake slot synchronization provided by the invention;
Fig. 3 is filter circuit schematic diagram provided by the invention;
Fig. 4 is shaping circuit schematic diagram provided by the invention;
Fig. 5 is hysteresis comparison circuit schematic diagram provided by the invention.
Embodiment
Below in conjunction with the accompanying drawing in the embodiment of the present invention, the technical scheme in the embodiment of the present invention is clearly and completely described, obviously, described embodiment is only the present invention's part embodiment, rather than whole embodiment.Based on the embodiment in the present invention, those of ordinary skills, not making the every other embodiment obtaining under creative work prerequisite, belong to the scope of protection of the invention.
For above-mentioned purpose of the present invention, feature and advantage can be become apparent more, below in conjunction with accompanying drawing, the specific embodiment of the present invention is described in detail.
Embodiment mono-:
Referring to Fig. 1, this figure is mould electric installation embodiment mono-schematic diagram for anti-shake slot synchronization provided by the invention.
It should be noted that, before the mould electric installation of the anti-shake slot synchronization that the embodiment of the present invention provides is applicable to ADC, that is, the signal of mould electric installation output inputs to ADC.
The present embodiment provides a kind of mould electric installation of anti-shake slot synchronization, comprising: coupling circuit 100, testing circuit 200, shaping circuit 300, hysteresis comparison circuit 400 and voltage-controlled attenuator 500;
It should be noted that, the radiofrequency signal in radio communication is time slot signal.
Described coupling circuit 100, for the radiofrequency signal that is coupled from radio frequency path to described testing circuit 200;
It should be noted that, the coupling circuit 100 in the present embodiment can be realized by coupling capacitance.
One end of described coupling capacitance connects described radio frequency path, and the other end of described coupling capacitance connects the input of described testing circuit 200.
It should be noted that, described radiofrequency signal is input to voltage-controlled attenuator 500.The effect of voltage-controlled attenuator 500 is for laggard line output that radiofrequency signal is decayed, and for example, the frequency of the radiofrequency signal of voltage-controlled attenuator 500 inputs is 0dB, and the frequency of radiofrequency signal after voltage-controlled attenuator 500 output is-10dB.
Described testing circuit 200, sends to described shaping circuit 300 for described radiofrequency signal being converted to voltage time-domain signal;
Because radiofrequency signal is power signal, therefore, need testing circuit 200 that power signal is converted to voltage time-domain signal.
Described shaping circuit 300, sends to described hysteresis comparison circuit 400 for described voltage time-domain signal is converted to triangle wave voltage time-domain signal;
The voltage time-domain signal of exporting due to testing circuit 200 easily produces shake in setting threshold value, and voltage time-domain signal is along with the different jitter range that produce of complementary cumulative distribution function (CCDF, Complementary Cumulative Distribution Function) are also different.The error producing in order to eliminate shake, the voltage time-domain signal of in the present invention, testing circuit 200 being exported is converted to triangle wave voltage time-domain signal by shaping circuit 300.
The triangle wave voltage time-domain signal that export in described shaping loop 300 can provide highs and lows for hysteresis comparison circuit 400, and time interval between highs and lows is the same with the one-period time of voltage time-domain signal.
Particularly, the output of triangle wave voltage time-domain signal can be realized by differential circuit in described shaping loop 300, and time slot waveform occurs that the high point of moment rising edge is become the high point of triangular wave by differential, and time slot waveform moment trailing edge is become the low spot of triangular wave by differential.
Described hysteresis comparison circuit 400, for described triangle wave voltage time-domain signal is compared with setting threshold value, whether output comparative result is given described voltage-controlled attenuator 500, work to control voltage-controlled attenuator 500.
It should be noted that, in the present invention, utilize hysteresis comparison circuit 400 that triangle wave voltage time-domain signal and setting threshold value are compared, and there is no a general common comparator of application, the sensitivity in order to prevent that comparator is too high, because too high output and the multiple triggering voltage-controlled attenuator of easily making the mistake of comparator sensitivity.
The effect of this hysteresis comparison circuit 400 is that the triangle wave voltage time-domain signal that input is received compares with setting threshold value, determines whether output voltage time-domain signal according to comparative structure.For example, when triangle wave voltage time-domain signal is higher than setting when threshold value, hysteresis comparison circuit 400 is exported high level signal to voltage-controlled attenuator 500, and voltage-controlled attenuator 500 is opened and carried out work, output after the radiofrequency signal of voltage-controlled attenuator 500 inputs is decayed.When triangle wave voltage time-domain signal is lower than setting when threshold value, hysteresis comparison circuit 400 output low level signals are to voltage-controlled attenuator 500, voltage-controlled attenuator 500 is not opened, do not carry out decay work, now voltage-controlled attenuator 500 is exported the original signal of radiofrequency signal, and does not decay, for example, the radiofrequency signal of voltage-controlled attenuator 500 inputs is 0dB, and the radiofrequency signal of output is still 0dB.
The effect of described voltage-controlled attenuator 500 is for radiofrequency signal is decayed and Domain Synchronous.
The mould electric installation for anti-shake slot synchronization that the present embodiment provides, by coupling circuit from the radio frequency path radiofrequency signal that is coupled, the radiofrequency signal of coupling is converted to voltage time-domain signal to be processed, for the mistake that prevents that shake from causing, voltage time-domain signal is changed again for triangle wave voltage time-domain signal, by hysteresis comparison circuit, triangle wave voltage time-domain signal is compared with setting threshold value, whether work thereby control voltage-controlled attenuator.This mould electric installation that the embodiment of the present invention provides has been realized the synchronous of anti-shake time slot signal by hardware circuit completely, because hardware circuit itself is just higher than the real-time of digital form, therefore, mould electric installation provided by the invention not only can be anti-shake, and reaction speed is fast, real-time is high.
Embodiment bis-:
Referring to Fig. 2, this figure is mould electric installation embodiment bis-schematic diagrames for anti-shake slot synchronization provided by the invention.
It should be noted that, the mould electric installation that the present embodiment provides is compared with embodiment, and difference is to have increased filter circuit 600.
Described filter circuit 600 is connected to the output of described testing circuit 200;
Described filter circuit 600, carries out sending to described shaping circuit 300 after filtering for the voltage time-domain signal that described testing circuit 200 is exported.
Because the voltage dithering of time slot signal is except the CCDF impact of power supply and signal, the ripple of testing circuit output is also a key factor that affects voltage dithering, therefore, need the ripple of voltage time-domain signal of testing circuit output the smaller the better, therefore, in the present embodiment, be provided with filter circuit 600, by filter circuit 600, ripple filtering exported to shaping circuit 300 more later.
Embodiment tri-:
Referring to Fig. 3, this figure is filter circuit schematic diagram provided by the invention.
It should be noted that, the filter circuit that the embodiment of the present invention provides is RC filter circuit 600, comprising: the 11 resistance R the 11 and the 11 capacitor C 11;
One end of described the 11 resistance R 11 connects the output of described testing circuit 200, the other end ground connection of described the 11 resistance R 11;
One end of described the 11 capacitor C 11 connects the output of described testing circuit 200, the other end ground connection of described the 11 capacitor C 11.
Embodiment tetra-:
Referring to Fig. 4, this figure is shaping circuit schematic diagram provided by the invention.
The mould electric installation of the anti-shake slot synchronization that the present embodiment provides, described shaping circuit comprises: the first capacitor C 1, the second capacitor C 2, the first resistance R 1, the second resistance R 2 and operational amplifier U1;
The first end of described the first capacitor C 1 connects the output (being the Vin in Fig. 4) of described testing circuit, the second end of described the first capacitor C 1 connects the first end of the second capacitor C 2, and the second end of the second capacitor C 2 connects the normal phase input end of described operational amplifier U1;
One end of described the first resistance R 1 connects the normal phase input end of described operational amplifier U1, the other end ground connection of described the first resistance R 1;
One end of described the second resistance R 2 connects the inverting input of described operational amplifier U1, and the other end of described the second resistance R 2 connects the second end of described the first capacitor C 1;
The inverting input of the output concatenation operation amplifier U1 of described operational amplifier U1.
Be that the cycle of signal frame is as 56.7ms below take Tetra signal frame length as 56.7ms(), the frequency of signal frame is 17.63668Hz, Q-Value in Electric Circuit is 0.707 to introduce the value of the parameters in shaping circuit for example.
F=1/0.0567*0.707=12.47102(Hz); F is the signal frame frequency after normalization;
Select the value of C1 and C2 to be 0.4uf;
It should be noted that, the capacitance of C1 and C2 can be selected as required, is only to calculate as an example of 0.4uF example in the present embodiment.
The computational methods of input impedance Ro of moving amplifier are as follows:
Ro=1/ (2 π C1*F)=1/[2*3.141593*0.4 (E-6) * 12.471] ≈ 31904.96=31.91 (kilohm);
It should be noted that, E-6 is expressed as 10
-6; 0.4uf*E=0.0000004pf.
R1=2Q*Ro=2*0.707*31.91=45.11 (kilohm);
R2=Ro/2Q=31.91/ (2*0.707)=22.56 (kilohm);
Can find out, C1, C2, R1 and the R2 in shaping circuit is combined into differential circuit and removes the circuit of the high-frequency harmonic of stack.
It should be noted that, the shaping circuit that the present embodiment provides also comprises: the 3rd capacitor C 3 and the 4th capacitor C 4; The effect of C3 and C4 is in order to carry out filtering to the working power of operational amplifier U1.
One end of described the 3rd capacitor C 3 connects the working power end of described operational amplifier U1, the other end ground connection of described the 3rd capacitor C 3;
One end of described the 4th capacitor C 4 connects the working power end of described operational amplifier U1, the other end ground connection of described the 4th capacitor C 4.
The error producing in order to eliminate shake, is converted to triangle wave voltage time-domain signal by the voltage time-domain signal of testing circuit output by shaping circuit in the present invention.
Embodiment five:
Referring to Fig. 5, this figure is hysteresis comparison circuit schematic diagram provided by the invention.
The mould electric installation of the anti-shake slot synchronization that the present embodiment provides, described hysteresis comparison circuit comprises: the 3rd resistance R 3, the 4th resistance R 4, the 5th resistance R 5 and hysteresis loop comparator U2;
One end of described the 4th resistance R 4 connects the output (being the Vin in Fig. 5) of described shaping circuit, and the other end of described the 4th resistance R 4 connects the normal phase input end (being IN+) of described hysteresis loop comparator U2;
The normal phase input end of described hysteresis loop comparator U2 is by described the 5th resistance R 5 ground connection;
The output (being OUT) of described hysteresis loop comparator U2 connects the normal phase input end of described hysteresis loop comparator U2 by described the 3rd resistance R 3;
The inverting input (being IN-) of described hysteresis loop comparator U2 connects the working power end of hysteresis loop comparator U2 by adjustable resistance RP, in Fig. 5, the working power voltage of hysteresis loop comparator U2 is+3V.
Hysteresis loop comparator U2 in the present embodiment can adopt MAX985 as master chip.
It should be noted that, the setting threshold value in hysteresis comparison circuit comprises threshold ones and wealthy family's limit value.For example, when 0dB corresponding voltage 1V, can set the limit value 0.85V of the wealthy family threshold ones 0.05V of hysteresis loop comparator, this choosing value can be selected according to concrete signal, needn't limit, because the operation principle of hysteresis loop comparator is well known in the art.For example, wealthy family's limit value can be selected 0.8V, and threshold ones can be selected 0.1V.As long as guarantee that low threshold is less than wealthy family limit value, and wealthy family's limit value be less than voltage corresponding to the performance number of needs get final product (for example 0dB corresponding be 1V, wealthy family's limit value is less than 1V).In practical application,
Can select+3V of the working power of master chip, Vref(reference voltage)=0.6V, VL(threshold ones)=0.05, VH(wealthy family limit value)=0.85, crucial resistance configuration is as follows:
The biasing Bias electric current of the both positive and negative polarity of input hysteresis loop comparator U2 is less than 10nA, is not 10nA through the electric current of resistance, and through 100 times of later hypothesis expansions, the electric current I r3 of process R3 is at least 1uA, the error causing to reduce Bias electric current.
R3=Vref/Ir3=0.6/1 (E-6)=600 (kilohm);
R3=(Vcc-Vref)/Ir3=(3.2-0.6)/1 (E-6)=2600000=2600 (kilohm);
Being more than two kinds of modes of calculating R3, is respectively the R3 that VCC calculates to the voltage between Vref, and one is the R3 that Vref calculates to the voltage between ground.
R3 gets the minimum value in above two kinds of account forms, select R3=600 (kilohm).
R4=R3*[(VH-VL)/Vcc]=600* ((0.85-0.05)/3.2)=150 (kilohm).
R5=1/ ((VH/ (Vref*R1))-1/R1-1/R3)=1/ ((0.85/ (0.6*150))-1/150-1/600)=900 (kilohm).
Due to the R3 calculating, R4 and R5 value too large, therefore, unified dwindle 10 times, last resistance configuration is: R4=15 (kilohm); R5=90 (kilohm); R3=60 (kilohm).
In the present embodiment, be to calculate R3, R4 and R5 take the voltage and current of concrete example as example, be understandable that, those skilled in the art can design other numerical value according to actual needs.In the present embodiment, dwindle 10 times as example take resistance unification, be understandable that, also can unify to dwindle 100 times, for example last resistance configuration is: R4=1.5 (kilohm); R5=9 (kilohm); R3=6 (kilohm).
In addition, the hysteresis comparison circuit that the present embodiment provides also comprises: the 5th capacitor C 5 and the 6th capacitor C 6;
One end of described the 5th capacitor C 5 connects the working power end of described hysteresis loop comparator U2, the other end ground connection of described the 5th capacitor C 5;
One end of described the 6th capacitor C 6 connects the working power end of described hysteresis loop comparator U2, the other end ground connection of described the 6th capacitor C 6.
It should be noted that, the effect of C5 and C6 is to carry out filtering for the working power of hysteresis loop comparator.
In sum, the mould electric installation of the anti-shake slot synchronization that the above embodiment of the present invention provides, realizes the anti-shake synchronous of time slot signal by hardware completely, high more a lot of than the real-time realizing with digital form in prior art, and simple structure, price is also much lower than digital form.If, with integrated chips such as FPGA, ADC, clock generators, price is very high in prior art.
The above, be only preferred embodiment of the present invention, not the present invention done to any pro forma restriction.Although the present invention discloses as above with preferred embodiment, but not in order to limit the present invention.Any those of ordinary skill in the art, do not departing from technical solution of the present invention scope situation, all can utilize method and the technology contents of above-mentioned announcement to make many possible variations and modification to technical solution of the present invention, or be revised as the equivalent embodiment of equivalent variations.Therefore, every content that does not depart from technical solution of the present invention,, all still belongs in the scope of technical solution of the present invention protection any simple modification made for any of the above embodiments, equivalent variations and modification according to technical spirit of the present invention.
Claims (10)
1. a mould electric installation for anti-shake slot synchronization, is characterized in that, comprising: coupling circuit, testing circuit, shaping circuit, hysteresis comparison circuit and voltage-controlled attenuator;
Described coupling circuit, for the radiofrequency signal that is coupled from radio frequency path to described testing circuit;
Described testing circuit, sends to described shaping circuit for described radiofrequency signal is converted to voltage time-domain signal;
Described shaping circuit, sends to described hysteresis comparison circuit for described voltage time-domain signal is converted to triangle wave voltage time-domain signal;
Described hysteresis comparison circuit, for more described triangle wave voltage time-domain signal, higher than setting when threshold value, output comparative result is given described voltage-controlled attenuator, controls voltage-controlled attenuator and carries out decay work.
2. the mould electric installation of anti-shake slot synchronization according to claim 1, is characterized in that, also comprises: filter circuit;
Described filter circuit is connected to the output of described testing circuit;
Described filter circuit, for carrying out the voltage time-domain signal of described testing circuit output to send to described shaping circuit after filtering.
3. the mould electric installation of anti-shake slot synchronization according to claim 2, is characterized in that, described filter circuit is RC filter circuit, comprising: the 11 resistance and the 11 electric capacity;
One end of described the 11 resistance connects the output of described testing circuit, the other end ground connection of described the 11 resistance;
One end of described the 11 electric capacity connects the output of described testing circuit, the other end ground connection of described the 11 electric capacity.
4. the mould electric installation of anti-shake slot synchronization according to claim 1, is characterized in that, described shaping circuit comprises: the first electric capacity, the second electric capacity, the first resistance, the second resistance and operational amplifier;
The first end of described the first electric capacity connects the output of described testing circuit, and the second end of described the first electric capacity connects the first end of the second electric capacity, and the second end of the second electric capacity connects the normal phase input end of described operational amplifier;
One end of described the first resistance connects the normal phase input end of described operational amplifier, the other end ground connection of described the first resistance;
One end of described the second resistance connects the inverting input of described operational amplifier, and the other end of described the second resistance connects the second end of described the first electric capacity;
The inverting input of the output concatenation operation amplifier of described operational amplifier.
5. the mould electric installation of anti-shake slot synchronization according to claim 4, is characterized in that, described shaping circuit also comprises: the 3rd electric capacity and the 4th electric capacity;
One end of described the 3rd electric capacity connects the working power end of described operational amplifier, the other end ground connection of described the 3rd electric capacity;
One end of described the 4th electric capacity connects the working power end of described operational amplifier, the other end ground connection of described the 4th electric capacity.
6. the mould electric installation of anti-shake slot synchronization according to claim 1, is characterized in that, described hysteresis comparison circuit comprises: the 3rd resistance, the 4th resistance, the 5th resistance and hysteresis loop comparator;
One end of described the 4th resistance connects the output of described shaping circuit, and the other end of described the 4th resistance connects the normal phase input end of described hysteresis loop comparator;
The normal phase input end of described hysteresis loop comparator is by described the 5th grounding through resistance;
The output of described hysteresis loop comparator connects the normal phase input end of described hysteresis loop comparator by described the 3rd resistance;
The inverting input of described hysteresis loop comparator connects the working power end of hysteresis loop comparator by adjustable resistance.
7. the mould electric installation of anti-shake slot synchronization according to claim 6, is characterized in that, described hysteresis comparison circuit also comprises: the 5th electric capacity and the 6th electric capacity;
One end of described the 5th electric capacity connects the working power end of described hysteresis loop comparator, the other end ground connection of described the 5th electric capacity;
One end of described the 6th electric capacity connects the working power end of described hysteresis loop comparator, the other end ground connection of described the 6th electric capacity.
8. the mould electric installation of anti-shake slot synchronization according to claim 6, is characterized in that, described setting threshold value comprises threshold ones and wealthy family's limit value;
Described threshold ones is 0.05V, and described wealthy family limit value is 0.85V.
9. the mould electric installation of anti-shake slot synchronization according to claim 6, is characterized in that, described the 3rd resistance is 60 kilohms;
Described the 4th resistance is 15 kilohms;
Described the 5th resistance is 90 kilohms.
10. the mould electric installation of anti-shake slot synchronization according to claim 1, is characterized in that, described coupling circuit comprises coupling capacitance;
One end of described coupling capacitance connects described radio frequency path, and the other end of described coupling capacitance connects the input of described testing circuit.
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| CN106877839A (en) * | 2017-02-23 | 2017-06-20 | 中国电子科技集团公司第二十四研究所 | Software hysteresis low pass filter and its method of work |
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| CN103795395B (en) | 2016-05-04 |
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