CN103777732A - Connector control method, connector and storage storing device - Google Patents
Connector control method, connector and storage storing device Download PDFInfo
- Publication number
- CN103777732A CN103777732A CN201210405185.5A CN201210405185A CN103777732A CN 103777732 A CN103777732 A CN 103777732A CN 201210405185 A CN201210405185 A CN 201210405185A CN 103777732 A CN103777732 A CN 103777732A
- Authority
- CN
- China
- Prior art keywords
- signal
- detector
- burst
- squelch
- signal string
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Images
Classifications
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
- Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management
Landscapes
- Mobile Radio Communication Systems (AREA)
- Noise Elimination (AREA)
Abstract
Provided are a connector control method, a storage storing device and a connector. The control method includes receiving a first signal string under the condition that a silencing detector of the connector is closed; judging whether the first signal string comprises an outburst signal under first operation frequency; on yes judgment, starting the silencing detector and utilizing the silencing detector to judge whether a second signal string is an awakening signal under second operation frequency, wherein the second signal string is received after the first signal string, and the second operation frequency is higher than the first operation frequency. The control method further includes that the operation state of the connector is changed to the starting state if the second signal string is the awakening signal. Therefore, power consumption of the connector can be reduced.
Description
Technical field
The invention relates to a kind of control method of connector and use connector and the memorizer memory devices of the method.
Background technology
Digital camera, mobile phone and MP3 player are very rapid in growth over the years, and consumer is also increased rapidly to the demand of Storage Media.For example, because duplicative non-volatile memory module (, flash memory) has that data are non-volatile, power saving, volume be little, and the characteristic such as machinery-free structure, so be built in above-mentioned given an example various portable multimedia devices in being applicable to very much.
In general, duplicative non-volatile memory module is to be controlled by a Memory Controller, and Memory Controller can be coupled to a host computer system by a connector.The standard meeting according to this connector, the mode of operation of connector comprises starting state and a non-started state to I haven't seen you for ages conventionally.In starting state, host computer system can this duplicative non-volatile memory module of access.In non-started state, Memory Controller can be closed element or the function of its part, the consumption of saving by this power.But in non-started state, connector must detect the signal from host computer system, judge whether by this will reply as starting state.That is to say in connector, to have the element of part to continue to operate the signal that detects host computer system transmission.Therefore, how under non-started state, further save the power that connector consumes, the subject under discussion of being concerned about for those skilled in the art.
Summary of the invention
In exemplary embodiment of the present invention, propose a kind of control method, connector and memorizer memory devices of connector, can save the power consumption of connector under non-started state.
The present invention's one exemplary embodiment proposes a kind of control method of connector.This control method comprises: in a pent situation of squelch detector of connector, receive first signal string; Whether comprise a burst at the first operating frequency this first signal string that judges; If first signal string comprises burst, start squelch detector, and whether be wake-up signal by squelch detector at the second operating frequency secondary signal string that judges, wherein secondary signal string be received in first signal string after, and the second operating frequency is greater than the first operating frequency.This control method also comprises: if secondary signal string is wake-up signal, change the mode of operation of connector to starting state.
In an exemplary embodiment, above-mentioned control method also comprises: if secondary signal string is not wake-up signal, close squelch detector, receive the 3rd signal, and judge whether the 3rd signal comprises burst.
In an exemplary embodiment, above-mentionedly whether comprise that at the first operating frequency first signal string that judges the step of burst comprises: whether comprise that at the first operating frequency first signal string that judges length is more than or equal to the subsignal of n unit interval, wherein n is more than or equal to 2 positive integer; And if first signal string comprises described subsignal, judge that first signal string comprises burst.
In an exemplary embodiment, above-mentioned positive integer n is 5.
In an exemplary embodiment, whether above-mentioned be that the step of wake-up signal comprises by squelch detector at the second operating frequency secondary signal string that judges: judge by squelch detector whether secondary signal string comprises m burst, and wherein m is positive integer; If secondary signal string comprises m burst, judge that by squelch detector secondary signal string is wake-up signal.
In the present invention's one exemplary embodiment, a kind of memorizer memory devices is proposed.This memorizer memory devices comprises connector, duplicative non-volatile memory module and Memory Controller.Connector is in order to be coupled to a host computer system.Duplicative non-volatile memory module comprises multiple physics unit of erasing.Memory Controller is to be coupled to connector and duplicative non-volatile memory module.Above-mentioned connector comprises state controller, squelch detector and burst detector.Squelch detector is to be coupled to state controller.Burst detector is to be coupled to squelch detector, in order to receive first signal string in the pent situation of squelch detector, and whether comprises a burst at the first operating frequency first signal string that judges.If first signal string comprises burst, burst detector is in order to start squelch detector.After squelch detector is waken up, whether squelch detector is a wake-up signal in order to the secondary signal string that judges at the second operating frequency, wherein secondary signal string be received in first signal string after, and the second operating frequency is greater than the first operating frequency.If secondary signal string is wake-up signal, state controller in order to the mode of operation that changes connector to starting state.
In an exemplary embodiment, if secondary signal string is not wake-up signal, burst detector, also in order to close squelch detector, receives the 3rd signal, and judges whether the 3rd signal comprises burst.
In an exemplary embodiment, whether above-mentioned burst detector comprises that at the first operating frequency first signal string that judges the operation of burst comprises: whether burst detector comprises that at the first operating frequency first signal string that judges length is more than or equal to the subsignal of n unit interval, and wherein n is more than or equal to 2 positive integer; If first signal string comprises subsignal, squelch detector can judge that first signal string comprises burst.
In an exemplary embodiment, above-mentioned positive integer n is 5.
In an exemplary embodiment, above-mentioned squelch detector judges that whether secondary signal string is that the operation of wake-up signal comprises: squelch detector judges whether secondary signal string comprises m burst, and wherein m is positive integer; If secondary signal string comprises m burst, squelch detector judges that secondary signal string is wake-up signal.
The present invention's one exemplary embodiment proposes a kind of connector, comprises state controller, squelch detector and burst detector.Squelch detector is to be coupled to state controller.Burst detector is to be coupled to squelch detector, in order to receive first signal string in the pent situation of squelch detector, and whether comprises a burst at the first operating frequency first signal string that judges.If first signal string comprises burst, burst detector can start squelch detector.After squelch detector is waken up, whether squelch detector is a wake-up signal in order to the secondary signal string that judges at the second operating frequency, wherein secondary signal string be received in first signal string after, and the second operating frequency is greater than the first operating frequency.If secondary signal string is wake-up signal, state controller in order to the mode of operation that changes connector to starting state.
In an exemplary embodiment, if secondary signal string is not wake-up signal, burst detector, also in order to close squelch detector, receives the 3rd signal, and judges whether the 3rd signal comprises burst.
In an exemplary embodiment, whether above-mentioned burst detector comprises that at the first operating frequency first signal string that judges the operation of burst comprises: whether burst detector comprises that at the first operating frequency first signal string that judges length is more than or equal to a subsignal of n unit interval, and wherein n is more than or equal to 2 positive integer; If first signal string comprises subsignal, squelch detector judges that first signal string comprises burst.
In an exemplary embodiment, above-mentioned positive integer n is 5.
In an exemplary embodiment, above-mentioned squelch detector judges that whether secondary signal string is that the operation of wake-up signal comprises: squelch detector judges whether secondary signal string comprises m burst, and wherein m is positive integer; If secondary signal string comprises m burst, squelch detector judges that secondary signal string is wake-up signal.
In an exemplary embodiment, above-mentioned burst detector comprises low-power squelch detector and squelch detector control circuit.Above-mentioned squelch detector comprises squelch detecting circuit and frequency external signal decision circuitry.Squelch detector control circuit is to be coupled to low-power squelch detector.Squelch detecting circuit is to be coupled to squelch detector control circuit.Frequently external signal decision circuitry is to be coupled to squelch detecting circuit and state controller.Low-power squelch detector is in order to receive first signal string in the pent situation of squelch detecting circuit, and whether comprises burst at the first operating frequency first signal string that judges.If first signal string comprises burst, squelch detector control circuit is in order to start squelch detecting circuit.After squelch detecting circuit is activated, squelch detecting circuit is in order to detect the second burst and the blank signal in secondary signal string under the second operating frequency, and frequency external signal decision circuitry is in order to judge according to the second burst and blank signal whether secondary signal string is wake-up signal.
The present invention's one exemplary embodiment proposes a kind of connector that meets the advanced annex standard of sequence.This connector comprises low frequency signal detecting device, signal detector control circuit, high-frequency detector, high-frequency signal decision circuitry and state controller.Signal detector control circuit is to be coupled to low frequency signal detecting device.High-frequency detector is to be coupled to signal detector control circuit.High-frequency signal decision circuitry is to be coupled to high-frequency detector.State controller is to be coupled to signal detector control circuit and high-frequency signal decision circuitry.Low frequency signal detecting device is in order to receive first signal string in the pent situation of high-frequency detector, and whether comprises a first signal model at the first operating frequency first signal string that judges.If first signal string comprises first signal model, signal detector control circuit is in order to start high-frequency detector.After high-frequency detector is activated, whether high-frequency detector comprises a secondary signal model in order to detect secondary signal string under the second operating frequency.Wherein secondary signal string be received in first signal string after, the second operating frequency is greater than the first operating frequency, and first signal model is different from secondary signal model.If secondary signal string comprises secondary signal model, state controller is starting state in order to change the mode of operation of connector.
In an exemplary embodiment, the first above-mentioned operating frequency is not more than the half of the second operating frequency.
Based on above-mentioned, the control method proposing in the embodiment of the present invention, in connector and memorizer memory devices, because connector squelch detector under non-started state is to be closed, and be to detect the burst from host computer system by burst detector, therefore can reduce the power that connector consumes.
For above-mentioned feature and advantage of the present invention can be become apparent, special embodiment below, and coordinate appended graphic being described in detail below.
Accompanying drawing explanation
Figure 1A is host computer system and the memorizer memory devices illustrating according to an exemplary embodiment.
Figure 1B is the schematic diagram of the computing machine, input/output device and the memorizer memory devices that illustrate according to an exemplary embodiment.
Fig. 1 C is the host computer system that illustrates according to an exemplary embodiment and the schematic diagram of memorizer memory devices.
Fig. 2 is the summary calcspar that illustrates the memorizer memory devices shown in Figure 1A.
Fig. 3 is the summary calcspar of the Memory Controller that illustrates according to an exemplary embodiment.
Fig. 4 is the circuit block diagram that illustrates connector according to an embodiment.
Fig. 5 is the process flow diagram that illustrates the control method of connector according to an exemplary embodiment.
Fig. 6 is the schematic diagram that illustrates wake-up signal, registration signal and D24.3 characteristic signals according to an exemplary embodiment.
Fig. 7 is the circuit block diagram that illustrates connector according to the second exemplary embodiment.
Fig. 8 illustrates connector according to the second exemplary embodiment to switch in the process flow diagram between starting state and part/sleep state.
Fig. 9 is the circuit block diagram that illustrates connector according to the 3rd exemplary embodiment.
[main element label declaration]
Embodiment
[the first exemplary embodiment]
Generally speaking, memorizer memory devices (also claiming memory storage system) comprises duplicative non-volatile memory module and controller (also claiming control circuit).Conventionally memorizer memory devices is to use together with host computer system, so that host computer system can write to data memorizer memory devices or reading out data from memorizer memory devices.
Figure 1A is host computer system and the memorizer memory devices illustrating according to an exemplary embodiment.
Please refer to Figure 1A, host computer system 1000 generally comprises computing machine 1100 and I/O (input/output, I/O) device 1106.Computing machine 1100 comprises microprocessor 1102, random access memory (random access memory, RAM) 1104, system bus 1108 and data transmission interface 1110.Input/output device 1106 comprises as the mouse 1202 of Figure 1B, keyboard 1204, display 1206 and printer 1208.It must be appreciated, the unrestricted input/output device 1106 of the device shown in Figure 1B, input/output device 1106 can also comprise other device.
In embodiments of the present invention, memorizer memory devices 100 is to couple by data transmission interface 1110 and other element of host computer system 1000.Data can be write to memorizer memory devices 100 or reading out data from memorizer memory devices 100 by microprocessor 1102, random access memory 1104 with the running of input/output device 1106.For example, memorizer memory devices 100 can be the duplicative non-volatile memory storage device of portable disk 1212, storage card 1214 or solid state hard disc (Solid State Drive, SSD) 1216 as shown in Figure 1B etc.
Generally speaking, host computer system 1000 is for can coordinate substantially any system with storage data with memorizer memory devices 100.Although in this exemplary embodiment, host computer system 1000 is to explain with computer system, but host computer system 1000 can be the systems such as digital camera, video camera, communicator, audio player or video player in another exemplary embodiment of the present invention.For example, be digital camera (video camera) 1310 o'clock in host computer system, duplicative non-volatile memory storage device is its SD card 1312 using, mmc card 1314, memory stick (memory stick) 1316, CF card 1318 or embedded storage device 1320 (as shown in Figure 1 C).Embedded storage device 1320 comprises embedded multi-media card (Embedded MMC, eMMC).It is worth mentioning that, embedded multi-media card is to be directly coupled on the substrate of host computer system.
Fig. 2 is the summary calcspar that illustrates the memorizer memory devices shown in Figure 1A.
Please refer to Fig. 2, memorizer memory devices 100 comprises connector 102, Memory Controller 104 and duplicative non-volatile memory module 106.
In this exemplary embodiment, connector 102 is to be compatible to advanced annex (Serial Advanced Technology Attachment, the SATA) standard of sequence.But, it must be appreciated, the invention is not restricted to this, connector 102 can also be to meet high-speed peripheral component connecting interface (Peripheral Component Interconnect Express, PCI Express) standard or other applicable standard.
Memory Controller 104 is multiple logic gates or the steering order with hardware pattern or firmware pattern implementation in order to execution, and in duplicative non-volatile memory module 106, carries out the runnings such as writing, read and erase of data according to the instruction of host computer system 1000.
Duplicative non-volatile memory module 106 is to be coupled to Memory Controller 104, and the data that write in order to store host computer system 1000.Duplicative non-volatile memory module 106 has the physics unit 304 (0)～304 (R) of erasing.For example, the physics unit 304 (0)～304 (R) of erasing can belong to same memory crystal grain (die) or belong to different memory crystal grain.Each physics unit of erasing has respectively multiple physics programming units, and belongs to the erase physics programming unit of unit of same physics and can be write independently and side by side be erased.For example, each physics unit of erasing is made up of 128 physics programming units.But, it must be appreciated, the invention is not restricted to this, each physics erase unit be can by 64 physics programming units, 256 physics programming units or other arbitrarily a physics programming unit be formed.
In more detail, the physics unit of erasing is the least unit of erasing.That is, each physics storage unit of being erased in the lump that unit contains minimal amount of erasing.Physics programming unit is the minimum unit of programming.The minimum unit that, physics programming unit is data writing.Each physics programming unit generally includes data bit district and redundant digit district.Data bit district comprises multiple physics access address in order to store user's data, and redundant digit district for example, in order to the data (, control information and error correcting code) of stocking system.In this exemplary embodiment, in the data bit district of each physics programming unit, can comprise 4 physics access addresses, and the size of a physics access address is 512 bytes (byte, B).But, in other exemplary embodiment, in data bit district, also can comprise 8,16 or the more or less physics access address of number, the present invention does not limit size and the number of physics access address.For example, the physics unit of erasing is physical blocks, and physics programming unit is physical page or physics fan.
In this exemplary embodiment, duplicative non-volatile memory module 106 is multi-level cell memory (Multi Level Cell, MLC) NAND type flash memory module, in a storage unit, can store at least 2 bit data.But, the invention is not restricted to this, also single-order storage unit (Single Level Cell of duplicative non-volatile memory module 106, SLC) NAND type flash memory module, multi-level cell memory (Trinary Level Cell, TLC) NAND type flash memory module, other flash memory module or other have the memory module of identical characteristics.
Fig. 3 is the summary calcspar of the Memory Controller that illustrates according to an exemplary embodiment.
Please refer to Fig. 3, Memory Controller 104 comprises memory management circuitry 202, host interface 204 and memory interface 206.
In this exemplary embodiment, the steering order of memory management circuitry 202 is to carry out implementation with firmware pattern.For example, memory management circuitry 202 has microprocessor unit (not illustrating) and ROM (read-only memory) (not illustrating), and these a little steering orders are to be burned onto in this ROM (read-only memory).In the time that memorizer memory devices 100 operates, these a little steering orders can be carried out to carry out by microprocessor unit the runnings such as writing, read and erase of data.
In another exemplary embodiment of the present invention, the steering order of memory management circuitry 202 can also procedure code pattern for example be stored in, in the specific region (, being exclusively used in the system region of storage system data in memory module) of duplicative non-volatile memory module 106.In addition, memory management circuitry 202 has microprocessor unit (not illustrating), ROM (read-only memory) (not illustrating) and random access memory (not illustrating).Particularly, this ROM (read-only memory) has the code of driving, and in the time that Memory Controller 104 is enabled, microprocessor unit can first be carried out this and drive code section that the steering order being stored in duplicative non-volatile memory module 106 is loaded in the random access memory of memory management circuitry 202.Afterwards, microprocessor unit can turn round these a little steering orders to carry out the runnings such as writing, read and erase of data.
In addition,, in another exemplary embodiment of the present invention, the steering order of memory management circuitry 202 can also a hardware pattern be carried out implementation.For example, memory management circuitry 202 comprises microcontroller, Memory Management Unit, storer writing unit, storer reading unit, storer erase unit and data processing unit.Erase unit and data processing unit of Memory Management Unit, storer writing unit, storer reading unit, storer is to be coupled to microcontroller.Wherein, Memory Management Unit is in order to manage the physical blocks of duplicative non-volatile memory module 106; Storer writing unit writes instruction data are write in duplicative non-volatile memory module 106 in order to duplicative non-volatile memory module 106 is assigned; Storer reading unit is in order to assign reading command with reading out data from duplicative non-volatile memory module 106 to duplicative non-volatile memory module 106; Storer is erased unit in order to duplicative non-volatile memory module 106 is assigned to the instruction of erasing so that data are erased from duplicative non-volatile memory module 106; And data processing unit is wanted the data that write to the data of duplicative non-volatile memory module 106 and read from duplicative non-volatile memory module 106 in order to processing.
In the present invention's one exemplary embodiment, Memory Controller 104 also comprises memory buffer 252, electric power management circuit 254 and bug check and correcting circuit 256.
Electric power management circuit 254 is to be coupled to memory management circuitry 202 and the power supply in order to control store storage device 100.
Bug check and correcting circuit 256 be coupled to memory management circuitry 202 and in order to execution error inspection and correction program to guarantee the correctness of data.Specifically, when memory management circuitry 202 receives while writing instruction from host computer system 1000, bug check can produce corresponding bug check and correcting code (Error Checking and Correcting Code for the corresponding data that this writes instruction with correcting circuit 256, ECC Code), and memory management circuitry 202 can write to corresponding these data that write instruction in duplicative non-volatile memory module 106 with corresponding bug check and correcting code.Afterwards, when memory management circuitry 202 can read bug check corresponding to these data and correcting code when reading out data from duplicative non-volatile memory module 106 simultaneously, and bug check and correcting circuit 256 can be according to this bug check and correcting code to read data execution error inspection and correction programs.
Fig. 4 is the circuit block diagram that illustrates connector according to an embodiment.
Please refer to Fig. 4, connector 102 comprises burst detector 410 (burst detector), squelch detector 420 (squelch detector) and state controller 430.
State controller 430 is the modes of operation in order to control linkage device.When host computer system 100 is during just at access memory storage device 100, the mode of operation of connector 102 is starting state.Otherwise if host computer system 100 is not wanted access memory storage device 100, state controller 430 can enter a non-started state by control linkage device 102.In non-started state, connector 102 or Memory Controller 104 can be closed some of circuit, save by this consumption of power.On the other hand, when connector 102 is during at non-started state, if host computer system 100 transmits a wake-up signal to connector 102, can to change the mode of operation of connectors 102 be starting state to state controller 430.In other words, connector 102 can be compatible with any standard that defines wake-up signal.For example, if connector 102 is compatible with SATA standard, the mode of operation of connector 102 comprises startup (active) state, partly (partial) state and sleep (slumber) state.Partial status and sleep state are also collectively referred to as non-started state.If connector 102 will be replied as starting state from non-started state, need to spend a period of time.In general, dormant power saving effect is better than the power saving effect of partial status, is that the required time of starting state is longer than the time that is starting state from partial status reply but reply from sleep state.
Squelch detector 420 is in order to the power grade of detection signal string 401 (power level).Train of signal 401 can comprise one or more signal.If the power grade of train of signal 401 is lower than a predetermined level, squelch detector 420 can be closed the circuit not used.For example, when the power grade of train of signal 401 is during lower than predetermined level, squelch detector 420 can send a message to state controller 430, and state controller 430 can be non-started state according to the mode of operation of this message sets connector 102.On the other hand, if the power grade of train of signal 401 for example, higher than predetermined level (, train of signal 401 has comprised a wake-up signal), the mode of operation that squelch detector 420 can drive state controllers 430 changes connector 102 is starting state.In an exemplary embodiment, train of signal 401 is frequency external signals (out-of-band signaling, OOB-signaling).And external signal is a kind of Data Styles (data pattern) frequently, interval (gap) signal and burst (burst) signal are wherein defined.The amplitude of burst can for example, with a frequency (, 1.5G hertz) vertical tremor, and the amplitude of blank signal signal remains unchanged.In other words, train of signal 401 can comprise one or more blank signal and burst.In frequency external signal, wake-up signal at least comprises 6 blank signals and 6 bursts, and squelch detector 420 can detect these blank signals and bursts, and judges in train of signal 401, whether to have comprised wake-up signal.
Fig. 6 is the schematic diagram that illustrates wake-up signal, registration signal and D24.3 characteristic signals according to an exemplary embodiment.
Please refer to Fig. 6, wake-up signal 510 comprises burst 511a～511f and blank signal 512a～512f.And each burst can by four alignings (align) signal 520 or four D24.3 characteristic signals 530 be formed.At this, a unit interval represents the length (, cycle) of the subsignal of wake-up signal 510 medium frequency maximums.For example, the maximum frequency of wake-up signal 510 is 1.5G hertz, and therefore each unit interval (unit interval) is 1/1.5G second (for example, unit interval 540).The beginning of registration signal 521 can comprise that length is the subsignal 521 of 5 unit intervals, next for multiple length is the subsignal of 1 or 2 unit interval.For example, and D24.3 characteristic signals 530 is formed (, subsignal 531) by length by the subsignal of 2 unit intervals entirely.In this exemplary embodiment, the operating frequency of squelch detector 420 is 1.5G hertz, the subsignal that random length detected that therefore can be complete; The operating frequency of burst detector 410 is 750M hertz, can detect the subsignal (, frequency is less than the subsignal of 750M hertz) that length is more than or equal to 2 unit intervals.
In this exemplary embodiment, when the mode of operation of connector 102 is during at partial status or sleep state, squelch detector 420 can be closed and burst detector 410 can be activated.It should be noted that because the second operating frequency is less than the first operating frequency the power that the power consuming when therefore burst detector 410 operates consumes can operate lower than squelch detector 420 time.In the time that burst detector 410 receives a first signal string 401, can first judge whether this first signal string comprises a burst.For example, burst detector 410 can judge in this first signal string 401 whether comprise that length is more than or equal to the subsignal of n unit interval, and wherein n is more than or equal to 2 positive integer.For example, n is positive integer 2, and therefore burst detector 410 can detect subsignal 521 and 531.If first signal string comprises length and is more than or equal to the subsignal of n unit interval, just burst detector 410 can judge that first signal string has comprised a burst and started squelch detector 420.
After squelch detector 420 is waken up, squelch detector 420 can continue to receive a secondary signal string, and judges whether secondary signal string is wake-up signal.This secondary signal string is to continue after first signal string, to send the signal of connector 102 to.For example, first signal string comprises burst 511a, and secondary signal string comprises burst 511b～511f.In an exemplary embodiment, if judging secondary signal string, squelch detector 420 comprises m burst, and squelch detector 420 can judge that secondary signal string is wake-up signal, and wherein m is positive integer (for example, m is 4).In other words, after burst detector 410 detects first burst 511a, can start squelch detector 420, and detect ensuing burst 511b～511f by squelch detector 420.It should be noted that because wake-up signal 510 can comprise 6 burst 511a～511f and 6 blank signal 512a～512f, and burst detector 410 received burst 511a, therefore in an exemplary embodiment, m can be set and is less than 6.
If it is wake-up signal that squelch detector 420 judges secondary signal string, squelch detector 420 can transmit a message to state controller 430.State controller 430 can be starting state according to the mode of operation of this message alteration connector 102.
In other exemplary embodiment, between connector 102 and host computer system 1000, the blank signal of transmission and the maximum frequency of burst can be also 3.0G hertz (now a unit interval is 1/3G second) or other numerical value, and the present invention is also not subject to the limits.In an exemplary embodiment, in the time that the maximum frequency of blank signal and burst is 3.0G hertz, the first operating frequency is 1.5G hertz, and the second operating frequency is 3.0G hertz.But the first operating frequency and the second operating frequency also can be set to other numerical value, the present invention is also not subject to the limits.
In an exemplary embodiment, if the received wake-up signal of connector 102 is only made up of registration signal, burst detector 410 can be set as 5 by n.For example, that is in the time that first signal string has comprised that length is more than or equal to the subsignal of 5 unit intervals (, subsignal 521), burst detector 410 just can judge that first signal string has comprised burst.Thus, lower (for example, 300M hertz) that the operating frequency of burst detector 410 can be set, further reduces the power consuming when burst detector 410 operates by this.But in other exemplary embodiment, burst detector 410 can be set as n 3,4 or other numerical value, the present invention is also not subject to the limits.
In an exemplary embodiment, if burst detector 410 can detect within the time of a burst whether received signal comprises a burst, and squelch detector 420 also can be set as 5 by m.Or squelch detector 420 also can be set as m 3 or other numerical value, the present invention is also not subject to the limits.
Fig. 6 is the process flow diagram that illustrates the control method of connector according to an exemplary embodiment.
Please refer to Fig. 6, in step S602, in the pent situation of squelch detector, burst detector 410 can receive a first signal string.In step S604, whether burst detector 410 can comprise a burst at the first operating frequency first signal string that judges.If first signal string does not comprise burst, get back to step S602.If first signal string comprises burst, in step S606, burst detector 410 can start squelch detector 420.In step S608, whether squelch detector 420 is wake-up signal at the second operating frequency secondary signal string that judges, and wherein the second operating frequency is greater than the first operating frequency.If secondary signal string is wake-up signal, in step S609, the mode of operation that state controller 430 can change connector is starting state.But in Fig. 5, each step has illustrated as above, just repeats no more at this.
[the second exemplary embodiment]
The second embodiment and the first embodiment part are similar, only describe difference at this.
Fig. 7 is the circuit block diagram that illustrates connector according to the second exemplary embodiment.
Please refer to Fig. 7, in the second exemplary embodiment, burst detector 410 has comprised low-power squelch detecting circuit 411 and squelch detector control circuit 412.Squelch detector 420 has comprised squelch detecting circuit 421 and frequency external signal decision circuitry 422.Low-power squelch detecting circuit 411 is in order to detect a burst under the first operating frequency.Squelch detector control circuit 412 is for example, in order to control (, start or cut out) squelch detecting circuit 421.Squelch detecting circuit 421 is in order to detect a burst in signal under the second operating frequency, and external signal decision circuitry 422 is to judge whether a signal is wake-up signal frequently.
Specifically, in the time that connector 102 is part/sleep state, squelch detecting circuit 421 can be closed.In the pent situation of squelch detecting circuit 421, low-power squelch detecting circuit 411 can receive train of signal 401, and judges whether train of signal 401 comprises that length is more than or equal to the subsignal of n unit interval.If train of signal 401 has comprised length and has been more than or equal to the subsignal of n unit interval, squelch detector control circuit 412 meeting startup squelch detecting circuits 421.Squelch detecting circuit 421 can continue to receive secondary signal string, and detects burst and the blank signal in secondary signal string.Frequently external signal decision circuitry 422 can judge whether secondary signal string is wake-up signal according to the burst in secondary signal string and blank signal.For example, if secondary signal string comprises m burst, external signal decision circuitry 422 can judge that secondary signal string is wake-up signal frequently.On the other hand, if external signal decision circuitry 422 judges that secondary signal string is not wake-up signal frequently, squelch detector control circuit 412 can cut out squelch detector 421, only receive next signal (also claiming the 3rd signal) by low-power squelch detecting circuit 411, and judge by low-power squelch detecting circuit 411 whether this 3rd signal comprises a burst.
Fig. 8 illustrates connector according to the second exemplary embodiment to switch in the process flow diagram between starting state and part/sleep state.
Please refer to Fig. 8, in step S802, connector 102 enters starting state.
In step S804, state controller 430 can judge whether to want entering part/sleep state.For example, state controller 430 can according to the indication of host computer system 1000 or the indication of Memory Controller 104 determines whether wanting entering part/sleep state.Or state controller 430 also can for example, judge whether to want entering part/sleep state by the information (, stand-by time) of itself.
If want entering part/sleep state, in step S806, state controller 430 can be set connector 102 entering parts/sleep state.Now, squelch detector control circuit 412 can cut out squelch detecting circuit 421.
In step S808, low-power squelch detecting circuit 411 can judge whether to have detected burst.
If low-power squelch detecting circuit 411 has detected burst, in step S810, squelch detector control circuit 412 can start squelch detecting circuit 421.
In step S812, squelch detector 420 can judge whether to detect wake-up signal.Specifically, squelch detecting circuit 421 can detect the burst in secondary signal string, and external signal decision circuitry 422 can judge whether this secondary signal string is wake-up signal frequently.
If it is wake-up signal that squelch detector 420 judges this secondary signal string, can get back to step S802, wherein state controller 430 can enter starting state by control linkage device 102.If squelch detector 420 does not detect wake-up signal, in step S814, squelch detector control circuit 412 can cut out squelch detecting circuit 421, and gets back to step S808.But in Fig. 8, each step has described in detail as above, just repeats no more at this.
[the 3rd exemplary embodiment]
Fig. 9 is the circuit block diagram of the connector that illustrates according to the 3rd exemplary embodiment.
Please refer to Fig. 9, connector 900 comprises low frequency signal detecting device 911, signal detector control circuit 912, high-frequency signal detecting device 921, high-frequency signal decision circuitry 922 and state controller 930.Connector 900 is to meet the advanced annex standard of sequence, and train of signal 901 can meet the definition of external signal frequently.Connector 900 can be installed on host computer system, hard disk, portable disk, solid state hard disc, personal computer or a server, and the present invention is also not subject to the limits.
When connector 900 is during at partial status and sleep state, high-frequency signal detecting device 921 can be closed and low frequency signal detecting device 911 can be activated.Low frequency signal detecting device 911 is in order to receive train of signal 901 (also claiming first signal string) in the pent situation of high-frequency signal detecting device 921, and whether comprises a first signal model at the first operating frequency first signal string that judges.For example, low frequency signal detecting device 911 judges whether first signal string has the burst of a specific quantity (being called the first burst), if judge that first signal string comprises first signal model.This first burst meets the pulse signal of a characteristic frequency, and its frequency is to be for example not more than 750M hertz (Hz).If first signal string comprises the first burst, signal detector control circuit 912 can start high-frequency signal detecting device 921.After being activated, high-frequency signal detecting device 921 can continue to receive a secondary signal string, and under the second operating frequency, detects in secondary signal string whether comprise a secondary signal model, and wherein this first signal model is different from secondary signal model.Secondary signal model is for example made up of several blank signals and several the second burst.The second burst meets the pulse signal of a characteristic frequency, and the frequency of this second burst can be identical or be different from the first burst.For example, high-frequency signal decision circuitry 922 can detect according to high-frequency signal detecting device 921 the second burst and blank signal judge whether secondary signal string is a wake-up signal.For instance, the wake-up signal in frequency external signal can be at least made up of 6 blank signals and 6 the second bursts.Specifically, the first operating frequency can be lower than the second operating frequency.For example, the first operating frequency is not more than the half of the second operating frequency, but the present invention not subject to the limits.For example, if secondary signal string comprises a secondary signal model (, wake-up signal), the mode of operation of state controller 930 meeting change connectors 900 is starting state.
In sum, in control method, memorizer memory devices and the connector of the connector proposing in the embodiment of the present invention, because burst detector is to detect burst under the first operating frequency, and the larger squelch detector of ability starting power consumption, therefore can reduce the power consumption of connector under non-started state in the time burst being detected.
Although the present invention discloses as above with embodiment; so it is not in order to limit the present invention; under any, in technical field, have and conventionally know the knowledgeable; without departing from the spirit and scope of the present invention; when doing a little change and retouching, therefore protection scope of the present invention is when being as the criterion depending on the appended claim scope person of defining.
Claims (19)
1. a control method for connector, wherein this connector comprises a squelch detector, it is characterized in that, this control method comprises:
In the pent situation of this squelch detector, receive a first signal string;
Whether comprise a burst at one first operating frequency this first signal string that judges;
If this first signal string comprises this burst, start this squelch detector, and whether be a wake-up signal by this squelch detector at the one second operating frequency secondary signal string that judges, wherein this secondary signal string be received in this first signal string after, and this second operating frequency is greater than this first operating frequency; And
If this secondary signal string is this wake-up signal, change mode of operation to starting state of this connector.
2. control method according to claim 1, also comprises:
If this secondary signal string is not this wake-up signal, close this squelch detector, receive one the 3rd signal, and judge whether the 3rd signal comprises this burst.
3. whether control method according to claim 1, wherein comprise that at this first operating frequency this first signal string that judges the step of this burst comprises:
Whether comprise that at this first operating frequency this first signal string that judges length is more than or equal to a subsignal of n unit interval, wherein n is more than or equal to 2 positive integer; And
If this first signal string comprises this subsignal, judge that this first signal string comprises this burst.
4. control method according to claim 3, wherein this positive integer n is 5.
5. whether control method according to claim 1 is wherein that the step of this wake-up signal comprises by this squelch detector at this second operating frequency this secondary signal string that judges:
Judge by this squelch detector whether this secondary signal string comprises m burst, and wherein m is positive integer;
If this secondary signal string comprises this m burst, judge that by this squelch detector this secondary signal string is this wake-up signal.
6. a memorizer memory devices, is characterized in that, this memorizer memory devices comprises:
A connector, in order to be coupled to a host computer system;
One duplicative non-volatile memory module, comprises multiple physics unit of erasing; And
One Memory Controller, is coupled to this connector and this duplicative non-volatile memory module,
Wherein this connector comprises:
One state controller;
One squelch detector, is coupled to this state controller; And
One burst detector, is coupled to this squelch detector, in order to receive a first signal string in the pent situation of this squelch detector, and whether comprises a burst at one first operating frequency this first signal string that judges,
Wherein, if this first signal string comprises this burst, this burst detector is in order to start this squelch detector,
After this squelch detector is activated, whether this squelch detector is a wake-up signal in order to the secondary signal string that judges at one second operating frequency, wherein this secondary signal string be received in this first signal string after, and this second operating frequency is greater than this first operating frequency
If this secondary signal string is this wake-up signal, this state controller is in order to change mode of operation to starting state of this connector.
7. memorizer memory devices according to claim 6, if wherein this secondary signal string is not this wake-up signal, this burst detector, also in order to close this squelch detector, receives one the 3rd signal, and judges whether the 3rd signal comprises this burst.
8. memorizer memory devices according to claim 6, wherein whether this burst detector comprises that at this first operating frequency this first signal string that judges the operation of this burst comprises:
Whether this burst detector comprises that at this first operating frequency this first signal string that judges length is more than or equal to a subsignal of n unit interval, and wherein n is more than or equal to 2 positive integer;
If this first signal string comprises this subsignal, this squelch detector judges that this first signal string comprises this burst.
9. memorizer memory devices according to claim 8, wherein this positive integer n is 5.
10. memorizer memory devices according to claim 6, wherein judges that in this squelch detector whether this secondary signal string is that the operation of this wake-up signal comprises:
This squelch detector judges whether this secondary signal string comprises m burst, and wherein m is positive integer;
If this secondary signal string comprises m burst, this squelch detector judges that this secondary signal string is this wake-up signal.
11. memorizer memory devices according to claim 6, wherein this burst detector comprises:
One low-power squelch detector; And
One squelch detector control circuit, is coupled to this low-power squelch detector,
This squelch detector comprises;
One squelch detecting circuit, is coupled to this squelch detector control circuit; And
One frequency external signal decision circuitry, is coupled to this squelch detecting circuit and this state controller,
Wherein, this low-power squelch detector is in order to receive this first signal string in the pent situation of this squelch detecting circuit, and whether comprises this burst at this first operating frequency this first signal string that judges,
If this first signal string comprises this burst, this squelch detector control circuit is in order to start this squelch detecting circuit,
After this squelch detecting circuit is activated, this squelch detecting circuit is in order to detect one second burst and the blank signal in this secondary signal string under this second operating frequency, and this frequency external signal decision circuitry is in order to judge according to this second burst and this blank signal whether this secondary signal string is this wake-up signal.
12. 1 kinds of connectors, is characterized in that, this connector comprises:
One state controller;
One squelch detector, is coupled to this state controller; And
One burst detector, is coupled to this squelch detector, in order to receive a first signal string in the pent situation of this squelch detector, and whether comprises a burst at one first operating frequency this first signal string that judges,
Wherein, if this first signal string comprises this burst, this burst detector starts this squelch detector,
After this squelch detector is activated, whether this squelch detector is a wake-up signal in order to the secondary signal string that judges at one second operating frequency, wherein this secondary signal string be received in this first signal string after, and this second operating frequency is greater than this first operating frequency
If this secondary signal string is this wake-up signal, this state controller is a starting state in order to change a mode of operation of this connector.
13. connectors according to claim 12, if wherein this secondary signal string is not this wake-up signal, this burst detector, also in order to close this squelch detector, receives one the 3rd signal, and judges whether the 3rd signal comprises this burst.
14. connectors according to claim 12, wherein whether this burst detector comprises that at this first operating frequency this first signal string that judges the operation of this burst comprises:
Whether this burst detector comprises that at this first operating frequency this first signal string that judges length is more than or equal to a subsignal of n unit interval, and wherein n is more than or equal to 2 positive integer;
If this first signal string comprises this subsignal, this squelch detector judges that this first signal string comprises this burst.
15. connectors according to claim 14, wherein this positive integer n is 5.
16. connectors according to claim 12, wherein judge that in this squelch detector whether this secondary signal string is that the operation of this wake-up signal comprises:
This squelch detector judges whether this secondary signal string comprises m burst, and wherein m is positive integer;
If this secondary signal string comprises m burst, this squelch detector judges that this secondary signal string is this wake-up signal.
17. connectors according to claim 12, wherein this burst detector comprises:
One low-power squelch detector; And
One squelch detector control circuit, is coupled to this low-power squelch detector,
This squelch detector comprises:
One squelch detecting circuit, is coupled to this squelch detector control circuit; And
One frequency external signal decision circuitry, is coupled to this squelch detecting circuit and this state controller,
Wherein, this low-power squelch detector is in order to receive this first signal string in the pent situation of this squelch detecting circuit, and whether comprises this burst at this first operating frequency this first signal string that judges,
If this first signal string comprises this burst, this squelch detector control circuit is in order to start this squelch detecting circuit,
After this squelch detecting circuit is activated, this squelch detecting circuit is in order to detect one second burst and the blank signal in this secondary signal string under this second operating frequency, and this frequency external signal decision circuitry is in order to judge according to this second burst and this blank signal whether this secondary signal string is this wake-up signal.
18. 1 kinds of connectors, meet the advanced annex standard of a sequence, it is characterized in that, this connector comprises:
One low frequency signal detecting device;
One signal detector control circuit, is coupled to this low frequency signal detecting device;
One high-frequency detector, is coupled to this signal detector control circuit;
One high-frequency signal decision circuitry, is coupled to this high-frequency detector;
One state controller, is coupled to this signal detector control circuit and this high-frequency signal decision circuitry,
Wherein, this low frequency signal detecting device is in order to receive a first signal string in the pent situation of this high-frequency detector, and whether comprises a first signal model at one first operating frequency this first signal string that judges,
If this first signal string comprises this first signal model, this signal detector control circuit is in order to start this high-frequency detector,
After this high-frequency detector is activated, whether this high-frequency detector comprises a secondary signal model in order to detect a secondary signal string under one second operating frequency, wherein this secondary signal string be received in this first signal string after, and this second operating frequency is greater than this first operating frequency, this first signal model is different from this secondary signal model
If this secondary signal string comprises this secondary signal model, this state controller is a starting state in order to change a mode of operation of this connector.
19. connectors according to claim 18, wherein this first operating frequency is not more than the half of this second operating frequency.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201210405185.5A CN103777732B (en) | 2012-10-22 | 2012-10-22 | The control method of adapter, adapter and memorizer memory devices |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201210405185.5A CN103777732B (en) | 2012-10-22 | 2012-10-22 | The control method of adapter, adapter and memorizer memory devices |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN103777732A true CN103777732A (en) | 2014-05-07 |
| CN103777732B CN103777732B (en) | 2016-08-17 |
Family
ID=50570084
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201210405185.5A Active CN103777732B (en) | 2012-10-22 | 2012-10-22 | The control method of adapter, adapter and memorizer memory devices |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN103777732B (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105227404A (en) * | 2015-10-13 | 2016-01-06 | 英特格灵芯片(天津)有限公司 | A kind of method and device thereof detecting transfer of data |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108702704B (en) * | 2017-03-02 | 2021-01-05 | 华为技术有限公司 | Method and device for waking up wireless device |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5881101A (en) * | 1994-09-01 | 1999-03-09 | Harris Corporation | Burst serial tone waveform signaling method and device for squelch/wake-up control of an HF transceiver |
| CN1653406A (en) * | 2002-03-14 | 2005-08-10 | 英特尔公司 | Methods and apparatus for reducing power usage of a transmitter and receiver coupled via a differential serial data link |
| US20070218938A1 (en) * | 2006-03-20 | 2007-09-20 | Conexant Systems, Inc. | Sleep Mode Systems and Methods |
| CN101714022A (en) * | 2008-09-29 | 2010-05-26 | 英特尔公司 | Dynamic squelch detection power control |
| CN102124454A (en) * | 2008-08-21 | 2011-07-13 | 高通股份有限公司 | Universal serial bus (usb) remote wakeup |
-
2012
- 2012-10-22 CN CN201210405185.5A patent/CN103777732B/en active Active
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5881101A (en) * | 1994-09-01 | 1999-03-09 | Harris Corporation | Burst serial tone waveform signaling method and device for squelch/wake-up control of an HF transceiver |
| CN1653406A (en) * | 2002-03-14 | 2005-08-10 | 英特尔公司 | Methods and apparatus for reducing power usage of a transmitter and receiver coupled via a differential serial data link |
| US20070218938A1 (en) * | 2006-03-20 | 2007-09-20 | Conexant Systems, Inc. | Sleep Mode Systems and Methods |
| CN102124454A (en) * | 2008-08-21 | 2011-07-13 | 高通股份有限公司 | Universal serial bus (usb) remote wakeup |
| CN101714022A (en) * | 2008-09-29 | 2010-05-26 | 英特尔公司 | Dynamic squelch detection power control |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105227404A (en) * | 2015-10-13 | 2016-01-06 | 英特格灵芯片(天津)有限公司 | A kind of method and device thereof detecting transfer of data |
| CN105227404B (en) * | 2015-10-13 | 2019-04-09 | 英特格灵芯片(天津)有限公司 | A kind of method and device thereof of detection data transmission |
Also Published As
| Publication number | Publication date |
|---|---|
| CN103777732B (en) | 2016-08-17 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US9612761B2 (en) | Semiconductor device | |
| TWI473099B (en) | Memory storage device, memory controller and controlling method | |
| TWI459400B (en) | Memory stroage apparatus, and memolry controller and power control method | |
| US8606970B2 (en) | Data writing method for non-volatile memory, and controller and storage system using the same | |
| US8595523B2 (en) | Data writing method for non-volatile memory, and controller and storage system using the same | |
| US9424177B2 (en) | Clock switching method, memory controller and memory storage apparatus | |
| CN103035282B (en) | Memorizer memory devices, Memory Controller and method for managing temperature | |
| CN103514103A (en) | Data protection method, memory controller and memory storage device | |
| CN103377155A (en) | Memorizer memory device, memorizer controller and power supply control method | |
| TWI526818B (en) | Method of enabling sleep mode, memory control circuit unit and storage appartus | |
| CN206331414U (en) | A kind of solid state hard disc | |
| CN103777732A (en) | Connector control method, connector and storage storing device | |
| CN104115116A (en) | Systems and methods for managing data in a device for hibernation states | |
| TWI521354B (en) | Controlling method for connector, connector and memory storage device | |
| CN104765625A (en) | Sleep mode starting method, memory control circuit unit and storing equipment | |
| TWI512623B (en) | Method of enabling sleep mode, memory control circuit unit and storage apparatus | |
| US8897093B2 (en) | Controlling method of connector, connector, and memory storage device | |
| TWI738235B (en) | Method for performing resuming management, and memory device and controller thereof and electronic device | |
| CN103198861A (en) | Memory storage device, memory controller and memory control method | |
| CN103985403A (en) | Working clock switching method, memory controller and memory storage device | |
| CN102855192B (en) | Storer erasing method, Memory Controller and memorizer memory devices | |
| CN104809082A (en) | Data protection method, storage storing device and storage control unit circuit | |
| CN104615554A (en) | Memory module detecting method, memory control circuit unit and storing device | |
| CN103926993A (en) | Controlling method of connector, connector and storer storing device | |
| CN103955434A (en) | Data writing-in method, memory controller and memory storage device |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant |