CN103761990A - Method for reducing leakage current of read-only memory - Google Patents
Method for reducing leakage current of read-only memory Download PDFInfo
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- CN103761990A CN103761990A CN201410056343.XA CN201410056343A CN103761990A CN 103761990 A CN103761990 A CN 103761990A CN 201410056343 A CN201410056343 A CN 201410056343A CN 103761990 A CN103761990 A CN 103761990A
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Abstract
The invention discloses a method for reducing leakage current of a read-only memory. The method comprises the steps that the total number of logic data to be stored in the read-only memory is computed; the number of high level logic data in the logic data is computed; the logic data is stored in the read-only memory; and if the number of the high level logic data is greater than one half of the total number of the logic data, the logic data is subjected to negation and then stored in the read-only memory. The invention further discloses the method for reducing the leakage current of the read-only memory. The method comprises the steps that 1, storage addresses of the high level logic data in the logic data to be stored in the read-only memory are acquired; 2, the storage addresses of the high level logic data are converted into addresses of the same row or line of storage units in storage unit arrays in the read-only memory; and 3, the logic data is stored in the read-only memory according to the converted addresses. According to the method, the leakage current and the quiescent power dissipation of the read-only memory are reduced by a smaller-area chip and lower delay, and interference of the leakage current to data storage and reading is reduced.
Description
Technical field
The invention belongs to semiconductor memory technologies field, relate in particular to a kind of method that reduces ROM (read-only memory) leakage current.
Background technology
ROM (read-only memory) is a kind of storer that can only reading out data, the English ROM (Read-Only Memory) that is called for short.ROM stored data, finishes writing before generally packing system in advance, in system work process, can only read, and can rewrite data unlike random access memory.ROM stored data is stable, and after power-off, stored data can not change yet; It is simple in structure, reads conveniently, and low price, is very suitable for storing various fixed routines and data, is the preferential solution of fixed data in various games systems and word-base system.
Due to low price, the area of ROM must as far as possible littlely just have profit; Because function is simple, the area of peripheral circuit is little, and the area of ROM depends primarily on the size of storage unit; So constantly dwindling of semiconductor technology size, provides more multimachine meeting to ROM product.Minimum feature is the technique of F, and the minimum memory unit that can realize is only to need a two terminal device for a bit line and a word line, the live width of its bit line and word line and be indirectly F, and its area is 4F
2; The example of this storage unit is the unit that bit line and word line infall have a diode, as shown in Figure 1, wherein WL1/2/3 is word line, BL1/2/3 is bit line, U11/22 etc. are the diode of bit line and word line infall, diode cathode is connected representative data 1 with bit line, diode cathode and bit line disconnect representative data 0.
Minimum two-terminal device is that also to have brought challenge, one of them challenge when offering an opportunity be the processing of the reverse leakage current in array to ROM product.As shown in Figure 2, if WL2 is low level, BL2 is high level, U22 conducting and be accessed storage unit; In order to make U12 in off state, the level of WL1 can not be lower than the level of BL2; In order to make U23 in off state, the level of BL3 can not be higher than the level of WL2; U13 must have reverse leakage current to flow to BL3 above like this, and in the situation that there is no other paths, it is upper that this leakage current will flow to WL2 by U23, and U33 can provide similar leakage current; Because the WL2 in circuit has dead resistance, these leakage currents will produce the normal read out function of pressure drop affects on parasitic circuit.Suppose the storage array of a 2024x2024, the leakage current of each unit is 40pA, and the all-in resistance of WL equivalence is 4K ohm, and accessed word line voltage may be elevated 0.64V, this voltage approaches with the threshold value of diode, by speed or function that seriously impact is read.
A common method that solves electric leakage problem is the storage unit every some, with the metal of low resistance, word line is linked up.The harm of doing is like this that area will increase, and not minimizing of leakage current, and the quiescent current of chip operation does not improve.
Summary of the invention
The present invention has overcome the defects such as ROM (read-only memory) area that leakage current in prior art effectively solved, reduced leakage current increases and the quiescent current of chip operation does not improve, and has proposed a kind of method that subtracts ROM (read-only memory) leakage current.
The present invention proposes a kind of method that reduces ROM (read-only memory) leakage current, comprise the steps:
Step 1: the sum that calculates the logical data of ROM (read-only memory) to be deposited;
Step 2: the quantity of calculating high level logic data in described logical data;
Step 3: described logical data is deposited in described ROM (read-only memory); If the quantity of described high level logic data is greater than total half of described logical data, will after described logical data negate, deposit in described ROM (read-only memory).
In the method for the minimizing ROM (read-only memory) leakage current that the present invention proposes, further comprise: the quantity of high level logic data in calculating section logical data block, if the quantity of described high level logic data is greater than a total half of logical data in described partial logic block, will after the logical data negate in described partial logic block, deposit in described ROM (read-only memory).
The method of minimizing ROM (read-only memory) leakage current as claimed in claim 1, further comprises step 4: from described ROM (read-only memory), read and outputting logic data; If described logical data is negate before storage, read and reduce after described logical data and export.
In the method for the minimizing ROM (read-only memory) leakage current that the present invention proposes, further comprise: if the quantity of described high level logic data is greater than total half of described logical data, described logical data is deposited in described ROM (read-only memory) after mapping principle is changed.
In the method for the minimizing ROM (read-only memory) leakage current that the present invention proposes, from described ROM (read-only memory), read and outputting logic data; If described logical data through conversion, reads and reduces after described logical data and export according to described mapping principle before storage.
The invention allows for a kind of method that reduces ROM (read-only memory) leakage current, comprise the steps:
Step 1: the memory address of obtaining high level logic data in the logical data of ROM (read-only memory) to be deposited;
Step 2: the memory address of described high level logic data is converted in the memory cell array of described ROM (read-only memory) to the address with a line or same array storage unit;
Step 3: described logical data is deposited in described ROM (read-only memory) by the address after changing.
The present invention, the in the situation that of a small amount of increase chip area and a small amount of delay, has reduced the leakage current in ROM (read-only memory).The logical device of the present invention application is conventional logic gate device, effectively reduce that data read or storing process in overhead.
The present invention, when reducing leakage current, provides safe and encryption and decryption functions flexibly in conjunction with the method for processing leakage current, thereby has made ROM (read-only memory) have better security performance.
Accompanying drawing explanation
Fig. 1 represents to use in prior art the ROM storage array of diode;
Fig. 2 represents the leakage current path in ROM array in prior art;
Fig. 3 represents that the present invention reduces the process flow diagram of the method for ROM (read-only memory) leakage current;
Fig. 4 represents to realize the ROM (read-only memory) of the inventive method and the structural representation of parts thereof;
Fig. 5 represents the schematic diagram of embodiment 1 neutrality line discharge path;
Fig. 6 represents the schematic diagram of address decoding and interval judgement parallel control in embodiment 5;
Fig. 7 represents by increasing a bit line, to distinguish in embodiment 5 schematic diagram of the negate state of word line data;
Fig. 8 represents the schematic diagram of data-mapping storage scheme in embodiment 6;
Fig. 9 represents that the present invention reduces the process flow diagram of the method for ROM (read-only memory) leakage current;
Figure 10 represents to realize the ROM (read-only memory) of the inventive method and the structural representation of parts thereof;
The data in embodiment 7 of representing Figure 11 store the schematic diagram of the Sequential Mapping of storage array into;
The data in embodiment 7 of representing Figure 12 store the schematic diagram of the jump mapping of storage array into;
Figure 13 represents the schematic diagram of the control of address mapping in embodiment 7;
Figure 14 represents ROM (read-only memory) overall construction drawing in embodiment 8.
Embodiment
In conjunction with following specific embodiments and the drawings, the present invention is described in further detail.Implement process of the present invention, condition, experimental technique etc., except the content of mentioning specially below, be universal knowledege and the common practise of this area, the present invention is not particularly limited content.
As shown in Figure 3, the method for minimizing ROM (read-only memory) leakage current of the present invention, comprises the steps: step 1: the sum that calculates the logical data of ROM (read-only memory) to be deposited; Step 2: the quantity of high level logic data in computational logic data; Step 3: logical data is deposited in ROM (read-only memory); If the quantity of high level logic data is greater than total half of logical data, will after logical data negate, deposit in ROM (read-only memory).
Because logical data " 0 " is relative with " 1 ", method of the present invention is not only applicable to reduce the situation of the number of high level logic data " 1 ", is equally applicable to reduce the number situation of data " 0 ".Except ROM (read-only memory), the storer based on two terminal device may be also other nonvolatile memory, and the leakage problem that they exist can adopt one or more methods of the present invention equally.Except leakage problem, the data confining force problem that ROM (read-only memory) or nonvolatile memory exist also may tend to reduce the number of data " 0 " or " 1 ", and these problems can be applied one or more methods of the present invention equally.
What Fig. 4 showed is to realize the ROM (read-only memory) of method and the structural representation of parts thereof that the present invention reduces ROM (read-only memory) leakage current, the ROM (read-only memory) wherein relating to is based on two terminal device, this embodiment comprises: at least one storage array, comprising word line and bit line, for stored logic data; Address decoder, it is connected with storage array, for select the bit line of storage array according to memory address; Sensor amplifier, all the other storage arrays connect, for amplifying the logical data on the selecteed bit line of output; The data input pin of storage array and sensor amplifier are provided with logic gate device.Logic gate device is not gate, after non-goalkeeper's logical data negate of data input pin, deposit in storage array, during data reading by negate after the data reading of sensor amplifier.
The present invention, also according to the ratio of high level logic data in partial logic block, deposits the logical data negate in this block in ROM (read-only memory).Therefore, in this embodiment, ROM (read-only memory) is further provided with address section judge module.Address section judge module is for judging the memory address of the logical data that needs negate.Logic gate device in ROM (read-only memory) is XOR gate, address section judge module is connected with XOR gate, when address interval judgement Module recognition needs the memory address of the logical data of negate, generate control signal and also input in XOR gate, for the logical data of memory address, carry out negate.
In the present invention, can also will after the logical data negate in ROM (read-only memory) middle finger position line to be deposited, deposit ROM (read-only memory) in.Correspondingly, a bit line is set in the storage array of ROM (read-only memory), stored logic negate signal on bit line more; Logic negate signal when the logical data on word line is read on word line is read simultaneously, logic gate device according to logic negate signal to logical data negate.
Preferably, deposit in ROM (read-only memory) after can partial logic data being changed according to mapping principle.Correspondingly, this embodiment further comprises data-mapping unit, and it deposits in storage array after logical data to be stored being shone upon according to mapping principle, and the logical data of output is reflected and penetrated.
Embodiment 1:
In the present embodiment, by provide low-impedance path to realize to leakage current, reduce the impact that leakage current reads data.As shown in Figure 5, in order to make do not have selected bit line as far as possible few to the electric current of the word line of choosing, WL0～WL4 provides does not equidistantly have selected bit line BL1 to the current path on ground, this is reduced to 1/6. original word line WL1 by the electric current that makes to flow on selected WL5, the introducing of WL2 and WL3, will increase extra height; But the area that this metal than word line connects is little more than 2 times, reason is that the connection of the metal of word line needs extra spacing, and the drop-down word line and the original word line that directly increase are identical, do not have the increase of spacing.If consider that bit line is used metal routing conventionally, resistance is little, WL1, WL2 and WL3 can directly be moved to the two ends of bit line BL1, directly utilize many of storage array edge to fill word line (dummy BL) parallel connection, can not only complete essentially identical function, and take full advantage of filling word line, not increase any area.
Embodiment 2:
Because the high level data of storing represents with data " 1 ", the two terminal device of storage data 1 easily produces leakage current.So in the present embodiment, by the sum of the data " 1 " in each byte of statistics, if sum is than a half of data sum, each data in bytes all in ROM (read-only memory) are carried out storing after negate, thereby effectively reduce the quantity of data 1 in ROM (read-only memory), total leakage current will obviously reduce.For example, the analysis of the sample data of a 25Mb shows, the summation of data " 1 " accounts for 70% of total memory capacity, and all, after negates storage, the sum of data " 1 " will be reduced to 30%, and leakage current is original 3/7 by being reduced to, 42.9%.
In reading embodiment 2, during the data of storage, need all data again after negate, read, at most only need two-stage gate delay, very little on the impact of reading speed.
Embodiment 3
The present embodiment is the further refinement of embodiment 2, and according to the summation of the data " 1 " in every of each byte of statistics, then, by one or several the negates storages outnumbering certain ratio of data " 1 ", leakage current will be improved.If the data of storing in storage array are databases, and in database, have a large amount of negatives, the most significant digit data of negative are with 1 expression, in the most significant digit of 8 or 16 or 32 bit data, having a large amount of 1 occurs, in the present embodiment, will after the most significant digit data-conversion of 8 or 16 or 32 bit data, store, thereby effectively reduce the sum of data 1, reduced total leakage current.Similarly, in reading embodiment 2, during the data of storage, need all data again after negate, read, at most only need two-stage gate delay, very little on the impact of reading speed.
Embodiment 4
In the present embodiment, the rule showing in storage array according to data, by data according to the data on himself rule negate word line or bit line.For example, by statistics, show that 1 in odd number or even bitlines is obviously than more than 0, or 1 in odd number or even wordline is obviously than more than 0, data-conversion storage on these bit lines or word line will contribute to leakage current to reduce, after this data-conversion, only need be according to the neat even rule of word line or bit line address, negate sensor amplifier output data can obtain correct data; Owing to judging that address and read operation are parallel, this method is very little on the impact of reading speed.
Embodiment 5:
In the present embodiment, by finding out between word line or bitline regions single or continuous in storage array, will after their data-conversion, store.Take word line as example, if in storage array on many continuous word lines or on many single word lines great majority be all data 1, after the storage of these data-conversions, leakage current also will reduce.
As shown in Figure 6, address is when giving address decoder, and whether the data that address section judge module can judge this address negate.If negate, address section judge module can be controlled the data of sensor amplifier output negate.For example, the analysis of a sample data shows, the ratio that the continuation address region of data complete 1 accounts for total data 1 is 23.8%, and after negate storage, the impact of leakage current will obviously reduce.Because judgement and the read operation of address section are parallel, the method for Fig. 6 does not affect reading speed, and address section judgement only needs simple logic, and the increase of area also can be controlled very littlely.
As shown in Figure 7, storage array has increased a bit line BLe, if the data-conversion on word line, BLe is communicated with to the two terminal device of this root word line, as shown in WL1, otherwise disconnects, as WL2 and WL3.In sense data, the data on BLe are read simultaneously, if the data of BLe are 1, and the output data of negate sensor amplifier, if the data of BL3 are 0, the output data of not negate sensor amplifier.Owing to only increasing a bit line, and reading with other bit line of this root bit line read simultaneously, and method shown in Fig. 7 is all very little on the impact of Area and Speed.
Embodiment 6:
In the present embodiment, first data are carried out to man-to-man mapping, then the data after Storage Mapping.As shown in Figure 8, raw data, before store storage array, is first shone upon one to one.For the byte data of 8, this possible be mapped with one to one 256! (256 factorials) plant, and any man-to-man mapping is all feasible in principle.What in this embodiment, realize is to have detection data " 0 " and 1 mapping one to one changing.
Table 1 is depicted as take a kind of mapping one to one that 4 bit data are example; Store by raw data on first, the left side of data, if left side second data are identical with the first bit data, becomes 0, otherwise be 1; If the left side the 3rd bit data is identical with second data, becomes 0, otherwise be 1; The rest may be inferred carries out xor operation successively to data.8 mode conversions that can directly press table 1 of actual byte data, also can divide 24 bit data to convert respectively, are even divided into 42 bit data and convert respectively; The mode of packet can be both to close on multidigit to divide mode in groups together, can be also neat several multidigits or the even number multidigit packet mode together jumping; The order of conversion can be both from left to right, can be also from right to left; The transform method of 16 or 32 bit data can the rest may be inferred and combination.As can be seen from Table 1, this mapping one to one can become the few data of data " 1 " number by the data of continuous a plurality of data " 1 ", it is many that the data of continuous a plurality of data " 0 " remain data " 0 ", but data " 0 " and 1 data that alternately change frequency is many will become more than the data of original data " 1 " number.If raw data is regarded as to a random series, this mapping one to one can detect the continuous data " 0 " of different length of this random series and continuous data " 1 " number, if the random number word string of continuous data " 0 " or 1 is a lot, this mapping will obviously reduce the number of data " 1 ", and then reduce leakage current; So the validity of this mapping depends on the random character of original random series.
Table 1 be take the table of mapping relations one to one that 4 bit data are example
In this embodiment, also encryption and decryption control module can be further set; Encryption and decryption control module is connected with address decoder or sensor amplifier, for the logical data of input being encrypted and the logical data of output being decrypted.
As shown in Figure 9, the method for minimizing ROM (read-only memory) leakage current of the present invention, comprises the steps: step 1: the memory address of obtaining high level logic data in the logical data of ROM (read-only memory) to be deposited; Step 2: the memory address of high level logic data is converted in the memory cell array of ROM (read-only memory) to the address with a line or same array storage unit; Step 3: logical data is deposited in ROM (read-only memory) by the address after changing.
What Figure 10 showed is to realize the ROM (read-only memory) of method and the structural representation of parts thereof that the present invention reduces ROM (read-only memory) leakage current, comprising at least one storage array, comprising word line and bit line, for stored logic data; Address decoder, it is connected with storage array, for select the bit line of storage array according to memory address; Sensor amplifier, it is connected with storage array, for amplifying the logical data on the selecteed bit line of output; Address mapper, it is connected with address decoder, for memory address is shone upon; Address map decode device, it is connected with sensor amplifier, for memory address is reflected and penetrated.
Embodiment 7:
By leakage current in the present embodiment, affect equiblibrium mass distribution in different storage arrays.When the DeGrain of above-mentioned several method, by check each storage array in the distribution situation of total data " 1 ", the situation that judges whether to exist the data " 1 " in different storage arrays to differ greatly, then work out corresponding address mapping scheme, data are redistributed to each different storage array.The data that represent Figure 11 and Figure 12 store the schematic diagram of two kinds of different mappings methods in two storage arrays into.
As shown in figure 11, be first filled with in order storage array 1, more remaining data are put in storage array 2.As shown in figure 12, by the order of jumping, data are stored in two storage arrays.Actual storage array number can be more, and the jumping mode of data storage also has a variety of, according to the distribution situation of the data of customer data " 0 " and 1, selects corresponding mapping method.As shown in figure 13, actual circuit only needs some simple decoding and MUX to relevant steering logic, can complete multiple possible mapping; These circuit are simple, and not only area is little, and decoding scheme is not in critical path, just increased the two-stage gate delay of MUX readout time.
Embodiment 8:
The general frame of the ROM (read-only memory) in the present embodiment as shown in figure 14, storage array is the matrix of storage unit, row address decoder is chosen the word line that will access according to Input Address, column address decoder is chosen the bit line that will access according to Input Address, sensor amplifier reads selected word line and the data on bit line; Address control register is stored various leakage currents and is reduced the required address control information of measure, and address decoding controller is controlled the function of row and column address decoder according to the information of address control register; Read control register storage leakage current and reduce the required data control information of measure, read-out controller is adjusted the data of sensor amplifier output according to the content of reading control register.Address control register and read control register and need to be configured by control signal and Input Address chip power after, only has and has inputted correct configuration information, and data could be exported with correct content in the correct order.When address control register with read control register incorrect time, ROM (read-only memory) of the present invention still can be worked as a normal memory, and just order and the content of data are wrong; Crack a kind of like this ROM (read-only memory), the combination that not only will enumerate various registers, and will guess whether right the data of reading are on earth, exists to have obtained correct data and but think wrong possibility completely.Although so this encryption method is simple, very effective.Consider that again the mixing that various leakage currents reduce measure used, address control register and read that the position of control register is long can be long, the difficulty cracking further increases.
Diversity due to storage data, the inventive method can be the combination of above-mentioned the whole bag of tricks, concrete array mode determines by data, and the hardware setting of ROM (read-only memory) is respective change also, and by address decoding control register with read control register and be configured and encrypt.
Protection content of the present invention is not limited to above embodiment.Do not deviating under the spirit and scope of inventive concept, variation and advantage that those skilled in the art can expect are all included in the present invention, and take appending claims as protection domain.
Claims (6)
1. a method that reduces ROM (read-only memory) leakage current, is characterized in that, comprises the steps:
Step 1: the sum that calculates the logical data of ROM (read-only memory) to be deposited;
Step 2: the quantity of calculating high level logic data in described logical data;
Step 3: described logical data is deposited in described ROM (read-only memory); If the quantity of described high level logic data is greater than total half of described logical data, will after described logical data negate, deposit in described ROM (read-only memory).
2. the method for minimizing ROM (read-only memory) leakage current as claimed in claim 1, it is characterized in that, further comprise: the quantity of high level logic data in calculating section logical data block, if the quantity of described high level logic data is greater than a total half of logical data in described partial logic block, will after the logical data negate in described partial logic block, deposit in described ROM (read-only memory).
3. the method for minimizing ROM (read-only memory) leakage current as claimed in claim 1, is characterized in that, further comprises step 4: from described ROM (read-only memory), read and outputting logic data; If described logical data is negate before storage, read and reduce after described logical data and export.
4. the method for the minimizing ROM (read-only memory) leakage current as described in any one of claim 1 or 2, it is characterized in that, further comprise: if the quantity of described high level logic data is greater than total half of described logical data, described logical data is deposited in described ROM (read-only memory) after mapping principle is changed.
5. the method for minimizing ROM (read-only memory) leakage current as claimed in claim 4, is characterized in that, reads and outputting logic data from described ROM (read-only memory); If described logical data through conversion, reads and reduces after described logical data and export according to described mapping principle before storage.
6. a method that reduces ROM (read-only memory) leakage current, is characterized in that, comprises the steps:
Step 1: the memory address of obtaining high level logic data in the logical data of ROM (read-only memory) to be deposited;
Step 2: the memory address of described high level logic data is converted in the memory cell array of described ROM (read-only memory) to the address with a line or same array storage unit;
Step 3: described logical data is deposited in described ROM (read-only memory) by the address after changing.
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