CN103745057B - In FPGA, carry out the logical block packing method of electric design automation - Google Patents
In FPGA, carry out the logical block packing method of electric design automation Download PDFInfo
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Abstract
The invention discloses the logical block packing method that carries out electric design automation in a kind of FPGA, mainly solve the rear circuit time delay of prior art vanning excessive, configurable logic cell CLB consumes too much problem. Its vanning process is: by Technology Mapping, dividing elements circuit after treatment represents with directed acyclic graph; By the connected mode between question blank LUT in circuit, the Delay in directed acyclic graph is initialized; Calculate the shatter value of each node by breadth First traversal, and the impact of circuit critical path is calculated to its crucial degree in conjunction with each node; According to the crucial degree of each node and in conjunction with the gauze number having used in the gauze number of question blank LUT and configurable logic cell CLB, calculate the gauze yield value of each question blank LUT, according to gauze yield value, question blank LUT is selected to load. The present invention has greatly reduced the time delay of final circuit, has greatly reduced the quantity of the configurable logic cell CLB of final circuitry consumes simultaneously.
Description
Technical field
The invention belongs to field of computer technology, particularly a kind of electric design automation design vanning packaging method,Can be used for isomorphism, the application design of the multiple fpga chip such as isomery.
Background technology
The mid-80, first Xilinx company of the U.S. has released FPGA FPGA, it beThe product further developing on the basis of programmable logic array PLA and GAL GAL. Along with integrated electricThe deep-submicron manufacturing technology on road and developing rapidly of designing technique, integrated circuit has entered the system-level SOC epoch.The FPGA of 1,000,000 Virtex series that Xilinx company releases, for resolution system level design problem provides newFPGA platform. At present, designing technique and the processing technology maturation of external FPGA, product is covering extensive fields, canUp to a hundred series of products are provided, and chip integration has reached door up to a million, and be widely used in communication, space flight, aviation,The national defence fields such as navigation, remote sensing, remote measurement. The company monopolizings such as U.S. Xilinx, Altera, Lattice and ActelPLD market, the whole world. And it is not domestic chip develops substantially in the poor and underdeveloped stage, autonomousThe core process technology of property right, so it is very urgent to research and develop the autonomous fpga chip of China.
Use fpga chip must have the electronic design automation software of supporting FPGA exploitation, exploitation is based on FPGAThe design cycle of electronic design automation software comprise: logic synthesis, Technology Mapping, dividing elements, logical blockVanning, layout, wiring, the steps such as program downloads, as shown in Figure 1. Wherein:
Net table is optimized, and for realizing the logic of eliminating redundancy, reduces the actual required area of circuit;
Technology Mapping, for the net table after optimizing is converted into the circuit being made up of question blank LUT and timing unit,Realize under the condition that meets input constraint, more combinational logic is put into a question blank LUT, to reduceThe capacity of required FPGA;
Dividing elements, for scale being exceeded to the LUT integrated unit of FPGA capacity, is divided into several can dividingDo not put the little LUT unit group in given FPGA into;
Logical block vanning, for according to the interconnection Delay between the LUT unit group after dividing, calculates LUTBetween interconnect delay and calculate the weighted value of each LUT, then according to the size of weighted value, LUT is sorted,Case in configurable logic cell CLB in order successively in LUT unit one by one;
Layout, for each logical place to actual FPGA by the CLB unit maps after vanning, to reachReduce the stagger ratio of line between CLB, alleviate the pressure of interconnect module;
Wiring, adopts the interconnection resources that FPGA inside has existed to connect each connection between CLB for realizingConnect, whole circuit is mapped completely on given fpga chip;
Coding is downloaded, and the circuit having shone upon according to wiring, generates the bit data stream file that will use by compiling, soAfter this data file is downloaded in fpga chip.
Described logical block is cased, and conventionally depends on the structure of FPGA, and at present popular FPGA structure justBe inner containing multiple queries table LUT at a configurable logic cell CLB, between these question blanks LUT, share defeatedEnter, their output simultaneously also can feed back to input by ICR interconnect resource. Existing logical block packing method baseOriginally be divided into following two kinds:
A delay performance that improves final circuit by the quantity of sacrifice configurable logic cell CLB, for exampleT-vpack logical block packing method, the method is exactly to calculate to improve by backtracking repeatedly in the calculation delay stageThe time delay of final circuit,, after each question blank LUT has been loaded, all can go the time delay to whole circuitInformation is upgraded, and calculates the corresponding time delay weights of question blank LUT simultaneously. Although this method can ensure circuitDelay performance efficient, but the area to final circuit not, the number of the configurable logic cell CLB consumingAmount is carried out good optimal control, makes to be finally loaded into the configurable logic list of the circuitry consumes on FPGA development boardCLB is too much in unit.
Another kind is the configurable logic cell CLB consumption that reduces final circuit by the delay performance of sacrifice circuit,For example R-pack logical block packing method, the method is by final circuitry consumes configurable logic cell CLBNumber, and fills question blank LUT in order to ensure the question blank LUT packing of casing as primary optimization aimThe continuity of case, does not carry out backtracking renewal in the calculation delay stage to the Delay of circuit. Though this method is ensureingIn the situation that question blank LUT loads continuously, can fully control the configurable logic cell CLB's of final circuitry consumesQuantity, but ignored the guarantee to circuit final delay performance, make to be finally loaded into the electricity on FPGA development boardRoad is long running time.
Summary of the invention
The object of the invention is to the deficiency for above-mentioned prior art, propose to carry out Electronic Design certainly in a kind of FPGAThe logical block packing method of movingization, to consider the final delay performance of circuit and the configurable logic of consumptionThe quantity of unit CLB, makes final design circuit out reach high as far as possible performance.
The technical scheme that realizes the object of the invention, comprises the steps:
A. the crucial degree B of each question blank LUT in counting circuit:
(A1) will be through Technology Mapping, dividing elements circuit after treatment, should as a directed acyclic graph DAGNode in directed acyclic graph represents to have the question blank LUT of memory circuit logic function; Limit in directed acyclic graphRepresent the gauze line between question blank LUT, according to the actual annexation between question blank LUT to directed acyclicUpper corresponding time delay weighted value is composed on every limit in figure;
(A2), from the source node of circuit, according to the corresponding time delay weighted value in limit in directed acyclic graph, adoptThe Ta time of advent the latest (i) that calculates node i in directed acyclic graph by the method for breadth First traversal, wherein i representsThe label of i node in directed acyclic graph, the span of i is 1～N, the sum of node in N indication circuit,The input of node i is In (i) expression for node set, and the node sum in set In (i) represents with e1, the output of node iOn for node set (i) expression, the node sum in set On (i) represents with e2;
(A3), from the endpoint node of circuit, in conjunction with every time delay weighted value that limit is corresponding, adopt breadth FirstWhat the method for traversal calculated node i in directed acyclic graph needs to reach time T r (i) the latest;
(A4) according to the Ta time of advent the latest (i) of node i in the directed acyclic graph obtaining with while needing to reach the latestBetween Tr (i), obtain shatter value corresponding to node i: s (i)=Tr (i)-Ta (i);
(A5) according to the time ductility of node i in shatter value calculating directed acyclic graph: C (i)=1-s (i)/Ms, wherein MsRepresent the maximum of all node shatter values in directed acyclic graph;
(A6) calculate the affect weights of node i on critical path in directed acyclic graph:
TA(i)＝IA(i)+OA(i)，
Wherein: IA (i) represents the node sum of the corresponding input node of node i in critical path, and OA (i) represents jointThe node sum of the corresponding output node of some i in critical path;
(A7) according to time ductility C (i) and the affect weights of this node on critical path in directed acyclic graph of node iTA (i), the crucial degree of computing node i:Wherein
B. select question blank LUT to be loaded into new configurable logic cell CLB:
(B1) sort for the crucial degree of the each node obtaining in step (A7), select crucial degreeThe corresponding question blank LUT of that high node, is filled in a new configurable logic cell CLB and goes;
(B2) the question blank LUT being loaded in configurable logic cell CLB is labeled as to H, calculates and H phaseThe gauze associated gain I (j) of j the question blank LUT connecting, wherein j represents j the inquiry being connected with HTable LUT, the span of j is 1～M, M represents total number of the question blank LUT being connected with H;
(B3) the associated yield value I of the gauze of all question blank LUT that calculate (j) is sorted, select lineThat question blank LUT of gateway connection yield value maximum is filled in above-mentioned new configurable logic cell CLBGo;
(B4) repeating step (B2) and step (B3), until above-mentioned new configurable logic cell CLB is filled outTill filling;
C. refresh circuit Delay, continues question blank LUT to load:
(C1) loaded full configurable logic cell CLB for one, according in it and circuit, other are looked intoAsk the connected mode of table LUT, reset the time delay weighted value on limit in circuit, form new directed acyclic graph DAG ';
(C2) utilize new directed acyclic graph DAG ', repeating step (A2) and step (B4), until circuitIn till all question blank LUT have been loaded.
The present invention compared with prior art institute's tool has the following advantages:
(1) the present invention is in the time selecting question blank LUT to be loaded into new configurable logic cell CLB, by calculatingThe method of the associated gain of gauze is selected question blank LUT, makes the space in configurable logic cell CLB canTo be utilized fully, reduce the quantity that uses configurable logic cell CLB;
(2) the present invention carries out overall renewal to the Delay of circuit in vanning process, when have one configurableLogical block CLB loaded full after, according to the connected mode of other question blanks LUT in it and circuit, recalculateThe time delay weighted value on limit in circuit, makes the delay of final circuit reach optimum, has reduced circuit final running time.
Brief description of the drawings
Fig. 1 is the existing flow chart that carries out automatic electronic design in FPGA;
Fig. 2 is that whole vanning of the present invention realizes general flow chart;
Fig. 3 is the crucial degree sub-process figure that calculates whole circuit question blank LUT in the present invention;
Fig. 4 is that in the present invention, the crucial degree according to question blank LUT is selected the sub-process figure loading.
Detailed description of the invention
With reference to Fig. 2, performing step of the present invention is as follows:
Step 1, will be through Technology Mapping, and dividing elements circuit after treatment is set to directed acyclic graph DAG.
Technology Mapping is that circuit is converted into question blank LUT integrated unit, if the scale of this integrated unit is superCross the capacity of FPGA, will question blank LUT integrated unit be divided into multiple can putting into by dividing elementsQuestion blank LUT unit group in given FPGA. Because this unit group is to interconnect group by multiple queries table LUTBecome, therefore this circuit can be regarded as to a directed acyclic graph DAG, in circuit, will there is memory circuit logic meritThe question blank LUT of energy regards a node in directed acyclic graph as, and the gauze line between question blank LUT is seenOne-tenth is the limit in directed acyclic graph;
According to the annexation between question blank LUT, upper corresponding time delay weight is composed in every limit in directed acyclic graphValue, in this example directed acyclic graph, the time delay weighted value on all limits is set to 0.1.
Step 2, the crucial degree of each question blank LUT in counting circuit, the i.e. pass of each node in directed acyclic graphKey degree B:
With reference to Fig. 3, being achieved as follows of this step:
(2a) adopt the method for breadth First traversal calculate node i in directed acyclic graph the Ta time of advent the latest (i) andNeed the latest to reach time T r (i), wherein i represents the label of i node in directed acyclic graph, the span of iBe 1～N, the sum of node in N indication circuit:
(2a1) the input node set of establishing node i is In (i), and the node sum in set In (i) represents with e1, jointThe output node set of point i is On (i), and the node sum in set On (i) represents with e2;
(2a2), from the source node of circuit, calculate directed acyclic graph in conjunction with every time delay weighted value corresponding to limitThe time of advent the latest of middle node i:
Ta(i)＝max{Ta(m)+t(m,i)}，
Wherein m represents m node in the input node set In (i) of node i, and the span of m is: 1～e1;T (m, i) represents the time delay weighted value between node i in m node in set In (i) and directed acyclic graph;
(2a3), from the endpoint node of circuit, calculate directed acyclic graph in conjunction with every time delay weighted value corresponding to limitMiddle node i need the latest to reach the time:
Tr(i)＝min{Tr(n)-t(i,n)}，
Wherein n represents n node in the output node set On (i) of node i, and the span of n is: 1～e2;T (i, n) represents the time delay weighted value between the node i in n node and the directed acyclic graph in set On (i);
(2b) according to the Ta time of advent the latest (i) of node i in the directed acyclic graph obtaining with need the latest to reach the timeTr (i), obtains the shatter value of node i: s (i)=Tr (i)-Ta (i);
(2c) according to the time ductility of node i in shatter value calculating directed acyclic graph:
C(i)＝1-s(i)/Ms，
Wherein Ms represents the maximum of all node shatter values in directed acyclic graph;
(2d) calculate the affect weights of node i on critical path in directed acyclic graph:
TA(i)＝IA(i)+OA(i)，
Wherein: IA (i) represents the node sum of the corresponding input node of node i in critical path, and OA (i) represents jointThe node sum of the corresponding output node of some i in critical path;
(2e) according to time ductility C (i) and the affect weights of this node on critical path in directed acyclic graph of node iTA (i), the crucial degree of computing node i:Wherein
Step 3, selects question blank LUT, and is loaded into new configurable logic cell CLB.
With reference to Fig. 4, being achieved as follows of this step:
(3a) the crucial degree of the each node obtaining in step (2e) is sorted, select crucial degree the highestThe corresponding question blank LUT of that node, is filled in a new configurable logic cell CLB and goes;
(3b) the question blank LUT of above-mentioned filling is labeled as to H, continues to select other question blank LUT to be filled intoIn above-mentioned configurable logic cell CLB:
(3b1) the associated gain of the gauze I (j) of j the question blank LUT that calculating is connected with H:
(3b11) the gauze weights of j question blank LUT of calculating:
w(j)＝2.0/k，
Wherein k represents the gauze sum of j question blank LUT; J represents j the question blank being connected with HThe label of LUT, the span of j is 1～M; M represents total number of the question blank LUT being connected with H;
(3b12) according to the gauze weight w (j) of j the question blank LUT obtaining, calculate j question blank LUTGauze gain:
I(j)＝μ*w(j)*(1+a)，
Wherein, a represents j question blank LUT and the affiliated shared gauze of configurable logic cell CLB of HNumber, H is the question blank LUT being loaded in configurable logic cell CLB, μ represents gauze gain coefficient, whenWhen the gauze of j question blank LUT is all comprised in the configurable logic cell CLB under H, the value of μBe 10.0, otherwise the value of μ is 1.0;
(3b2) the associated yield value I of the gauze of all question blank LUT that obtain (j) is sorted, select gauze to closeThat question blank LUT of connection yield value maximum, is filled in above-mentioned new configurable logic cell CLB and is gone;
(3c) repeating step (3b), until above-mentioned new configurable logic cell CLB is loaded completely;
(3d) refresh circuit Delay, continues question blank LUT to load:
(3d1) loaded full configurable logic cell CLB for one, according in it and circuit, other are looked intoAsk the connected mode of table LUT, by the time delay weighted value of the gauze line between question blank LUT in this CLB againBe set to 1.0, form new directed acyclic graph DAG ';
(3d2) utilize new directed acyclic graph DAG ', repeating step 2 and step 3, until all looking in circuitTill inquiry table LUT has been loaded, whole vanning process finishes.
After whole vanning process finishes, enter the FPGA electric design automation layout stage, what be about to form joinsPut logical block CLB unit maps to each logical place of FPGA, with reduce configurable logic cell CLB itBetween the stagger ratio of line, adequately and reasonably utilize existing resource on FPGA development board.
Effect of the present invention can be by following emulation experiment further instruction
1. simulated conditions
Select in international standard circuit through Technology Mapping and dividing elements instrument ABC large-scale circuit after treatment
2. emulation content
Through Technology Mapping and dividing elements large mould rule circuit after treatment, adopt respectively vanning side of the present invention by above-mentionedMethod and in the world conventional T-vpack packing method carry out emulation experiment, and the circuit after vanning is added up respectively to theirsTime delay and area result. Wherein time delay represents the length in final circuit critical path, and it has determined that this circuit is finalRunning time; The number of the configurable logic cell CLB that the final circuit of cartographic represenation of area will be used.
Each emulation repeats 20 times, and the simulation experiment result is averaged, and obtains two kinds of method simulation comparisons, as tableShown in 1:
The result contrast of table 1 packing method of the present invention and existing T-vpack packing method
As can be seen from Table 1, aspect area, packing method of the present invention is better than T-vpack packing method, finally totalArea result improved 1.5%; Aspect time delay, the handled circuit of the present invention is also better than the result of T-vpack,Final total time delay result has improved 5.8%.
Show according to above emulation experiment and data result, the present invention has considered shadow in the vanning process to circuitRing the factor of circuit time delay and area, when the Delay to circuit of the overall situation upgrades, also consideredIn filling process, use the situation of configurable logic cell CLB, adopted the method for calculating gauze gain to question blankLUT selects to load, and makes the time delay of final circuit and two important performance indexes of area all obtain significantly and carryHigh.
Claims (3)
1. a logical block packing method that carries out electric design automation in FPGA, comprises the steps:
A. the crucial degree B of each question blank LUT in counting circuit:
(A1) will be through Technology Mapping, dividing elements circuit after treatment is as a directed acyclic graph DAG,Node in this directed acyclic graph represents to have the question blank LUT of memory circuit logic function; Directed acyclic graphIn limit represent the gauze line between question blank LUT, according to the actual annexation between question blank LUTUpper corresponding time delay weighted value is composed in every limit in directed acyclic graph;
(A2) from the source node of circuit, according to the corresponding time delay weighted value in limit in directed acyclic graph,Adopt the method for breadth First traversal to calculate the Ta time of advent the latest (i) of node i in directed acyclic graph:
Ta(i)＝max{Ta(m)+t(m,i)}，
Wherein m represents m node in the input node set In (i) of node i, and the span of m is:1～e1; T (m, i) represents that in m node in set In (i) and directed acyclic graph, the time delay between node i is weighedHeavily value, i represents the label of i node in directed acyclic graph, and the span of i is 1～N, and N represents electricityThe sum of node in road, the input of node i is In (i) expression for node set, and the node sum in set In (i) is usedE1 represents, the output node of node i for set On (i) represent, the node sum in set On (i) represents with e2;
(A3), from the endpoint node of circuit, in conjunction with every time delay weighted value that limit is corresponding, adopt rangeWhat the method for preferential traversal calculated node i in directed acyclic graph needs to reach time T r (i) the latest:
Tr(i)＝min{Tr(n)-t(i,n)}，
Wherein n represents n node in On (i) in the output node set of node i, and the span of n is:1～e2; T (i, n) represents that in n node in set On (i) and directed acyclic graph, the time delay between node i is weighedHeavily value;
(A4) according to the Ta time of advent the latest (i) of node i in the directed acyclic graph obtaining with need the latest to reachTo time Tr (i), obtain shatter value corresponding to node i: s (i)=Tr (i)-Ta (i);
(A5) according to the time ductility of node i in shatter value calculating directed acyclic graph: C (i)=1-s (i)/Ms,Wherein Ms represents the maximum of all node shatter values in directed acyclic graph;
(A6) calculate the affect weights of node i on critical path in directed acyclic graph:
TA(i)＝IA(i)+OA(i)，
Wherein: IA (i) represents the node sum of the corresponding input node of node i in critical path, OA (i) tableShow the node sum of the corresponding output node of node i in critical path;
(A7) according to time ductility C (i) and the impact power of this node on critical path in directed acyclic graph of node iValue TA (i), the crucial degree of computing node i:WhereinGet 0.01;
B. select question blank LUT to be loaded into new configurable logic cell CLB:
(B1) sort for the crucial degree of the each node obtaining in step (A7), select keySpend the highest corresponding question blank LUT of that node, be filled into a new configurable logic cell CLBIn go;
(B2) the question blank LUT being loaded in configurable logic cell CLB is labeled as to H, calculates and HThe gauze associated gain I (j) of j the question blank LUT being connected, wherein j represents the j being connected with HIndividual question blank LUT, the span of j is 1～M, M represents total of the question blank LUT being connected with HNumber;
(B3) the associated yield value I of the gauze of all question blank LUT that calculate (j) is sorted, choosingThat question blank LUT that selects the associated yield value maximum of gauze is filled into above-mentioned new configurable logic cellIn CLB, go;
(B4) repeating step (B2) and step (B3), until above-mentioned new configurable logic cell CLBTill being loaded completely;
C. refresh circuit Delay, continues question blank LUT to load:
(C1) loaded full configurable logic cell CLB for one, according in it and circuit itsThe connected mode of he question blank LUT, resets the time delay weighted value on limit in circuit, forms new oriented nothingRing figure DAG ';
(C2) utilize new directed acyclic graph DAG ', repeating step (A2) and step (B4), untilTill in circuit, all question blank LUT have been loaded.
2. packing method according to claim 1, calculates and question blank LUTH in wherein said (B2)The gauze associated gain I (j) of j the question blank LUT being connected, carries out as follows:
(B21) the gauze weights of j question blank LUT of calculating:
w(j)＝2.0/k，
Wherein k represents the gauze sum of j question blank LUT;
(B22) according to the gauze weights of j the question blank LUT obtaining, calculate j question blank LUTGauze gain:
I(j)＝μ*w(j)*(1+a)，
Wherein, a represents what j question blank LUT and the affiliated configurable logic cell CLB of H were sharedGauze number, H is the question blank LUT being loaded in configurable logic cell CLB, u represents gauze gainCoefficient, the configurable logic cell CLB under the gauze of j question blank LUT is all comprised in HWhen middle, the value of u is 10.0, otherwise the value of u is 1.0.
3. packing method according to claim 1, resets limit in circuit in wherein said (C1)Time delay weighted value: loaded full configurable logic cell CLB for one, according to it and circuitIn the connected mode of other question blanks LUT, by the gauze line between question blank LUT in this CLB timeProlong weighted value and be re-set as 1.0, form new directed acyclic graph DAG '.
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| CN112948323A (en) * | 2021-04-16 | 2021-06-11 | 山东高云半导体科技有限公司 | Memory mapping processing method and device and FPGA chip |
| CN115017844B (en) * | 2022-08-03 | 2022-11-08 | 阿里巴巴（中国）有限公司 | Design parameter adjusting method, device, electronic equipment and storage medium |
| CN115862052A (en) * | 2023-02-24 | 2023-03-28 | 北京芯愿景软件技术股份有限公司 | Method, device, equipment and storage medium for automatically identifying clock crossing circuit |
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